From ed9f67afe7a5f0e1e86a35f77de7b0d0bdea2c02 Mon Sep 17 00:00:00 2001 From: Filip Navara Date: Thu, 29 Apr 2004 17:06:21 +0000 Subject: [PATCH] - Initialize the serial port to reasonable state after the detection. (Needed by Virtual PC) svn path=/trunk/; revision=9244 --- reactos/hal/halx86/kdbg.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/reactos/hal/halx86/kdbg.c b/reactos/hal/halx86/kdbg.c index 61e5d42d04d..6e55bc2cec9 100644 --- a/reactos/hal/halx86/kdbg.c +++ b/reactos/hal/halx86/kdbg.c @@ -1,4 +1,4 @@ -/* $Id: kdbg.c,v 1.7 2003/12/28 22:38:09 fireball Exp $ +/* $Id: kdbg.c,v 1.8 2004/04/29 17:06:21 navaraf Exp $ * * COPYRIGHT: See COPYING in the top level directory * PROJECT: ReactOS kernel @@ -34,6 +34,10 @@ #define SR_IER_ALL 0x0F #define SER_DLM(x) ((x)+1) #define SER_IIR(x) ((x)+2) +#define SER_FCR(x) ((x)+2) +#define SR_FCR_ENABLE_FIFO 0x01 +#define SR_FCR_CLEAR_RCVR 0x02 +#define SR_FCR_CLEAR_XMIT 0x04 #define SER_LCR(x) ((x)+3) #define SR_LCR_CS5 0x00 #define SR_LCR_CS6 0x01 @@ -118,7 +122,18 @@ KdpDoesComPortExist (PUCHAR BaseAddress) * equal to the lower nibble of the MCR (modem input bits) */ if ((msr & 0xF0) == 0xF0) + { + /* + * setup a resonable state for the port: + * enable fifo and clear recieve/transmit buffers + */ + WRITE_PORT_UCHAR (SER_FCR(BaseAddress), + (SR_FCR_ENABLE_FIFO | SR_FCR_CLEAR_RCVR | SR_FCR_CLEAR_XMIT)); + WRITE_PORT_UCHAR (SER_FCR(BaseAddress), 0); + READ_PORT_UCHAR (SER_RBR(BaseAddress)); + WRITE_PORT_UCHAR (SER_IER(BaseAddress), 0); found = TRUE; + } } /* restore MCR */ -- 2.17.1