From fa9cd08b02fed8d1bd4c10a2f3119f22fa4157dd Mon Sep 17 00:00:00 2001 From: Sir Richard Date: Sat, 29 May 2010 19:27:32 +0000 Subject: [PATCH] Timo/Physicus: Please validate for AMD64. [NTOS]: Write down the PTE attribute flags for X86/AMD64. Timo/Physicus: Please double-check. [NTOS]: Write down the array that converts from the MM_ protection flags arleady defined, into the appropriate PTE attribute flags that are architecture-specific. [NTOS]: This will allow constant-time conversion of NT attributes into PTE attributes. Win32 attributes to NT attributes conversion won't be needed until VAD support. svn path=/trunk/; revision=47427 --- reactos/ntoskrnl/mm/ARM3/miarm.h | 84 ++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/reactos/ntoskrnl/mm/ARM3/miarm.h b/reactos/ntoskrnl/mm/ARM3/miarm.h index 4c5e3bc441b..a670bcdb3fd 100644 --- a/reactos/ntoskrnl/mm/ARM3/miarm.h +++ b/reactos/ntoskrnl/mm/ARM3/miarm.h @@ -89,6 +89,90 @@ #define MM_DECOMMIT 0x10 #define MM_NOACCESS (MM_DECOMMIT | MM_NOCACHE) +// +// Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits +// The Memory Manager's definition define the attributes that must be preserved +// and these PTE definitions describe the attributes in the hardware sense. This +// helps deal with hardware differences between the actual boolean expression of +// the argument. +// +// For example, in the logical attributes, we want to express read-only as a flag +// but on x86, it is writability that must be set. On the other hand, on x86, just +// like in the kernel, it is disabling the caches that requires a special flag, +// while on certain architectures such as ARM, it is enabling the cache which +// requires a flag. +// +#if defined(_M_IX86) || defined(_M_AMD64) +// +// Access Flags +// +#define PTE_READONLY 0 +#define PTE_EXECUTE 0 // Not worrying about NX yet +#define PTE_EXECUTE_READ 0 // Not worrying about NX yet +#define PTE_READWRITE 0x2 +#define PTE_WRITECOPY 0x200 +#define PTE_EXECUTE_READWRITE 0x0 +#define PTE_EXECUTE_WRITECOPY 0x200 +// +// Cache flags +// +#define PTE_ENABLE_CACHE 0 +#define PTE_DISABLE_CACHE 0x10 +#define PTE_WRITECOMBINED_CACHE 0x10 +#elif defined(_M_ARM) +#else +#error Define these please! +#endif +static const +ULONG +MmProtectToPteMask[32] = +{ + // + // These are the base MM_ protection flags + // + 0, + PTE_READONLY | PTE_ENABLE_CACHE, + PTE_EXECUTE | PTE_ENABLE_CACHE, + PTE_EXECUTE_READ | PTE_ENABLE_CACHE, + PTE_READWRITE | PTE_ENABLE_CACHE, + PTE_WRITECOPY | PTE_ENABLE_CACHE, + PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE, + PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE, + // + // These OR in the MM_NOCACHE flag + // + 0, + PTE_READONLY | PTE_DISABLE_CACHE, + PTE_EXECUTE | PTE_DISABLE_CACHE, + PTE_EXECUTE_READ | PTE_DISABLE_CACHE, + PTE_READWRITE | PTE_DISABLE_CACHE, + PTE_WRITECOPY | PTE_DISABLE_CACHE, + PTE_EXECUTE_READWRITE | PTE_DISABLE_CACHE, + PTE_EXECUTE_WRITECOPY | PTE_DISABLE_CACHE, + // + // These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM + // + 0, + PTE_READONLY | PTE_ENABLE_CACHE, + PTE_EXECUTE | PTE_ENABLE_CACHE, + PTE_EXECUTE_READ | PTE_ENABLE_CACHE, + PTE_READWRITE | PTE_ENABLE_CACHE, + PTE_WRITECOPY | PTE_ENABLE_CACHE, + PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE, + PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE, + // + // These OR in the MM_NOACCESS flag, which seems to enable WriteCombining? + // + 0, + PTE_READONLY | PTE_WRITECOMBINED_CACHE, + PTE_EXECUTE | PTE_WRITECOMBINED_CACHE, + PTE_EXECUTE_READ | PTE_WRITECOMBINED_CACHE, + PTE_READWRITE | PTE_WRITECOMBINED_CACHE, + PTE_WRITECOPY | PTE_WRITECOMBINED_CACHE, + PTE_EXECUTE_READWRITE | PTE_WRITECOMBINED_CACHE, + PTE_EXECUTE_WRITECOPY | PTE_WRITECOMBINED_CACHE, +}; + // // Assertions for session images, addresses, and PTEs // -- 2.17.1