reactos/hal/halx86/include/mps.h

   1 #ifndef __INCLUDE_HAL_MPS
   2 #define __INCLUDE_HAL_MPS
   3
   4 /*
   5  * FIXME: This does not work if we have more than 24 IRQs (ie. more than one
   6  * I/O APIC)
   7  */
   8 #define IRQL2VECTOR(irql)   (IRQ2VECTOR(PROFILE_LEVEL - (irql)))
   9
  10 #define IRQL2TPR(irql)      ((irql) >= IPI_LEVEL ? IPI_VECTOR : ((irql) >= PROFILE_LEVEL ? LOCAL_TIMER_VECTOR : ((irql) > DISPATCH_LEVEL ? IRQL2VECTOR(irql) : 0)))
  11
  12
  13 #if 0
  14 /* This values are defined in halirql.h */
  15 #define FIRST_DEVICE_VECTOR         0x30
  16 #define FIRST_SYSTEM_VECTOR         0xEF
  17 #endif
  18
  19 #define NUMBER_DEVICE_VECTORS       (FIRST_SYSTEM_VECTOR - FIRST_DEVICE_VECTOR)
  20
  21
  22 /* MP Floating Pointer Structure */
  23 #define MPF_SIGNATURE (('_' << 24) | ('P' << 16) | ('M' << 8) | '_')
  24
  25 #include <pshpack1.h>
  26 typedef struct _MP_FLOATING_POINTER
  27 {
  28         ULONG Signature;     /* _MP_ */
  29         ULONG Address;          /* Physical Address Pointer (0 means no configuration table exist) */
  30         UCHAR Length;           /* Structure length in 16-byte paragraphs */
  31         UCHAR Specification;    /* Specification revision       */
  32         UCHAR Checksum;         /* Checksum */
  33         UCHAR Feature1;         /* MP System Configuration Type */
  34         UCHAR Feature2;         /* Bit 7 set for IMCR|PIC */
  35         UCHAR Feature3;         /* Unused (0) */
  36         UCHAR Feature4;         /* Unused (0) */
  37         UCHAR Feature5;         /* Unused (0) */
  38 } MP_FLOATING_POINTER, *PMP_FLOATING_POINTER;
  39
  40
  41 #define FEATURE2_IMCRP  0x80
  42
  43 /* MP Configuration Table Header */
  44 #define MPC_SIGNATURE (('P' << 24) | ('M' << 16) | ('C' << 8) | 'P')
  45
  46 typedef struct _MP_CONFIGURATION_TABLE
  47 {
  48   ULONG Signature;     /* PCMP */
  49   USHORT Length;                /* Size of configuration table */
  50   CHAR  Specification;    /* Specification Revision */
  51   CHAR Checksum;          /* Checksum */
  52   CHAR Oem[8];            /* OEM ID */
  53   CHAR ProductId[12];     /* Product ID */
  54   ULONG OemTable;         /* 0 if not present */
  55   USHORT OemTableSize;    /* 0 if not present */
  56   USHORT EntryCount;      /* Number of entries */
  57   ULONG LocalAPICAddress; /* Local APIC address */
  58   USHORT ExtTableLength;  /* Extended Table Length */
  59   UCHAR ExtTableChecksum; /* Extended Table Checksum */
  60   UCHAR Reserved;         /* Reserved */
  61 } MP_CONFIGURATION_TABLE, *PMP_CONFIGURATION_TABLE;
  62
  63 /* MP Configuration Table Entries */
  64 #define MPCTE_PROCESSOR 0   /* One entry per processor */
  65 #define MPCTE_BUS       1   /* One entry per bus */
  66 #define MPCTE_IOAPIC    2   /* One entry per I/O APIC */
  67 #define MPCTE_INTSRC    3   /* One entry per bus interrupt source */
  68 #define MPCTE_LINTSRC   4   /* One entry per system interrupt source */
  69
  70
  71 typedef struct _MP_CONFIGURATION_PROCESSOR
  72 {
  73   UCHAR Type;         /* 0 */
  74   UCHAR ApicId;       /* Local APIC ID for the processor */
  75   UCHAR ApicVersion;  /* Local APIC version */
  76   UCHAR CpuFlags;     /* CPU flags */
  77   ULONG CpuSignature; /* CPU signature */
  78   ULONG FeatureFlags; /* CPUID feature value */
  79   ULONG Reserved[2];  /* Reserved (0) */
  80 }  MP_CONFIGURATION_PROCESSOR, *PMP_CONFIGURATION_PROCESSOR;
  81
  82
  83
  84 typedef struct  _MP_CONFIGURATION_BUS
  85 {
  86         UCHAR Type;         /* 1 */
  87         UCHAR BusId;        /* Bus ID */
  88         CHAR BusType[6];   /* Bus type */
  89 }  MP_CONFIGURATION_BUS, *PMP_CONFIGURATION_BUS;
  90
  91 #define MAX_BUS 32
  92
  93 #define MP_BUS_ISA  1
  94 #define MP_BUS_EISA 2
  95 #define MP_BUS_PCI  3
  96 #define MP_BUS_MCA  4
  97
  98 #define BUSTYPE_EISA      "EISA"
  99 #define BUSTYPE_ISA         "ISA"
 100 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
 101 #define BUSTYPE_MCA         "MCA"
 102 #define BUSTYPE_VL          "VL"                  /* Local bus */
 103 #define BUSTYPE_PCI         "PCI"
 104 #define BUSTYPE_PCMCIA  "PCMCIA"
 105 #define BUSTYPE_CBUS      "CBUS"
 106 #define BUSTYPE_CBUSII  "CBUSII"
 107 #define BUSTYPE_FUTURE  "FUTURE"
 108 #define BUSTYPE_MBI         "MBI"
 109 #define BUSTYPE_MBII      "MBII"
 110 #define BUSTYPE_MPI         "MPI"
 111 #define BUSTYPE_MPSA      "MPSA"
 112 #define BUSTYPE_NUBUS     "NUBUS"
 113 #define BUSTYPE_TC          "TC"
 114 #define BUSTYPE_VME         "VME"
 115 #define BUSTYPE_XPRESS  "XPRESS"
 116
 117
 118 typedef struct _MP_CONFIGURATION_IOAPIC
 119 {
 120         UCHAR Type;         /* 2 */
 121         UCHAR ApicId;       /* I/O APIC ID */
 122         UCHAR ApicVersion;  /* I/O APIC version */
 123         UCHAR ApicFlags;    /* I/O APIC flags */
 124         ULONG ApicAddress;  /* I/O APIC base address */
 125 } MP_CONFIGURATION_IOAPIC, *PMP_CONFIGURATION_IOAPIC;
 126
 127 #define MAX_IOAPIC  2
 128
 129 #define MP_IOAPIC_USABLE  0x01
 130
 131
 132 typedef struct _MP_CONFIGURATION_INTSRC
 133 {
 134         UCHAR Type;         /* 3 */
 135         UCHAR IrqType;      /* Interrupt type */
 136         USHORT IrqFlag;     /* Interrupt flags */
 137         UCHAR SrcBusId;     /* Source bus ID */
 138         UCHAR SrcBusIrq;    /* Source bus interrupt */
 139         UCHAR DstApicId;    /* Destination APIC ID */
 140         UCHAR DstApicInt;   /* Destination interrupt */
 141 }  MP_CONFIGURATION_INTSRC, *PMP_CONFIGURATION_INTSRC;
 142
 143 #define MAX_IRQ_SOURCE  128
 144
 145 #define INT_VECTORED    0
 146 #define INT_NMI         1
 147 #define INT_SMI         2
 148 #define INT_EXTINT      3
 149
 150 #define IRQDIR_DEFAULT  0
 151 #define IRQDIR_HIGH     1
 152 #define IRQDIR_LOW      3
 153
 154
 155 typedef struct _MP_CONFIGURATION_INTLOCAL
 156 {
 157         UCHAR Type;         /* 4 */
 158         UCHAR IrqType;      /* Interrupt type */
 159         USHORT IrqFlag;     /* Interrupt flags */
 160         UCHAR SrcBusId;     /* Source bus ID */
 161         UCHAR SrcBusIrq;    /* Source bus interrupt */
 162         UCHAR DstApicId;    /* Destination local APIC ID */
 163         UCHAR DstApicLInt;  /* Destination local APIC interrupt */
 164 } MP_CONFIGURATION_INTLOCAL, *PMP_CONFIGURATION_INTLOCAL;
 165 #include <poppack.h>
 166
 167 #define MP_APIC_ALL     0xFF
 168
 169 #define CPU_FLAG_ENABLED         1  /* Processor is available */
 170 #define CPU_FLAG_BSP             2  /* Processor is the bootstrap processor */
 171
 172 #define CPU_STEPPING_MASK  0x0F
 173 #define CPU_MODEL_MASK     0xF0
 174 #define CPU_FAMILY_MASK    0xF00
 175
 176 #define PIC_IRQS  16
 177
 178 /* Prototypes */
 179
 180 VOID HalpInitMPS(VOID);
 181
 182
 183 #endif /* __INCLUDE_HAL_MPS */
 184
 185 /* EOF */