reactos/ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * Lowlevel memory managment definitions
   3  */
   4
   5 #pragma once
   6
   7 /* Helper macros */
   8 #define PAGE_MASK(x)            ((x)&(~0xfff))
   9 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  10
  11 /* Memory layout base addresses */
  12 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  13 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  14 #define MI_SESSION_SPACE_MINIMUM        (PVOID)0xFFFFF90000000000ULL
  15 #define MI_SESSION_VIEW_END             (PVOID)0xFFFFF97FFF000000ULL
  16 #define MI_SESSION_SPACE_END            (PVOID)0xFFFFF98000000000ULL
  17 #define MI_SYSTEM_PTE_START             (PVOID)0xFFFFFAA000000000ULL
  18 #define MI_PAGED_POOL_START             (PVOID)0xFFFFFA8000000000ULL
  19 #define MI_NON_PAGED_SYSTEM_START_MIN          0xFFFFFAA000000000ULL
  20 #define MI_PFN_DATABASE                 (PVOID)0xFFFFFAC000000000ULL
  21 #define MI_NONPAGED_POOL_END            (PVOID)0xFFFFFAE000000000ULL
  22 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  23 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  24 #define MI_SYSTEM_CACHE_WS_START        (PVOID)0xFFFFF78000001000ULL // CHECKME
  25
  26 #define MI_LOWEST_VAD_ADDRESS           (PVOID)0x000000007FF00000ULL
  27
  28 #define MI_SYSTEM_PTE_BASE              (PVOID)MiAddressToPte(KSEG0_BASE)
  29
  30 /* Memory sizes */
  31 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  32 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
  33 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
  34 #define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128ULL * 1024 * 1024 * 1024)
  35 #define MI_MAX_NONPAGED_POOL_SIZE              (128ULL * 1024 * 1024 * 1024)
  36 #define MI_MAX_FREE_PAGE_LISTS                 4
  37 #define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
  38 #define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
  39 #define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
  40 #define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
  41 #define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
  42 #define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
  43                                                 MI_SESSION_POOL_SIZE + \
  44                                                 MI_SESSION_IMAGE_SIZE + \
  45                                                 MI_SESSION_WORKING_SET_SIZE)
  46 #define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
  47 #define MI_NUMBER_SYSTEM_PTES 22000
  48
  49 #define MI_MIN_SECONDARY_COLORS                 8
  50 #define MI_SECONDARY_COLORS                     64
  51 #define MI_MAX_SECONDARY_COLORS                 1024
  52
  53 #define MI_MIN_ALLOCATION_FRAGMENT              (4 * _1KB)
  54 #define MI_ALLOCATION_FRAGMENT                  (64 * _1KB)
  55 #define MI_MAX_ALLOCATION_FRAGMENT              (2  * _1MB)
  56
  57 #define MM_HIGHEST_VAD_ADDRESS \
  58     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  59
  60 PULONG64
  61 FORCEINLINE
  62 MmGetPageDirectory(VOID)
  63 {
  64     return (PULONG64)__readcr3();
  65 }
  66
  67 PMMPTE
  68 FORCEINLINE
  69 MiAddressToPxe(PVOID Address)
  70 {
  71     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
  72     Offset &= PXI_MASK << 3;
  73     return (PMMPTE)(PXE_BASE + Offset);
  74 }
  75
  76 PMMPTE
  77 FORCEINLINE
  78 MiAddressToPpe(PVOID Address)
  79 {
  80     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
  81     Offset &= 0x3FFFF << 3;
  82     return (PMMPTE)(PPE_BASE + Offset);
  83 }
  84
  85 PMMPTE
  86 FORCEINLINE
  87 _MiAddressToPde(PVOID Address)
  88 {
  89     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
  90     Offset &= 0x7FFFFFF << 3;
  91     return (PMMPTE)(PDE_BASE + Offset);
  92 }
  93 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
  94
  95 PMMPTE
  96 FORCEINLINE
  97 _MiAddressToPte(PVOID Address)
  98 {
  99     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
 100     Offset &= 0xFFFFFFFFFULL << 3;
 101     return (PMMPTE)(PTE_BASE + Offset);
 102 }
 103 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
 104
 105 ULONG
 106 FORCEINLINE
 107 MiAddressToPti(PVOID Address)
 108 {
 109     ULONG64 Pti = (ULONG64)Address >> PTI_SHIFT;
 110     Pti &= PTI_MASK_AMD64;
 111     return Pti;
 112 }
 113
 114 #define MiAddressToPteOffset(x) MiAddressToPti(x)
 115
 116 /* Convert a PTE into a corresponding address */
 117 PVOID
 118 FORCEINLINE
 119 MiPteToAddress(PMMPTE Pte)
 120 {
 121     /* Use signed math */
 122     LONG64 Temp = (LONG64)Pte;
 123     Temp <<= 25;
 124     Temp >>= 16;
 125     return (PVOID)Temp;
 126 }
 127
 128 BOOLEAN
 129 FORCEINLINE
 130 MiIsPdeForAddressValid(PVOID Address)
 131 {
 132     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
 133             (MiAddressToPpe(Address)->u.Hard.Valid) &&
 134             (MiAddressToPde(Address)->u.Hard.Valid));
 135 }
 136
 137 #define ADDR_TO_PAGE_TABLE(v) (((ULONG_PTR)(v)) / (512 * PAGE_SIZE))
 138 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
 139 #define ADDR_TO_PTE_OFFSET(v)  ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE)
 140
 141 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
 142
 143 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
 144 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
 145 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 146 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 147
 148 /* We don't use these hacks */
 149 VOID
 150 FORCEINLINE
 151 MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
 152 {
 153     /* Nothing to do */
 154 }
 155
 156 VOID
 157 FORCEINLINE
 158 MmInitGlobalKernelPageDirectory(VOID)
 159 {
 160     /* Nothing to do */
 161 }
 162
 163 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
 164 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
 165
 166 /* Easy accessing PFN in PTE */
 167 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 168
 169 // FIXME, only copied from x86
 170 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 171 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 172 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 173 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 174 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 175 #if !defined(CONFIG_SMP)
 176 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 177 #else
 178 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
 179 #endif
 180 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 181 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 182 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 183 #if !defined(CONFIG_SMP)
 184 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 185 #else
 186 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
 187 #endif
 188
 189 // FIXME!!!
 190 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 191     ((x) / (4*1024*1024))
 192
 193 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 194     ((((x)) % (4*1024*1024)) / (4*1024))
 195
 196 #define NR_SECTION_PAGE_TABLES              1024
 197 #define NR_SECTION_PAGE_ENTRIES             1024
 198
 199 //#define TEB_BASE                            0x7FFDE000
 200
 201 #define MI_HYPERSPACE_PTES                  (256 - 1)
 202 #define MI_ZERO_PTES                        (32)
 203 #define MI_MAPPING_RANGE_START              (ULONG)HYPER_SPACE
 204 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
 205                                              MI_HYPERSPACE_PTES * PAGE_SIZE)
 206 #define MI_ZERO_PTE                         (PMMPTE)(MI_MAPPING_RANGE_END + \
 207                                              PAGE_SIZE)
 208
 209 /* On x86, these two are the same */
 210 #define MMPDE MMPTE
 211 #define PMMPDE PMMPTE
 212
 213 /*
 214 * FIXME - different architectures have different cache line sizes...
 215 */
 216 #define MM_CACHE_LINE_SIZE                  32
 217