+#include <ntddk.h>
+#include <ata.h>
+#include <storport.h>
+
+#define DEBUG 1
+#pragma warning(disable:4214) // bit field types other than int
+#pragma warning(disable:4201) // nameless struct/union
+
+#define MAXIMUM_AHCI_PORT_COUNT 32
+#define MAXIMUM_AHCI_PRDT_ENTRIES 32
+#define MAXIMUM_AHCI_PORT_NCS 30
+#define MAXIMUM_QUEUE_BUFFER_SIZE 255
+#define MAXIMUM_TRANSFER_LENGTH (128*1024) // 128 KB
+
+// device type (DeviceParams)
+#define AHCI_DEVICE_TYPE_ATA 1
+#define AHCI_DEVICE_TYPE_ATAPI 2
+#define AHCI_DEVICE_TYPE_NODEVICE 3
+
+// section 3.1.2
+#define AHCI_Global_HBA_CAP_S64A (1 << 31)
+
+// FIS Types : http://wiki.osdev.org/AHCI
+#define FIS_TYPE_REG_H2D 0x27 // Register FIS - host to device
+#define FIS_TYPE_REG_D2H 0x34 // Register FIS - device to host
+#define FIS_TYPE_DMA_ACT 0x39 // DMA activate FIS - device to host
+#define FIS_TYPE_DMA_SETUP 0x41 // DMA setup FIS - bidirectional
+#define FIS_TYPE_BIST 0x58 // BIST activate FIS - bidirectional
+#define FIS_TYPE_PIO_SETUP 0x5F // PIO setup FIS - device to host
+#define FIS_TYPE_DEV_BITS 0xA1 // Set device bits FIS - device to host
+
+#define AHCI_ATA_CFIS_FisType 0
+#define AHCI_ATA_CFIS_PMPort_C 1
+#define AHCI_ATA_CFIS_CommandReg 2
+#define AHCI_ATA_CFIS_FeaturesLow 3
+#define AHCI_ATA_CFIS_LBA0 4
+#define AHCI_ATA_CFIS_LBA1 5
+#define AHCI_ATA_CFIS_LBA2 6
+#define AHCI_ATA_CFIS_Device 7
+#define AHCI_ATA_CFIS_LBA3 8
+#define AHCI_ATA_CFIS_LBA4 9
+#define AHCI_ATA_CFIS_LBA5 10
+#define AHCI_ATA_CFIS_FeaturesHigh 11
+#define AHCI_ATA_CFIS_SectorCountLow 12
+#define AHCI_ATA_CFIS_SectorCountHigh 13
+
+// ATA Functions
+#define ATA_FUNCTION_ATA_COMMAND 0x100
+#define ATA_FUNCTION_ATA_IDENTIFY 0x101
+
+// ATAPI Functions
+#define ATA_FUNCTION_ATAPI_COMMAND 0x200
+
+// ATA Flags
+#define ATA_FLAGS_DATA_IN (1 << 1)
+#define ATA_FLAGS_DATA_OUT (1 << 2)
+
+#define IsAtaCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATA_COMMAND)
+#define IsAtapiCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATAPI_COMMAND)
+#define IsDataTransferNeeded(SrbExtension) (SrbExtension->Flags & (ATA_FLAGS_DATA_IN | ATA_FLAGS_DATA_OUT))
+#define IsAdapterCAPS64(CAP) (CAP & AHCI_Global_HBA_CAP_S64A)
+
+// 3.1.1 NCS = CAP[12:08] -> Align
+#define AHCI_Global_Port_CAP_NCS(x) (((x) & 0xF00) >> 8)
+
+#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
+#ifdef DBG
+ #define DebugPrint(format, ...) StorPortDebugPrint(0, format, __VA_ARGS__)
+#endif
+
+typedef
+VOID
+(*PAHCI_COMPLETION_ROUTINE) (
+ __in PVOID PortExtension,
+ __in PVOID Srb
+ );
+
+//////////////////////////////////////////////////////////////
+// ---- Support Structures --- //
+//////////////////////////////////////////////////////////////
+
+// section 3.3.5
+typedef union _AHCI_INTERRUPT_STATUS
+{
+ struct
+ {
+ ULONG DHRS:1; //Device to Host Register FIS Interrupt
+ ULONG PSS :1; //PIO Setup FIS Interrupt
+ ULONG DSS :1; //DMA Setup FIS Interrupt
+ ULONG SDBS :1; //Set Device Bits Interrupt
+ ULONG UFS :1; //Unknown FIS Interrupt
+ ULONG DPS :1; //Descriptor Processed
+ ULONG PCS :1; //Port Connect Change Status
+ ULONG DMPS :1; //Device Mechanical Presence Status (DMPS)
+ ULONG Reserved :14;
+ ULONG PRCS :1; //PhyRdy Change Status
+ ULONG IPMS :1; //Incorrect Port Multiplier Status
+ ULONG OFS :1; //Overflow Status
+ ULONG Reserved2 :1;
+ ULONG INFS :1; //Interface Non-fatal Error Status
+ ULONG IFS :1; //Interface Fatal Error Status
+ ULONG HBDS :1; //Host Bus Data Error Status
+ ULONG HBFS :1; //Host Bus Fatal Error Status
+ ULONG TFES :1; //Task File Error Status
+ ULONG CPDS :1; //Cold Port Detect Status
+ };
+
+ ULONG Status;
+} AHCI_INTERRUPT_STATUS;
+
+typedef struct _AHCI_FIS_DMA_SETUP
+{
+ ULONG ULONG0_1; // FIS_TYPE_DMA_SETUP
+ // Port multiplier
+ // Reserved
+ // Data transfer direction, 1 - device to host
+ // Interrupt bit
+ // Auto-activate. Specifies if DMA Activate FIS is needed
+ UCHAR Reserved[2]; // Reserved
+ ULONG DmaBufferLow; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
+ ULONG DmaBufferHigh;
+ ULONG Reserved2; // More reserved
+ ULONG DmaBufferOffset; // Byte offset into buffer. First 2 bits must be 0
+ ULONG TranferCount; // Number of bytes to transfer. Bit 0 must be 0
+ ULONG Reserved3; // Reserved
+} AHCI_FIS_DMA_SETUP;
+
+typedef struct _AHCI_PIO_SETUP_FIS
+{
+ UCHAR FisType;
+ UCHAR Reserved1 :5;
+ UCHAR D :1;
+ UCHAR I :1;
+ UCHAR Reserved2 :1;
+ UCHAR Status;
+ UCHAR Error;
+
+ UCHAR SectorNumber;
+ UCHAR CylLow;
+ UCHAR CylHigh;
+ UCHAR Dev_Head;
+
+ UCHAR SectorNumb_Exp;
+ UCHAR CylLow_Exp;
+ UCHAR CylHigh_Exp;
+ UCHAR Reserved3;
+
+ UCHAR SectorCount;
+ UCHAR SectorCount_Exp;
+ UCHAR Reserved4;
+ UCHAR E_Status;
+
+ USHORT TransferCount;
+ UCHAR Reserved5[2];
+} AHCI_PIO_SETUP_FIS;
+
+typedef struct _AHCI_D2H_REGISTER_FIS
+{
+ UCHAR FisType;
+ UCHAR Reserved1 :6;
+ UCHAR I:1;
+ UCHAR Reserved2 :1;
+ UCHAR Status;
+ UCHAR Error;
+
+ UCHAR SectorNumber;
+ UCHAR CylLow;
+ UCHAR CylHigh;
+ UCHAR Dev_Head;
+
+ UCHAR SectorNum_Exp;
+ UCHAR CylLow_Exp;
+ UCHAR CylHigh_Exp;
+ UCHAR Reserved;
+
+ UCHAR SectorCount;
+ UCHAR SectorCount_Exp;
+ UCHAR Reserved3[2];
+
+ UCHAR Reserved4[4];
+} AHCI_D2H_REGISTER_FIS;
+
+typedef struct _AHCI_SET_DEVICE_BITS_FIS
+{
+ UCHAR FisType;
+
+ UCHAR PMPort: 4;
+ UCHAR Reserved1 :2;
+ UCHAR I :1;
+ UCHAR N :1;
+
+ UCHAR Status_Lo :3;
+ UCHAR Reserved2 :1;
+ UCHAR Status_Hi :3;
+ UCHAR Reserved3 :1;
+
+ UCHAR Error;
+
+ UCHAR Reserved5[4];
+} AHCI_SET_DEVICE_BITS_FIS;
+
+typedef struct _AHCI_QUEUE
+{
+ PVOID Buffer[MAXIMUM_QUEUE_BUFFER_SIZE]; // because Storahci hold Srb queue of 255 size
+ ULONG Head;
+ ULONG Tail;
+} AHCI_QUEUE, *PAHCI_QUEUE;
+
+//////////////////////////////////////////////////////////////
+// --------------------------- //
+//////////////////////////////////////////////////////////////
+
+typedef union _AHCI_COMMAND_HEADER_DESCRIPTION
+{
+ struct
+ {
+ ULONG CFL : 5; // Command FIS Length
+ ULONG A : 1; // IsATAPI
+ ULONG W : 1; // Write
+ ULONG P : 1; // Prefetchable
+
+ ULONG R : 1; // Reset
+ ULONG B : 1; // BIST
+ ULONG C : 1; //Clear Busy upon R_OK
+ ULONG RSV : 1;
+ ULONG PMP : 4; //Port Multiplier Port
+
+ ULONG PRDTL : 16; //Physical Region Descriptor Table Length
+ };
+
+ ULONG Status;
+} AHCI_COMMAND_HEADER_DESCRIPTION;
+
+typedef union _AHCI_GHC
+{
+ struct
+ {
+ ULONG HR : 1;
+ ULONG IE : 1;
+ ULONG MRSM : 1;
+ ULONG RSV0 : 28;
+ ULONG AE : 1;
+ };
+
+ ULONG Status;
+} AHCI_GHC;
+
+// section 3.3.7
+typedef union _AHCI_PORT_CMD
+{
+ struct
+ {
+ ULONG ST : 1;
+ ULONG SUD : 1;
+ ULONG POD : 1;
+ ULONG CLO : 1;
+ ULONG FRE : 1;
+ ULONG RSV0 : 3;
+ ULONG CCS : 5;
+ ULONG MPSS : 1;
+ ULONG FR : 1;
+ ULONG CR : 1;
+ ULONG CPS : 1;
+ ULONG PMA : 1;
+ ULONG HPCP : 1;
+ ULONG MPSP : 1;
+ ULONG CPD : 1;
+ ULONG ESP : 1;
+ ULONG FBSCP : 1;
+ ULONG APSTE : 1;
+ ULONG ATAPI : 1;
+ ULONG DLAE : 1;
+ ULONG ALPE : 1;
+ ULONG ASP : 1;
+ ULONG ICC : 4;
+ };
+
+ ULONG Status;
+} AHCI_PORT_CMD;
+
+typedef union _AHCI_SERIAL_ATA_CONTROL
+{
+ struct
+ {
+ ULONG DET :4;
+ ULONG SPD :4;
+ ULONG IPM :4;
+ ULONG SPM :4;
+ ULONG PMP :4;
+ ULONG DW11_Reserved :12;
+ };
+
+ ULONG Status;
+} AHCI_SERIAL_ATA_CONTROL;
+
+typedef union _AHCI_SERIAL_ATA_STATUS
+{
+ struct
+ {
+ ULONG DET :4;
+ ULONG SPD :4;
+ ULONG IPM :4;
+ ULONG RSV0 :20;
+ };
+
+ ULONG Status;
+} AHCI_SERIAL_ATA_STATUS;
+
+typedef union _AHCI_TASK_FILE_DATA
+{
+ struct
+ {
+ struct _STS
+ {
+ UCHAR ERR : 1;
+ UCHAR CS1 : 2;
+ UCHAR DRQ : 1;
+ UCHAR CS2 : 3;
+ UCHAR BSY : 1;
+ } STS;
+ UCHAR ERR;
+ USHORT RSV;
+ };
+
+ ULONG Status;
+} AHCI_TASK_FILE_DATA;
+
+typedef struct _AHCI_PRDT
+{
+ ULONG DBA;
+ ULONG DBAU;
+ ULONG RSV0;
+
+ ULONG DBC : 22;
+ ULONG RSV1 : 9;
+ ULONG I : 1;
+} AHCI_PRDT, *PAHCI_PRDT;
+
+// 4.2.3 Command Table
+typedef struct _AHCI_COMMAND_TABLE
+{
+ // (16 * 32) + 64 + 16 + 48 = 648
+ // 128 byte aligned :D
+ UCHAR CFIS[64];
+ UCHAR ACMD[16];
+ UCHAR RSV0[48];
+ AHCI_PRDT PRDT[MAXIMUM_AHCI_PRDT_ENTRIES];
+} AHCI_COMMAND_TABLE, *PAHCI_COMMAND_TABLE;
+
+// 4.2.2 Command Header
+typedef struct _AHCI_COMMAND_HEADER
+{
+ AHCI_COMMAND_HEADER_DESCRIPTION DI; // DW 0
+ ULONG PRDBC; // DW 1
+ ULONG CTBA; // DW 2
+ ULONG CTBA_U; // DW 3
+ ULONG Reserved[4]; // DW 4-7
+} AHCI_COMMAND_HEADER, *PAHCI_COMMAND_HEADER;
+
+// Received FIS
+typedef struct _AHCI_RECEIVED_FIS
+{
+ struct _AHCI_FIS_DMA_SETUP DmaSetupFIS; // 0x00 -- DMA Setup FIS
+ ULONG pad0; // 4 BYTE padding
+ struct _AHCI_PIO_SETUP_FIS PioSetupFIS; // 0x20 -- PIO Setup FIS
+ ULONG pad1[3]; // 12 BYTE padding
+ struct _AHCI_D2H_REGISTER_FIS RegisterFIS; // 0x40 -- Register – Device to Host FIS
+ ULONG pad2; // 4 BYTE padding
+ struct _AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS; // 0x58 -- Set Device Bit FIS
+ ULONG UnknowFIS[16]; // 0x60 -- Unknown FIS
+ ULONG Reserved[24]; // 0xA0 -- Reserved
+} AHCI_RECEIVED_FIS, *PAHCI_RECEIVED_FIS;
+
+// Holds Port Information