#define PROCESSOR_ARCHITECTURE_ARM 5
#define PROCESSOR_ARCHITECTURE_IA64 6
#define PROCESSOR_ARCHITECTURE_ALPHA64 7
-#define PROCESSOR_ARCHITECTURE_MSIL8
+#define PROCESSOR_ARCHITECTURE_MSIL 8
+#define PROCESSOR_ARCHITECTURE_AMD64 9
#define PROCESSOR_ARCHITECTURE_UNKNOWN 0xFFFF
#define PF_FLOATING_POINT_PRECISION_ERRATA 0
#define PF_FLOATING_POINT_EMULATED 1
return *((PVOID *)GetCurrentFiber());
}
+#if defined(__GNUC__)
+
+static __inline__ BOOLEAN
+InterlockedBitTestAndSet(IN LONG *Base,
+ IN LONG Bit)
+{
+ LONG OldBit;
+
+ __asm__ __volatile__("lock "
+ "btsl %2,%1\n\t"
+ "sbbl %0,%0\n\t"
+ :"=r" (OldBit),"=m" (*Base)
+ :"Ir" (Bit)
+ : "memory");
+ return OldBit;
+}
+
+static __inline__ BOOLEAN
+InterlockedBitTestAndReset(IN LONG *Base,
+ IN LONG Bit)
+{
+ LONG OldBit;
+
+ __asm__ __volatile__("lock "
+ "btrl %2,%1\n\t"
+ "sbbl %0,%0\n\t"
+ :"=r" (OldBit),"=m" (*Base)
+ :"Ir" (Bit)
+ : "memory");
+ return OldBit;
+}
+
+#endif
+
+#define YieldProcessor() __asm__ __volatile__("pause");
+
+#if defined(_AMD64_)
+#if defined(_M_AMD64)
+
+#define InterlockedExchangeAddSizeT(a, b) InterlockedExchangeAdd64((LONG64 *)a, b)
+
+#endif
+
+#else
+
+#define InterlockedExchangeAddSizeT(a, b) InterlockedExchangeAdd((LONG *)a, b)
+
+#endif
+
#endif /* RC_INVOKED */
#ifdef __cplusplus