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e836d0b)
[ROSLOAD]: The IA32_MISC_ENABLE MSR bit actually _disables_ NX, so
diabling the bit _enables_ NX.
[ROSLOAD]: The MSR_XD_ENABLE_MASK is for the _high_ DWORD of the MSR
(bit 34), not the low.
[ROSLOAD]: Fix printf.
[ENVIRON/ROSLOAD]: Switch to CPU_INFO structure instead of blindly using
INT[4]. Revealed a bug in the PAE detection which was reading out of
bounds.
_Out_ PULONG ReturnFlags
)
{
_Out_ PULONG ReturnFlags
)
{
- INT CpuInfo[4];
- BOOLEAN NxDisabled;
+ CPU_INFO CpuInfo;
+ BOOLEAN NxEnabled;
NTSTATUS Status;
BOOLEAN ExecuteJump;
NTSTATUS Status;
BOOLEAN ExecuteJump;
/* Check if the CPU supports NX */
/* Check if the CPU supports NX */
- BlArchCpuId(0x80000001, 0, CpuInfo);
- if (!(CpuInfo[3] & 0x10000))
+ BlArchCpuId(0x80000001, 0, &CpuInfo);
+ if (!(CpuInfo.Edx & 0x10000))
{
/* It doesn't, check if this is Intel */
{
/* It doesn't, check if this is Intel */
- EfiPrintf(L"NX disabled: %d\r\n");
+ EfiPrintf(L"NX disabled: %lx\r\n", CpuInfo.Edx);
if (BlArchGetCpuVendor() == CPU_INTEL)
{
if (BlArchGetCpuVendor() == CPU_INTEL)
{
- /* Then turn off the MSR feature for it */
- EfiPrintf(L"NX being turned off\r\n");
- __writemsr(MSR_IA32_MISC_ENABLE,
- __readmsr(MSR_IA32_MISC_ENABLE) & MSR_XD_ENABLE_MASK);
- NxDisabled = TRUE;
+ /* Then turn off the MSR disable feature for it, enabling NX */
+ EfiPrintf(L"NX being turned on\r\n");
+ miscMsr.QuadPart = __readmsr(MSR_IA32_MISC_ENABLE);
+ miscMsr.HighPart &= MSR_XD_ENABLE_MASK;
+ __writemsr(MSR_IA32_MISC_ENABLE, miscMsr.QuadPart);
+ NxEnabled = TRUE;
/* Retore NX support */
__writemsr(MSR_EFER, __readmsr(MSR_EFER) ^ MSR_NXE);
/* Retore NX support */
__writemsr(MSR_EFER, __readmsr(MSR_EFER) ^ MSR_NXE);
- /* Did we disable NX? */
- if (NxDisabled)
+ /* Did we manually enable NX? */
+ if (NxEnabled)
- /* Turn it back on */
- __writemsr(MSR_IA32_MISC_ENABLE,
- __readmsr(MSR_IA32_MISC_ENABLE) | ~MSR_XD_ENABLE_MASK);
+ /* Turn it back off */
+ miscMsr.QuadPart = __readmsr(MSR_IA32_MISC_ENABLE);
+ miscMsr.HighPart |= ~MSR_XD_ENABLE_MASK;
+ __writemsr(MSR_IA32_MISC_ENABLE, miscMsr.QuadPart);
NTSTATUS Status;
PBL_RETURN_ARGUMENTS ReturnArguments;
PBL_APPLICATION_ENTRY AppEntry;
NTSTATUS Status;
PBL_RETURN_ARGUMENTS ReturnArguments;
PBL_APPLICATION_ENTRY AppEntry;
ULONG Flags;
#ifdef DRAW_LOGO
EFI_GRAPHICS_OUTPUT_BLT_PIXEL* gopBlt;
ULONG Flags;
#ifdef DRAW_LOGO
EFI_GRAPHICS_OUTPUT_BLT_PIXEL* gopBlt;
if (BlArchIsCpuIdFunctionSupported(1))
{
/* Query CPU features */
if (BlArchIsCpuIdFunctionSupported(1))
{
/* Query CPU features */
- BlArchCpuId(1, 0, CpuInfo);
+ BlArchCpuId(1, 0, &CpuInfo);
/* Check if PAE is supported */
/* Check if PAE is supported */
+ if (CpuInfo.Edx & 0x40)
{
EfiPrintf(L"PAE Supported, but won't be used\r\n");
}
{
EfiPrintf(L"PAE Supported, but won't be used\r\n");
}
BlArchCpuId (
_In_ ULONG Function,
_In_ ULONG SubFunction,
BlArchCpuId (
_In_ ULONG Function,
_In_ ULONG SubFunction,
)
{
#if defined(_M_IX86) || defined(_M_X64)
)
{
#if defined(_M_IX86) || defined(_M_X64)
/* Serialize with CPUID, if it exists */
if (Archx86IsCpuidSupported())
{
/* Serialize with CPUID, if it exists */
if (Archx86IsCpuidSupported())
{
- BlArchCpuId(0, 0, CpuInfo);
+ BlArchCpuId(0, 0, &CpuInfo);
BlArchCpuId (
_In_ ULONG Function,
_In_ ULONG SubFunction,
BlArchCpuId (
_In_ ULONG Function,
_In_ ULONG SubFunction,
)
{
#if defined(_M_IX86) || defined(_M_X64)
/* Use the intrinsic */
)
{
#if defined(_M_IX86) || defined(_M_X64)
/* Use the intrinsic */
- __cpuidex(Result, Function, SubFunction);
+ __cpuidex((INT*)Result->AsUINT32, Function, SubFunction);
INT Temp;
/* Get the CPU Vendor */
INT Temp;
/* Get the CPU Vendor */
- BlArchCpuId(0, 0, CpuInfo);
- Temp = CpuInfo[2];
- CpuInfo[2] = CpuInfo[3];
- CpuInfo[3] = Temp;
+ BlArchCpuId(0, 0, &CpuInfo);
+ Temp = CpuInfo.Ecx;
+ CpuInfo.Ecx = CpuInfo.Edx;
+ CpuInfo.Edx = Temp;
/* Check against supported values */
/* Check against supported values */
- if (!strncmp((PCHAR)&CpuInfo[1], "GenuineIntel", 12))
+ if (!strncmp((PCHAR)&CpuInfo.Ebx, "GenuineIntel", 12))
- if (!strncmp((PCHAR)&CpuInfo[1], "AuthenticAMD", 12))
+ if (!strncmp((PCHAR)&CpuInfo.Ebx, "AuthenticAMD", 12))
- if (!strncmp((PCHAR)&CpuInfo[1], "CentaurHauls", 12))
+ if (!strncmp((PCHAR)&CpuInfo.Ebx, "CentaurHauls", 12))
- if (!strncmp((PCHAR)&CpuInfo[1], "CyrixInstead", 12))
+ if (!strncmp((PCHAR)&CpuInfo.Ebx, "CyrixInstead", 12))
- if (!strncmp((PCHAR)&CpuInfo[1], "GenuineTMx86", 12))
+ if (!strncmp((PCHAR)&CpuInfo.Ebx, "GenuineTMx86", 12))
{
return CPU_TRANSMETA;
}
{
return CPU_TRANSMETA;
}
- if (!strncmp((PCHAR)&CpuInfo[1], "RiseRiseRise", 12))
+ if (!strncmp((PCHAR)&CpuInfo.Ebx, "RiseRiseRise", 12))
{
NTSTATUS Status;
ULONGLONG IncreaseUserVa, PerfCounter, CpuRandom;
{
NTSTATUS Status;
ULONGLONG IncreaseUserVa, PerfCounter, CpuRandom;
/* For phase 2, just map deferred regions */
if (Phase != 1)
/* For phase 2, just map deferred regions */
if (Phase != 1)
if (BlArchIsCpuIdFunctionSupported(1))
{
/* Call it */
if (BlArchIsCpuIdFunctionSupported(1))
{
/* Call it */
- BlArchCpuId(1, 0, CpuInfo);
+ BlArchCpuId(1, 0, &CpuInfo);
/* Check if RDRAND is supported */
/* Check if RDRAND is supported */
- if (CpuInfo[2] & 0x40000000)
+ if (CpuInfo.Ecx & 0x40000000)
{
EfiPrintf(L"Your CPU can do RDRAND! Good for you!\r\n");
CpuRandom = 0;
{
EfiPrintf(L"Your CPU can do RDRAND! Good for you!\r\n");
CpuRandom = 0;