35905, 35906, 35942, 35947, 35948, 35949, 35953, 36013, 36388, 36389, 36570, 37873, 37991, 39151 from amd64 branch
svn path=/trunk/; revision=43173
<xi:include href="halx86/hal_generic_up.rbuild" />
<xi:include href="halx86/hal_generic_pc.rbuild" />
<xi:include href="halx86/halup.rbuild" />
---- <xi:include href="halx86/halmp.rbuild" />
++++ <if property="BUILD_MP" value="1">
++++ <xi:include href="halx86/halmp.rbuild" />
++++ </if>
<xi:include href="halx86/halxbox.rbuild" />
</directory>
</if>
<xi:include href="halarm/directory.rbuild" />
</directory>
</if>
- <xi:include href="halx86/hal_generic_pc.rbuild" />
+ <if property="ARCH" value="amd64">
+++ <directory name="halx86">
+++ <xi:include href="halx86/hal_generic_amd64.rbuild" />
- <xi:include href="halamd64/hal_generic.rbuild" />
+++ </directory>
+ <directory name="halamd64">
++ <xi:include href="halamd64/directory.rbuild" />
+ </directory>
+ </if>
</group>
/* DATA **********************************************************************/
----ULONG _KdComPortInUse = 0;
++++PUCHAR KdComPortInUse;
/* FUNCTIONS *****************************************************************/
NTAPI
HalStopProfileInterrupt(IN KPROFILE_SOURCE ProfileSource)
{
---- KEBUGCHECK(0);
++++ ASSERT(FALSE);
return;
}
NTAPI
HalStartProfileInterrupt(IN KPROFILE_SOURCE ProfileSource)
{
---- KEBUGCHECK(0);
++++ ASSERT(FALSE);
return;
}
NTAPI
HalSetProfileInterval(IN ULONG_PTR Interval)
{
---- KEBUGCHECK(0);
++++ ASSERT(FALSE);
return Interval;
}
- #if 0
+
+++ #ifndef _M_AMD64
VOID
FASTCALL
ExAcquireFastMutex(
return TRUE;
}
--
++ #endif
VOID
NTAPI
VOID
NTAPI
HalRequestIpi(
- ULONG Unknown)
+ KAFFINITY TargetSet)
{
UNIMPLEMENTED;
}
return TRUE;
}
----
++++#ifndef _M_ARM
VOID
NTAPI
HalpAssignDriveLetters(IN struct _LOADER_PARAMETER_BLOCK *LoaderBlock,
PartitionNumber,
PartitionType);
}
----
++++#endif
BOOLEAN
NTAPI
return 0;
}
-----
+++++#ifndef _M_AMD64
VOID
FASTCALL
KeAcquireInStackQueuedSpinLock(
{
UNIMPLEMENTED;
}
+++++#endif
VOID
NTAPI
UNIMPLEMENTED;
}
+++ #ifndef _M_AMD64
#undef KeGetCurrentIrql
KIRQL
NTAPI
{
UNIMPLEMENTED;
}
+++ #endif
LARGE_INTEGER
return Value;
}
--#if 0
+++++#ifndef _M_AMD64
#undef KeRaiseIrql
VOID
NTAPI
return (KIRQL)0;
}
+++ #endif
+++++#ifndef _M_AMD64
#undef KeReleaseSpinLock
VOID
NTAPI
{
UNIMPLEMENTED;
}
-----
+++++#endif
VOID
NTAPI
return FALSE;
}
---
+++ #if !defined(_M_AMD64)
KIRQL
FASTCALL
KfAcquireSpinLock(
{
UNIMPLEMENTED;
}
+++ #endif
-
+ #if !defined(_M_AMD64)
VOID
NTAPI
READ_PORT_BUFFER_UCHAR(
{
UNIMPLEMENTED;
}
+ #endif
KIRQL
FASTCALL
UNIMPLEMENTED;
}
++ VOID
++ HalSweepDcache(VOID)
++ {
++ UNIMPLEMENTED;
++ }
++
++ VOID
++ HalSweepIcache(VOID)
++ {
++ UNIMPLEMENTED;
++ }
++
++ ULONG
++ HalGetInterruptSource(VOID)
++ {
++ UNIMPLEMENTED;
++ return 0;
++ }
++
/* EOF */
<?xml version="1.0"?>
<!DOCTYPE group SYSTEM "../../tools/rbuild/project.dtd">
<group>
++ <if property="ARCH" value="arm">
<module name="hal" type="kernelmodedll">
-- <importlibrary definition="hal_$(ARCH).def" />
-- <importlibrary definition="hal_arm.def" />
++++ <importlibrary definition="hal.pspec" />
<include base="ntoskrnl">include</include>
<library>ntoskrnl</library>
<define name="_NTHAL_" />
-- <linkerflag>-enable-stdcall-fixup</linkerflag>
<file>hal.c</file>
<file>hal.rc</file>
-- <file>hal.spec</file>
</module>
- </if>
- <if property="ARCH" value="i386">
+++ </if>
+++ <if property="ARCH" value="i386">
++ <module name="hal" type="kernelmodedll">
-- <importlibrary definition="hal.spec.def" />
++++ <importlibrary definition="hal.pspec" />
++ <include base="ntoskrnl">include</include>
++ <library>ntoskrnl</library>
++ <define name="_NTHAL_" />
++ <file>hal.c</file>
++ <file>hal.rc</file>
-- <file>hal.spec</file>
++ </module>
- </if>
+++ </if>
<if property="ARCH" value="i386">
<module ifnot="false" name="halupalias" type="alias" installbase="system32" installname="hal.dll" aliasof="halup">
</module>
<if property="ARCH" value="powerpc">
<module name="halupalias" type="alias" installbase="system32" installname="hal.dll" aliasof="halppc_up"/>
</if>
+++ <if property="ARCH" value="amd64">
+++ <module name="hal" type="kernelmodedll">
+++ <importlibrary definition="hal_amd64.def" />
+++ <include base="ntoskrnl">include</include>
+++ <library>ntoskrnl</library>
+++ <define name="_NTHAL_" />
+++ <file>hal.c</file>
+++ <file>hal.rc</file>
+++ </module>
+++ </if>
</group>
--- /dev/null
--- /dev/null
--- /dev/null
-- .ascii "Sory, asm function "
+++ /*
+++ * FILE: hal/halx86/generic/irq.S
+++ * COPYRIGHT: See COPYING in the top level directory
+++ * PURPOSE: Software, System and Hardware IRQ Management
+++ * PROGRAMMER: Alex Ionescu (alex@relsoft.net)
+++ */
+++
+++ /* INCLUDES ******************************************************************/
+++
+++ #include <asm.h>
+++ #include <internal/i386/asmmacro.S>
+++ .intel_syntax noprefix
+++
+++ .macro UNIMPLEMENTED func
+++ jmp 2f
+++ 1:
- UNIMPLEMENTED "HalpInitPICs"
+++++ .ascii "Sorry, asm function "
+++ .ascii func
+++ .ascii " is unimplemented!\n\0"
+++ 2:
+++ movabs rcx, offset 1b
+++ call _DbgPrint
+++ ret
+++ .endm
+++
+++
+++
+++ /* GLOBALS *******************************************************************/
+++
+++
+++
+++ /* FUNCTIONS *****************************************************************/
+++
+++ .globl _HalpInitPICs
+++ .func _HalpInitPICs
+++ _HalpInitPICs:
- .globl _HalRequestSoftwareInterrupt
- .func _HalRequestSoftwareInterrupt
- _HalRequestSoftwareInterrupt:
- UNIMPLEMENTED "HalRequestSoftwareInterrupt"
- .endfunc
-
++++ UNIMPLEMENTED "HalpInitPICs"
++++ .endfunc
++++
++++ .global _HalEnableInterrupt
++++ .func _HalEnableInterrupt
++++ _HalEnableInterrupt:
++++ UNIMPLEMENTED "HalEnableInterrupt"
++++ .endfunc
+++
++++ .global _HalDisableInterrupt
++++ .func _HalDisableInterrupt
++++ _HalDisableInterrupt:
++++ UNIMPLEMENTED "HalDisableInterrupt"
++++ .endfunc
++++
++++ .global _HalRequestSoftwareInterrupt
++++ .func _HalRequestSoftwareInterrupt
++++ _HalRequestSoftwareInterrupt:
++++ UNIMPLEMENTED "HalRequestSoftwareInterrupt"
+++ .endfunc
+++
++++ .global _HalSendSoftwareInterrupt
++++ .func _HalSendSoftwareInterrupt
++++ _HalSendSoftwareInterrupt:
++++ UNIMPLEMENTED "HalSendSoftwareInterrupt"
++++ .endfunc
++++
++++ .global _HalEndSystemInterrupt
++++ .func _HalEndSystemInterrupt
++++ _HalEndSystemInterrupt:
++++ UNIMPLEMENTED "HalEndSystemInterrupt"
++++ .endfunc
++++
++++
+++ .globl _HalClearSoftwareInterrupt
+++ .func _HalClearSoftwareInterrupt
+++ _HalClearSoftwareInterrupt:
++++ UNIMPLEMENTED "HalClearSoftwareInterrupt"
+++
+++ /* Get IRR mask */
+++ mov eax, 1
+++ shl eax, cl
+++ not eax
+++
+++ /* Set IRR */
+++ // and gs:[KPCR_IRR], eax
+++ ret
+++ .endfunc
+++
- UNIMPLEMENTED "HalBeginSystemInterrupt"
- .endfunc
-
- .globl _HalpApcInterrupt
- .func _HalpApcInterrupt
- //TRAP_FIXUPS hapc_a, hapc_t, DoFixupV86, DoFixupAbios
- _HalpApcInterrupt:
- UNIMPLEMENTED "HalpApcInterrupt"
- .endfunc
-
- .globl _HalpApcInterrupt2ndEntry
- .func _HalpApcInterrupt2ndEntry
- _HalpApcInterrupt2ndEntry:
- UNIMPLEMENTED "HalpApcInterrupt2ndEntry"
- .endfunc
-
- .globl _HalpDispatchInterrupt
- .func _HalpDispatchInterrupt
- //TRAP_FIXUPS hdpc_a, hdpc_t, DoFixupV86, DoFixupAbios
- _HalpDispatchInterrupt:
- UNIMPLEMENTED "HalpDispatchInterrupt"
- .endfunc
-
-
- .globl _HalpDispatchInterrupt2ndEntry
- .func _HalpDispatchInterrupt2ndEntry
- _HalpDispatchInterrupt2ndEntry:
- UNIMPLEMENTED "HalpDispatchInterrupt2ndEntry"
+++ .globl _HalBeginSystemInterrupt
+++ .func _HalBeginSystemInterrupt
+++ _HalBeginSystemInterrupt:
++++ UNIMPLEMENTED "HalBeginSystemInterrupt"
+++ .endfunc
+++
--- /dev/null
--- /dev/null
--PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
+++ /*
+++ *
+++ */
+++
++ #ifndef __INTERNAL_HAL_HAL_H
++ #define __INTERNAL_HAL_HAL_H
++
+++ #define HAL_APC_REQUEST 0
+++ #define HAL_DPC_REQUEST 1
+++
+++ /* CMOS Registers and Ports */
+++ #define CMOS_CONTROL_PORT (PUCHAR)0x70
+++ #define CMOS_DATA_PORT (PUCHAR)0x71
+++ #define RTC_REGISTER_A 0x0A
+++ #define RTC_REGISTER_B 0x0B
+++ #define RTC_REG_A_UIP 0x80
+++ #define RTC_REGISTER_CENTURY 0x32
+++
+++ /* Timer Registers and Ports */
+++ #define TIMER_CONTROL_PORT 0x43
+++ #define TIMER_DATA_PORT0 0x40
+++ #define TIMER_SC0 0
+++ #define TIMER_BOTH 0x30
+++ #define TIMER_MD2 0x4
+++
+++ /* Conversion functions */
+++ #define BCD_INT(bcd) \
+++ (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
+++ #define INT_BCD(int) \
+++ (UCHAR)(((int / 10) << 4) + (int % 10))
+++
+++ /* adapter.c */
- // ARM Headers
+++++PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
+++
+++ /* bus.c */
+++ VOID NTAPI HalpInitNonBusHandler (VOID);
+++
+++ /* irql.c */
+++ VOID NTAPI HalpInitPICs(VOID);
+++
+++ /* udelay.c */
+++ VOID NTAPI HalpInitializeClock(VOID);
+++
+++ /* pci.c */
+++ VOID HalpInitPciBus (VOID);
+++
+++ /* dma.c */
+++ VOID HalpInitDma (VOID);
+++
+++ /* Non-generic initialization */
+++ VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
+++ VOID HalpInitPhase1(VOID);
+++ VOID NTAPI HalpClockInterrupt(VOID);
+++
++ //
- #include <internal/arm/ke.h>
- #include <internal/arm/intrin_i.h>
+++ // KD Support
++ //
- // Versatile Peripherals
+++ VOID
+++ NTAPI
+++ HalpCheckPowerButton(
+++ VOID
+++ );
+++
+++ VOID
+++ NTAPI
+++ HalpRegisterKdSupportFunctions(
+++ VOID
+++ );
+++
+++ NTSTATUS
+++ NTAPI
+++ HalpSetupPciDeviceForDebugging(
+++ IN PVOID LoaderBlock,
+++ IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
+++ );
+++
+++ NTSTATUS
+++ NTAPI
+++ HalpReleasePciDeviceForDebugging(
+++ IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
+++ );
++
++ //
- #include <peripherals/pl011.h>
- #include <peripherals/pl190.h>
- #include <peripherals/sp804.h>
+++ // Memory routines
++ //
- // WDK Hack
+++ PVOID
+++ NTAPI
+++ HalpMapPhysicalMemory64(
+++ IN PHYSICAL_ADDRESS PhysicalAddress,
+++ IN ULONG NumberPage
+++ );
+++
+++ VOID
+++ NTAPI
+++ HalpUnmapVirtualAddress(
+++ IN PVOID VirtualAddress,
+++ IN ULONG NumberPages
+++ );
+++
+++ /* sysinfo.c */
+++ NTSTATUS
+++ NTAPI
+++ HaliQuerySystemInformation(
+++ IN HAL_QUERY_INFORMATION_CLASS InformationClass,
+++ IN ULONG BufferSize,
+++ IN OUT PVOID Buffer,
+++ OUT PULONG ReturnedLength
+++ );
+++
+++ NTSTATUS
+++ NTAPI
+++ HaliSetSystemInformation(
+++ IN HAL_SET_INFORMATION_CLASS InformationClass,
+++ IN ULONG BufferSize,
+++ IN OUT PVOID Buffer
+++ );
++
++ //
- #define KdComPortInUse _KdComPortInUse
+++ // BIOS Routines
++ //
+++ BOOLEAN
+++ NTAPI
+++ HalpBiosDisplayReset(
+++ VOID
+++ );
+++
+++ ULONG
+++ NTAPI
+++ HalpBorrowTss(
+++ VOID
+++ );
+++
+++ ULONG
+++ NTAPI
+++ HalpReturnTss(
+++ ULONG SavedTss
+++ );
+++
+++ VOID
+++ NTAPI
+++ HalpBiosCall(
+++ VOID
+++ );
+++
+++ VOID
+++ NTAPI
+++ HalpTrap0D(
+++ VOID
+++ );
+++
+++ VOID
+++ NTAPI
+++ HalpTrap06(
+++ VOID
+++ );
+++
+++++PDMA_ADAPTER
+++++NTAPI
+++++HalpGetDmaAdapter(
+++++ IN PVOID Context,
+++++ IN PDEVICE_DESCRIPTION DeviceDescription,
+++++ OUT PULONG NumberOfMapRegisters);
+++++
+++++VOID HaliInitBSP(VOID);
+++++VOID HaliStartApplicationProcessor(ULONG Cpu, ULONG Stack);
+++++
+++ extern PVOID HalpRealModeStart;
+++ extern PVOID HalpRealModeEnd;
+++
+++ extern KSPIN_LOCK HalpSystemHardwareLock;
++
++ #endif /* __INTERNAL_HAL_HAL_H */
PKPRCB Prcb = KeGetCurrentPrcb();
ULONG Increment;
USHORT RollOver;
- ULONG Flags;
-- ULONG Flags = 0;
-- ULONG_PTR Flags = 0;
+++++ ULONG_PTR Flags;
/* Check the CPU Type */
if (Prcb->CpuType <= 4)
KeSetTimeIncrement(Increment, HalpRolloverTable[0].HighPart);
/* Disable interrupts */
---- Ke386SaveFlags(Flags);
++++ Flags = __readeflags();
_disable();
/* Set the rollover */
__outbyte(TIMER_DATA_PORT0, RollOver >> 8);
/* Restore interrupts if they were previously enabled */
---- Ke386RestoreFlags(Flags);
++++ __writeeflags(Flags);
/* Save rollover and return */
HalpCurrentRollOver = RollOver;
HalCalibratePerformanceCounter(IN volatile PLONG Count,
IN ULONGLONG NewCount)
{
- ULONG Flags;
-- ULONG Flags = 0;
-- ULONG_PTR Flags = 0;
+++++ ULONG_PTR Flags;
/* Disable interrupts */
---- Ke386SaveFlags(Flags);
++++ Flags = __readeflags();
_disable();
/* Do a decrement for this CPU */
while (*Count);
/* Restore interrupts if they were previously enabled */
---- Ke386RestoreFlags(Flags);
++++ __writeeflags(Flags);
}
/*
#ifndef __INTERNAL_HAL_APIC_H
#define __INTERNAL_HAL_APIC_H
+++++#ifdef _M_AMD64
+++++#define APIC_DEFAULT_BASE 0xfffffffffee00000ULL;
+++++#else
#define APIC_DEFAULT_BASE 0xFEE00000 /* Default Local APIC Base Register Address */
+++++#endif
/* APIC Register Address Map */
#define APIC_ID 0x0020 /* Local APIC ID Register (R/W) */
#define APIC_LVT_VECTOR (0xFF << 0) /* Vector */
#define APIC_LVT_DS (0x1 << 12) /* Delivery Status */
----#define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */
----#define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */
----#define APIC_LVT_MASKED (0x1 << 16) /* Mask */
----#define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */
----
----#define APIC_LVT3_DM (0x7 << 8)
----#define APIC_LVT3_IIPP (0x1 << 13)
----#define APIC_LVT3_TM (0x1 << 15)
----#define APIC_LVT3_MASKED (0x1 << 16)
----#define APIC_LVT3_OS (0x1 << 17)
----
----#define APIC_TDCR_TMBASE (0x1 << 2)
----#define APIC_TDCR_MASK 0x0F
----#define APIC_TDCR_2 0x00
----#define APIC_TDCR_4 0x01
----#define APIC_TDCR_8 0x02
----#define APIC_TDCR_16 0x03
----#define APIC_TDCR_32 0x08
----#define APIC_TDCR_64 0x09
----#define APIC_TDCR_128 0x0A
----#define APIC_TDCR_1 0x0B
----
----#define APIC_LVT_VECTOR (0xFF << 0) /* Vector */
----#define APIC_LVT_DS (0x1 << 12) /* Delivery Status */
----#define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */
----#define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */
----#define APIC_LVT_MASKED (0x1 << 16) /* Mask */
----#define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */
++++#define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */
++++#define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */
++++#define APIC_LVT_MASKED (0x1 << 16) /* Mask */
++++#define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */
#define APIC_LVT3_DM (0x7 << 8)
#define APIC_LVT3_IIPP (0x1 << 13)
#define APIC_TDCR_128 0x0A
#define APIC_TDCR_1 0x0B
- #define APIC_LVT_VECTOR (0xFF << 0) /* Vector */
- #define APIC_LVT_DS (0x1 << 12) /* Delivery Status */
- #define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */
- #define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */
- #define APIC_LVT_MASKED (0x1 << 16) /* Mask */
- #define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */
-
- #define APIC_LVT3_DM (0x7 << 8)
- #define APIC_LVT3_IIPP (0x1 << 13)
- #define APIC_LVT3_TM (0x1 << 15)
- #define APIC_LVT3_MASKED (0x1 << 16)
- #define APIC_LVT3_OS (0x1 << 17)
-
- #define APIC_TDCR_TMBASE (0x1 << 2)
- #define APIC_TDCR_MASK 0x0F
- #define APIC_TDCR_2 0x00
- #define APIC_TDCR_4 0x01
- #define APIC_TDCR_8 0x02
- #define APIC_TDCR_16 0x03
- #define APIC_TDCR_32 0x08
- #define APIC_TDCR_64 0x09
- #define APIC_TDCR_128 0x0A
- #define APIC_TDCR_1 0x0B
-
#define APIC_TARGET_SELF 0x100
#define APIC_TARGET_ALL 0x200
#define APIC_TARGET_ALL_BUT_SELF 0x300
} CPU_INFO, *PCPU_INFO;
extern ULONG CPUCount; /* Total number of CPUs */
----extern ULONG BootCPU; /* Bootstrap processor */
++++extern ULONG BootCPU; /* Bootstrap processor */
extern ULONG OnlineCPUs; /* Bitmask of online CPUs */
extern CPU_INFO CPUMap[MAX_CPU]; /* Map of all CPUs in the system */
++++extern PULONG APICBase; /* Virtual address of local APIC */
++++extern ULONG lastregr[MAX_CPU]; /* For debugging */
++++extern ULONG lastvalr[MAX_CPU];
++++extern ULONG lastregw[MAX_CPU];
++++extern ULONG lastvalw[MAX_CPU];
/* Prototypes */
----
----__inline VOID APICWrite(ULONG Offset, ULONG Value);
----__inline ULONG APICRead(ULONG Offset);
VOID APICSendIPI(ULONG Target, ULONG Mode);
VOID APICSetup(VOID);
VOID HaliInitBSP(VOID);
VOID APICSyncArbIDs(VOID);
----__inline VOID APICSendEOI(VOID);
VOID APICCalibrateTimer(ULONG CPU);
VOID HaliStartApplicationProcessor(ULONG Cpu, ULONG Stack);
----static __inline ULONG ThisCPU(VOID)
++++static __inline ULONG _APICRead(ULONG Offset)
{
---- return (APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
++++ PULONG p;
++++
- p = (PULONG)((ULONG)APICBase + Offset);
+++++ p = (PULONG)((ULONG_PTR)APICBase + Offset);
++++ return *p;
}
- p = (PULONG)((ULONG)APICBase + Offset);
++++#if 0
++++static __inline VOID APICWrite(ULONG Offset,
++++ ULONG Value)
++++{
++++ PULONG p;
++++
+++++ p = (PULONG)((ULONG_PTR)APICBase + Offset);
- p = (PULONG)((ULONG)APICBase + Offset);
++++ *p = Value;
++++}
++++#else
++++static __inline VOID APICWrite(ULONG Offset,
++++ ULONG Value)
++++{
++++ PULONG p;
++++ ULONG CPU = (_APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
++++
++++ lastregw[CPU] = Offset;
++++ lastvalw[CPU] = Value;
++++
+++++ p = (PULONG)((ULONG_PTR)APICBase + Offset);
++++
++++ *p = Value;
++++}
#endif
++++#if 0
++++static __inline ULONG APICRead(ULONG Offset)
++++{
++++ PULONG p;
- p = (PULONG)((ULONG)APICBase + Offset);
----/* EOF */
+++++ p = (PULONG)((ULONG_PTR)APICBase + Offset);
++++ return *p;
++++}
++++#else
++++static __inline ULONG APICRead(ULONG Offset)
++++{
++++ PULONG p;
++++ ULONG CPU = (_APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
++++
++++ lastregr[CPU] = Offset;
++++ lastvalr[CPU] = 0;
++++
- p = (PULONG)((ULONG)APICBase + Offset);
+++++ p = (PULONG)((ULONG_PTR)APICBase + Offset);
++++ lastvalr[CPU] = *p;
++++ return lastvalr[CPU];
++++}
++++#endif
++++
++++static __inline ULONG ThisCPU(VOID)
++++{
++++ return (APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
++++}
++++
++++static __inline VOID APICSendEOI(VOID)
++++{
++++ // Send the EOI
++++ APICWrite(APIC_EOI, 0);
++++}
++++
++++#endif /* __INTERNAL_HAL_APIC_H */
++++
++++/* EOF */
#include <stdio.h>
/* WDK HAL Compilation hack */
----#ifdef _MSC_VER
#include <excpt.h>
#include <ntdef.h>
#undef _NTHAL_
#undef DECLSPEC_IMPORT
#define DECLSPEC_IMPORT
----#define __declspec(dllimport)
----#endif
++++#undef NTSYSAPI
++++#define NTSYSAPI __declspec(dllimport)
/* IFS/DDK/NDK Headers */
#include <ntifs.h>
/* Internal kernel headers */
#include "internal/pci.h"
+++ #ifdef _M_AMD64
+++ #include "internal/amd64/intrin_i.h"
+++ #else
#include "internal/i386/intrin_i.h"
+++ #endif
/* Internal HAL Headers */
#include "apic.h"
#include "mps.h"
#include "ioapic.h"
----/* Helper Header */
----#include <reactos/helper.h>
----
/* EOF */
(UCHAR)(((int / 10) << 4) + (int % 10))
/* adapter.c */
----PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
++++PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
/* bus.c */
VOID NTAPI HalpInitNonBusHandler (VOID);
VOID
);
+++ #ifdef _M_AMD64
+++ #define KfLowerIrql KeLowerIrql
+++ #ifndef CONFIG_SMP
+++ /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
+++ #define KiAcquireSpinLock(SpinLock)
+++ #define KiReleaseSpinLock(SpinLock)
+++ #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
+++ #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
+++ #endif // !CONFIG_SMP
+++ #endif // _M_AMD64
+++
extern PVOID HalpRealModeStart;
extern PVOID HalpRealModeEnd;
APICWrite(APIC_SIVR, tmp);
}
----
----__inline ULONG _APICRead(ULONG Offset)
----{
---- PULONG p;
----
--- p = (PULONG)((ULONG)APICBase + Offset);
- p = (PULONG)((ULONG_PTR)APICBase + Offset);
---- return *p;
----}
----
----#if 0
----__inline VOID APICWrite(ULONG Offset,
---- ULONG Value)
----{
---- PULONG p;
----
--- p = (PULONG)((ULONG)APICBase + Offset);
- p = (PULONG)((ULONG_PTR)APICBase + Offset);
----
---- *p = Value;
----}
----#else
----__inline VOID APICWrite(ULONG Offset,
---- ULONG Value)
----{
---- PULONG p;
---- ULONG CPU = (_APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
----
---- lastregw[CPU] = Offset;
---- lastvalw[CPU] = Value;
----
--- p = (PULONG)((ULONG)APICBase + Offset);
- p = (PULONG)((ULONG_PTR)APICBase + Offset);
----
---- *p = Value;
----}
----#endif
----
----
----#if 0
----__inline ULONG APICRead(ULONG Offset)
----{
---- PULONG p;
----
--- p = (PULONG)((ULONG)APICBase + Offset);
- p = (PULONG)((ULONG_PTR)APICBase + Offset);
---- return *p;
----}
----#else
----__inline ULONG APICRead(ULONG Offset)
----{
---- PULONG p;
---- ULONG CPU = (_APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
----
---- lastregr[CPU] = Offset;
---- lastvalr[CPU] = 0;
----
--- p = (PULONG)((ULONG)APICBase + Offset);
- p = (PULONG)((ULONG_PTR)APICBase + Offset);
----
---- lastvalr[CPU] = *p;
---- return lastvalr[CPU];
----}
----#endif
----
----__inline VOID APICSendEOI(VOID)
----{
---- // Send the EOI
---- APICWrite(APIC_EOI, 0);
----}
----
static VOID APICDumpBit(ULONG base)
{
ULONG v, i, j;
{
ULONG v, ver, maxlvt;
ULONG r1, r2, w1, w2;
---- ULONG CPU = ThisCPU();;
----
++++ ULONG CPU = ThisCPU();
r1 = lastregr[CPU];
BOOLEAN VerifyLocalAPIC(VOID)
{
SIZE_T reg0, reg1;
---- ULONG l, h;
++++ LARGE_INTEGER MsrValue;
++++
/* The version register is read-only in a real APIC */
reg0 = APICRead(APIC_VER);
DPRINT1("Getting VERSION: %x\n", reg0);
return FALSE;
}
---- Ke386Rdmsr(0x1b /*MSR_IA32_APICBASE*/, l, h);
++++ MsrValue.QuadPart = __readmsr(0x1B /*MSR_IA32_APICBASE*/);
---- if (!(l & /*MSR_IA32_APICBASE_ENABLE*/(1<<11)))
++++ if (!(MsrValue.LowPart & /*MSR_IA32_APICBASE_ENABLE*/(1<<11)))
{
DPRINT1("Local APIC disabled by BIOS -- reenabling.\n");
---- l &= ~/*MSR_IA32_APICBASE_BASE*/(1<<11);
---- l |= /*MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE*/(1<<11)|0xfee00000;
---- Ke386Wrmsr(0x1b/*MSR_IA32_APICBASE*/, l, h);
++++ MsrValue.LowPart &= ~/*MSR_IA32_APICBASE_BASE*/(1<<11);
++++ MsrValue.LowPart |= /*MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE*/(1<<11)|0xfee00000;
++++ __writemsr(0x1B /*MSR_IA32_APICBASE*/, MsrValue.HighPart);
}
ULONG tmp, i, flags;
/* save flags and disable interrupts */
---- Ke386SaveFlags(flags);
++++ flags = __readeflags();
_disable();
/* Wait up to 100ms for the APIC to become ready */
{
DPRINT1("CPU(%d) Current IPI was not delivered after 100ms.\n", ThisCPU());
}
---- Ke386RestoreFlags(flags);
++++ __writeeflags(flags);
}
#endif
MpsIRQTrapFrameToTrapFrame(PKIRQ_TRAPFRAME IrqTrapFrame,
PKTRAP_FRAME TrapFrame)
{
++++ #ifdef _M_AMD64
++++ UNIMPLEMENTED;
++++ #else
TrapFrame->SegGs = (USHORT)IrqTrapFrame->Gs;
TrapFrame->SegFs = (USHORT)IrqTrapFrame->Fs;
TrapFrame->SegEs = (USHORT)IrqTrapFrame->Es;
TrapFrame->Eip = IrqTrapFrame->Eip;
TrapFrame->SegCs = IrqTrapFrame->Cs;
TrapFrame->EFlags = IrqTrapFrame->Eflags;
++++ #endif
}
VOID
tmp = GET_APIC_VERSION(APICRead(APIC_VER));
if (!APIC_INTEGRATED(tmp))
{
---- tmp = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) | APIC_LVT_PERIODIC | LOCAL_TIMER_VECTOR;;
++++ tmp = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) | APIC_LVT_PERIODIC | LOCAL_TIMER_VECTOR;
}
else
{
/* Periodic timer */
---- tmp = APIC_LVT_PERIODIC | LOCAL_TIMER_VECTOR;;
++++ tmp = APIC_LVT_PERIODIC | LOCAL_TIMER_VECTOR;
}
APICWrite(APIC_LVTT, tmp);
APICSetupLVTT(1000000000);
---- TSCPresent = ((PKIPCR)KeGetPcr())->PrcbData.FeatureBits & KF_RDTSC ? TRUE : FALSE;
++++ TSCPresent = KeGetCurrentPrcb()->FeatureBits & KF_RDTSC ? TRUE : FALSE;
/*
* The timer chip counts down to zero. Let's wait
if (TSCPresent)
{
t2.QuadPart = (LONGLONG)__rdtsc();
---- CPUMap[CPU].CoreSpeed = (HZ * (t2.QuadPart - t1.QuadPart));
++++ CPUMap[CPU].CoreSpeed = (HZ * (ULONG)(t2.QuadPart - t1.QuadPart));
DPRINT("CPU clock speed is %ld.%04ld MHz.\n",
CPUMap[CPU].CoreSpeed/1000000,
CPUMap[CPU].CoreSpeed%1000000);
---- ((PKIPCR)KeGetPcr())->PrcbData.MHz = CPUMap[CPU].CoreSpeed/1000000;
++++ KeGetCurrentPrcb()->MHz = CPUMap[CPU].CoreSpeed/1000000;
}
CPUMap[CPU].BusSpeed = (HZ * (long)(tt1 - tt2) * APIC_DIVISOR);
}
VOID
---- SetInterruptGate(ULONG index, ULONG address)
++++ SetInterruptGate(ULONG index, ULONG_PTR address)
{
-UNIMPLEMENTED;
++++ #ifdef _M_AMD64
+++++ KIDTENTRY64 *idt;
+++++
+++++ idt = &KeGetPcr()->IdtBase[index];
+++++
+++++ idt->OffsetLow = address & 0xffff;
+++++ idt->Selector = KGDT_64_R0_CODE;
+++++ idt->IstIndex = 0;
+++++ idt->Reserved0 = 0;
+++++ idt->Type = 0x0e;
+++++ idt->Dpl = 0;
+++++ idt->Present = 1;
+++++ idt->OffsetMiddle = (address >> 16) & 0xffff;
+++++ idt->OffsetHigh = address >> 32;
+++++ idt->Reserved1 = 0;
+++++ idt->Alignment = 0;
++++ #else
KIDTENTRY *idt;
KIDT_ACCESS Access;
Access.SegmentType = I386_INTERRUPT_GATE;
idt = (KIDTENTRY*)((ULONG)KeGetPcr()->IDT + index * sizeof(KIDTENTRY));
---- idt->Offset = address & 0xffff;
++++ idt->Offset = (USHORT)(address & 0xffff);
idt->Selector = KGDT_R0_CODE;
idt->Access = Access.Value;
---- idt->ExtendedOffset = address >> 16;
++++ idt->ExtendedOffset = (USHORT)(address >> 16);
++++ #endif
}
VOID HaliInitBSP(VOID)
/* Only initialize the BSP once */
if (BSPInitialized)
{
---- KEBUGCHECK(0);
++++ ASSERT(FALSE);
return;
}
BSPInitialized = TRUE;
/* Setup interrupt handlers */
---- SetInterruptGate(LOCAL_TIMER_VECTOR, (ULONG)MpsTimerInterrupt);
---- SetInterruptGate(ERROR_VECTOR, (ULONG)MpsErrorInterrupt);
---- SetInterruptGate(SPURIOUS_VECTOR, (ULONG)MpsSpuriousInterrupt);
++++ SetInterruptGate(LOCAL_TIMER_VECTOR, (ULONG_PTR)MpsTimerInterrupt);
++++ SetInterruptGate(ERROR_VECTOR, (ULONG_PTR)MpsErrorInterrupt);
++++ SetInterruptGate(SPURIOUS_VECTOR, (ULONG_PTR)MpsSpuriousInterrupt);
#ifdef CONFIG_SMP
---- SetInterruptGate(IPI_VECTOR, (ULONG)MpsIpiInterrupt);
++++ SetInterruptGate(IPI_VECTOR, (ULONG_PTR)MpsIpiInterrupt);
#endif
DPRINT("APIC is mapped at 0x%X\n", APICBase);
else
{
DPRINT("No APIC found\n");
---- KEBUGCHECK(0);
++++ ASSERT(FALSE);
}
if (APICMode == amPIC)
CommonBase = (PULONG)COMMON_AREA;
/* Copy bootstrap code to common area */
----- memcpy((PVOID)((ULONG)CommonBase + PAGE_SIZE),
+++++ memcpy((PVOID)((ULONG_PTR)CommonBase + PAGE_SIZE),
&APstart,
----- (ULONG)&APend - (ULONG)&APstart + 1);
+++++ (ULONG_PTR)&APend - (ULONG_PTR)&APstart + 1);
/* Set shutdown code */
CMOS_WRITE(0xF, 0xA);
/* Set warm reset vector */
----- ps = (PUSHORT)((ULONG)BIOSBase + 0x467);
+++++ ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x467);
*ps = (COMMON_AREA + PAGE_SIZE) & 0xF;
----- ps = (PUSHORT)((ULONG)BIOSBase + 0x469);
+++++ ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x469);
*ps = (COMMON_AREA + PAGE_SIZE) >> 4;
#endif
Cpu >= CPUCount ||
OnlineCPUs & (1 << Cpu))
{
---- KEBUGCHECK(0);
++++ ASSERT(FALSE);
}
DPRINT1("Attempting to boot CPU %d\n", Cpu);
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