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[reactos.git] / drivers / storage / ide / uniata / atapi.h
1 /*++
2
3 Copyright (c) 2002-2012 Alexandr A. Telyatnikov (Alter)
4
5 Module Name:
6 atapi.h
7
8 Abstract:
9 This file contains IDE, ATA, ATAPI and SCSI Miniport definitions
10 and function prototypes.
11
12 Author:
13 Alexander A. Telyatnikov (Alter)
14
15 Environment:
16 kernel mode only
17
18 Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31 Revision History:
32
33 Some definitions were taken from standard ATAPI.SYS sources from NT4 DDK by
34 Mike Glass (MGlass)
35
36 Some definitions were taken from FreeBSD 4.3-4.6 ATA driver by
37 Søren Schmidt, Copyright (c) 1998,1999,2000,2001
38
39 Code was changed/updated by
40 Alter, Copyright (c) 2002-2004
41
42
43 --*/
44 #ifndef __GLOBAL_H__
45 #define __GLOBAL_H__
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif //__cplusplus
50
51 #ifndef USER_MODE
52 #include "config.h"
53 #endif //USER_MODE
54
55 #include "scsi.h"
56 #include "stdio.h"
57 #include "string.h"
58
59 #ifdef _DEBUG
60
61
62 #ifndef _DBGNT_
63
64 #ifdef KdPrint
65 #undef KdPrint
66 #endif
67
68 #ifdef USE_DBGPRINT_LOGGER
69 #include "inc/PostDbgMesg.h"
70 #define DbgPrint DbgDump_Printf
71 #define Connect_DbgPrint() {DbgDump_SetAutoReconnect(TRUE); DbgDump_Reconnect();}
72 #else // USE_DBGPRINT_LOGGER
73 #define Connect_DbgPrint() {;}
74 #endif // USE_DBGPRINT_LOGGER
75
76 #ifdef SCSI_PORT_DBG_PRINT
77
78 SCSIPORT_API
79 VOID
80 __cdecl
81 ScsiDebugPrint(
82 ULONG DebugPrintLevel,
83 PCCHAR DebugMessage,
84 ...
85 );
86
87 #define PRINT_PREFIX 0,
88
89 #define KdPrint3(_x_) ScsiDebugPrint _x_ {;}
90 #define KdPrint2(_x_) {ScsiDebugPrint("%x: ", PsGetCurrentThread()) ; ScsiDebugPrint _x_ ; }
91 #define KdPrint(_x_) ScsiDebugPrint _x_ {;}
92
93 #else // SCSI_PORT_DBG_PRINT
94
95 #ifndef USE_DBGPRINT_LOGGER
96 /*
97 ULONG
98 _cdecl
99 DbgPrint(
100 PCH Format,
101 ...
102 );
103 */
104 #endif // USE_DBGPRINT_LOGGER
105
106 #define PRINT_PREFIX
107
108 // Note, that using DbgPrint on raised IRQL will crash w2k
109 // ttis will not happen immediately, so we shall see some logs
110 //#define LOG_ON_RAISED_IRQL_W2K TRUE
111 //#define LOG_ON_RAISED_IRQL_W2K FALSE
112
113 #define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
114 #define KdPrint2(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
115 #define KdPrint(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
116 /*
117 #define PRINT_PREFIX_PTR ((PCHAR)&__tmp__kdprint__buff__)
118 #define PRINT_UPREFIX_PTR ((PWCHAR)&__tmp__kdprint__ubuff__)
119 #define PRINT_PREFIX PRINT_PREFIX_PTR,
120 #define KdPrint2(_x_) \
121 { \
122 WCHAR __tmp__kdprint__ubuff__[256]; \
123 CHAR __tmp__kdprint__buff__[256]; \
124 UNICODE_STRING __tmp__usrt__buff__; \
125 sprintf _x_; \
126 swprintf (PRINT_UPREFIX_PTR, L"%hs", PRINT_PREFIX_PTR); \
127 __tmp__usrt__buff__.Buffer = PRINT_UPREFIX_PTR; \
128 __tmp__usrt__buff__.Length = \
129 __tmp__usrt__buff__.MaximumLength = strlen(PRINT_PREFIX_PTR); \
130 NtDisplayString(&__tmp__usrt__buff__); \
131 };
132 #define KdPrint(_x_) DbgPrint _x_
133 */
134 #endif // SCSI_PORT_DBG_PRINT
135
136 //#define AtapiStallExecution(dt) { KdPrint2((" AtapiStallExecution(%d)\n", dt)); ScsiPortStallExecution(dt); }
137 #define AtapiStallExecution(dt) { ScsiPortStallExecution(dt); }
138
139 #endif // _DBGNT_
140
141 #else // _DEBUG
142
143 #ifdef KdPrint
144 #undef KdPrint
145 #endif
146
147 #define PRINT_PREFIX "UniATA: "
148
149 //#define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
150 #define KdPrint3(_x_) {;}
151 #define KdPrint2(_x_) {;}
152 #define KdPrint(_x_) {;}
153 #define Connect_DbgPrint() {;}
154
155 #define AtapiStallExecution(dt) ScsiPortStallExecution(dt)
156
157 #endif // _DEBUG
158
159 // IDE register definition
160
161 #pragma pack(push, 1)
162
163 typedef union _IDE_REGISTERS_1 {
164 struct _o {
165 UCHAR Data;
166 UCHAR Feature;
167 UCHAR BlockCount;
168 UCHAR BlockNumber;
169 UCHAR CylinderLow;
170 UCHAR CylinderHigh;
171 UCHAR DriveSelect;
172 UCHAR Command;
173 } o;
174
175 struct _i {
176 UCHAR Data;
177 UCHAR Error;
178 UCHAR BlockCount;
179 UCHAR BlockNumber;
180 UCHAR CylinderLow;
181 UCHAR CylinderHigh;
182 UCHAR DriveSelect;
183 UCHAR Status;
184 } i;
185
186 } IDE_REGISTERS_1, *PIDE_REGISTERS_1;
187
188 #define IDX_IO1 0
189 #define IDX_IO1_SZ sizeof(IDE_REGISTERS_1)
190
191 #define IDX_IO1 0
192 #define IDX_IO1_SZ sizeof(IDE_REGISTERS_1)
193 #define IDX_IO1_i_Data (FIELD_OFFSET(IDE_REGISTERS_1, i.Data )+IDX_IO1)
194 #define IDX_IO1_i_Error (FIELD_OFFSET(IDE_REGISTERS_1, i.Error )+IDX_IO1)
195 #define IDX_IO1_i_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockCount )+IDX_IO1)
196 #define IDX_IO1_i_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockNumber )+IDX_IO1)
197 #define IDX_IO1_i_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderLow )+IDX_IO1)
198 #define IDX_IO1_i_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderHigh)+IDX_IO1)
199 #define IDX_IO1_i_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, i.DriveSelect )+IDX_IO1)
200 #define IDX_IO1_i_Status (FIELD_OFFSET(IDE_REGISTERS_1, i.Status )+IDX_IO1)
201
202 #define IDX_IO1_o IDX_IO1_SZ
203 #define IDX_IO1_o_SZ sizeof(IDE_REGISTERS_1)
204
205 #define IDX_IO1_o_Data (FIELD_OFFSET(IDE_REGISTERS_1, o.Data )+IDX_IO1_o)
206 #define IDX_IO1_o_Feature (FIELD_OFFSET(IDE_REGISTERS_1, o.Feature )+IDX_IO1_o)
207 #define IDX_IO1_o_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockCount )+IDX_IO1_o)
208 #define IDX_IO1_o_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockNumber )+IDX_IO1_o)
209 #define IDX_IO1_o_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderLow )+IDX_IO1_o)
210 #define IDX_IO1_o_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderHigh)+IDX_IO1_o)
211 #define IDX_IO1_o_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, o.DriveSelect )+IDX_IO1_o)
212 #define IDX_IO1_o_Command (FIELD_OFFSET(IDE_REGISTERS_1, o.Command )+IDX_IO1_o)
213
214 typedef struct _IDE_REGISTERS_2 {
215 UCHAR AltStatus;
216 UCHAR DriveAddress;
217 } IDE_REGISTERS_2, *PIDE_REGISTERS_2;
218
219 #define IDX_IO2 (IDX_IO1_o+IDX_IO1_o_SZ)
220 #define IDX_IO2_SZ sizeof(IDE_REGISTERS_2)
221
222 #define IDX_IO2_AltStatus (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2)
223 #define IDX_IO2_DriveAddress (FIELD_OFFSET(IDE_REGISTERS_2, DriveAddress)+IDX_IO2)
224
225 #define IDX_IO2_o (IDX_IO2+IDX_IO2_SZ)
226 #define IDX_IO2_o_SZ sizeof(IDE_REGISTERS_2)
227
228 #define IDX_IO2_o_Control (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2_o)
229 //
230 // Device Extension Device Flags
231 //
232
233 #define DFLAGS_DEVICE_PRESENT 0x0001 // Indicates that some device is present.
234 #define DFLAGS_ATAPI_DEVICE 0x0002 // Indicates whether ATAPI commands can be used.
235 #define DFLAGS_TAPE_DEVICE 0x0004 // Indicates whether this is a tape device.
236 #define DFLAGS_INT_DRQ 0x0008 // Indicates whether device interrupts as DRQ is set after
237 // receiving ATAPI Packet Command
238 #define DFLAGS_REMOVABLE_DRIVE 0x0010 // Indicates that the drive has the 'removable' bit set in
239 // identify data (offset 128)
240 #define DFLAGS_MEDIA_STATUS_ENABLED 0x0020 // Media status notification enabled
241 #define DFLAGS_ATAPI_CHANGER 0x0040 // Indicates atapi 2.5 changer present.
242 #define DFLAGS_SANYO_ATAPI_CHANGER 0x0080 // Indicates multi-platter device, not conforming to the 2.5 spec.
243 #define DFLAGS_CHANGER_INITED 0x0100 // Indicates that the init path for changers has already been done.
244 #define DFLAGS_LBA_ENABLED 0x0200 // Indicates that we should use LBA addressing rather than CHS
245 #define DFLAGS_DWORDIO_ENABLED 0x0400 // Indicates that we should use 32-bit IO
246 #define DFLAGS_WCACHE_ENABLED 0x0800 // Indicates that we use write cache
247 #define DFLAGS_RCACHE_ENABLED 0x1000 // Indicates that we use read cache
248 #define DFLAGS_ORIG_GEOMETRY 0x2000 //
249 #define DFLAGS_REINIT_DMA 0x4000 //
250 #define DFLAGS_HIDDEN 0x8000 // Hidden device, available only with special IOCTLs
251 // via communication virtual device
252 #define DFLAGS_MANUAL_CHS 0x10000 // For devices those have no IDENTIFY commands
253 //#define DFLAGS_ 0x10000 //
254 //
255 // Used to disable 'advanced' features.
256 //
257
258 #define MAX_ERRORS 4
259
260 //
261 // ATAPI command definitions
262 //
263
264 #define ATAPI_MODE_SENSE 0x5A
265 #define ATAPI_MODE_SELECT 0x55
266 #define ATAPI_FORMAT_UNIT 0x24
267
268 // ATAPI Command Descriptor Block
269
270 typedef struct _MODE_SENSE_10 {
271 UCHAR OperationCode;
272 UCHAR Reserved1;
273 UCHAR PageCode : 6;
274 UCHAR Pc : 2;
275 UCHAR Reserved2[4];
276 UCHAR ParameterListLengthMsb;
277 UCHAR ParameterListLengthLsb;
278 UCHAR Reserved3[3];
279 } MODE_SENSE_10, *PMODE_SENSE_10;
280
281 typedef struct _MODE_SELECT_10 {
282 UCHAR OperationCode;
283 UCHAR Reserved1 : 4;
284 UCHAR PFBit : 1;
285 UCHAR Reserved2 : 3;
286 UCHAR Reserved3[5];
287 UCHAR ParameterListLengthMsb;
288 UCHAR ParameterListLengthLsb;
289 UCHAR Reserved4[3];
290 } MODE_SELECT_10, *PMODE_SELECT_10;
291
292 typedef struct _MODE_PARAMETER_HEADER_10 {
293 UCHAR ModeDataLengthMsb;
294 UCHAR ModeDataLengthLsb;
295 UCHAR MediumType;
296 UCHAR Reserved[5];
297 }MODE_PARAMETER_HEADER_10, *PMODE_PARAMETER_HEADER_10;
298
299 //
300 // values for TransferMode
301 //
302 #define ATA_PIO 0x00
303 #define ATA_PIO_NRDY 0x01
304
305 #define ATA_PIO0 0x08
306 #define ATA_PIO1 0x09
307 #define ATA_PIO2 0x0a
308 #define ATA_PIO3 0x0b
309 #define ATA_PIO4 0x0c
310 #define ATA_PIO5 0x0d
311
312 #define ATA_DMA 0x10
313 #define ATA_SDMA 0x10
314 #define ATA_SDMA0 0x10
315 #define ATA_SDMA1 0x11
316 #define ATA_SDMA2 0x12
317
318 #define ATA_WDMA 0x20
319 #define ATA_WDMA0 0x20
320 #define ATA_WDMA1 0x21
321 #define ATA_WDMA2 0x22
322
323 #define ATA_UDMA 0x40
324 #define ATA_UDMA0 0x40 // ATA-16
325 #define ATA_UDMA1 0x41 // ATA-25
326 #define ATA_UDMA2 0x42 // ATA-33
327 #define ATA_UDMA3 0x43 // ATA-44
328 #define ATA_UDMA4 0x44 // ATA-66
329 #define ATA_UDMA5 0x45 // ATA-100
330 #define ATA_UDMA6 0x46 // ATA-133
331 //#define ATA_UDMA7 0x47 // ATA-166
332
333 #define ATA_SA150 0x47 /*0x80*/
334 #define ATA_SA300 0x48 /*0x81*/
335 #define ATA_SA600 0x49 /*0x82*/
336
337 #define ATA_MODE_NOT_SPEC ((ULONG)(-1)) /*0x82*/
338
339 //
340 // IDE command definitions
341 //
342
343 #define IDE_COMMAND_DATA_SET_MGMT 0x06 // TRIM
344 #define IDE_COMMAND_ATAPI_RESET 0x08
345 #define IDE_COMMAND_RECALIBRATE 0x10
346 #define IDE_COMMAND_READ 0x20
347 #define IDE_COMMAND_READ_NO_RETR 0x21
348 #define IDE_COMMAND_READ48 0x24
349 #define IDE_COMMAND_READ_DMA48 0x25
350 #define IDE_COMMAND_READ_DMA_Q48 0x26
351 #define IDE_COMMAND_READ_NATIVE_SIZE48 0x27
352 #define IDE_COMMAND_READ_MUL48 0x29
353 #define IDE_COMMAND_READ_STREAM_DMA48 0x2A
354 #define IDE_COMMAND_READ_STREAM48 0x2B
355 #define IDE_COMMAND_READ_LOG48 0x2f
356 #define IDE_COMMAND_WRITE 0x30
357 #define IDE_COMMAND_WRITE_NO_RETR 0x31
358 #define IDE_COMMAND_WRITE48 0x34
359 #define IDE_COMMAND_WRITE_DMA48 0x35
360 #define IDE_COMMAND_WRITE_DMA_Q48 0x36
361 #define IDE_COMMAND_SET_NATIVE_SIZE48 0x37
362 #define IDE_COMMAND_WRITE_MUL48 0x39
363 #define IDE_COMMAND_WRITE_STREAM_DMA48 0x3a
364 #define IDE_COMMAND_WRITE_STREAM48 0x3b
365 #define IDE_COMMAND_WRITE_FUA_DMA48 0x3d
366 #define IDE_COMMAND_WRITE_FUA_DMA_Q48 0x3e
367 #define IDE_COMMAND_WRITE_LOG48 0x3f
368 #define IDE_COMMAND_VERIFY 0x40
369 #define IDE_COMMAND_VERIFY48 0x42
370 #define IDE_COMMAND_READ_LOG_DMA48 0x47
371 #define IDE_COMMAND_WRITE_LOG_DMA48 0x57
372 #define IDE_COMMAND_TRUSTED_RCV 0x5c
373 #define IDE_COMMAND_TRUSTED_RCV_DMA 0x5d
374 #define IDE_COMMAND_TRUSTED_SEND 0x5e
375 #define IDE_COMMAND_TRUSTED_SEND_DMA 0x5f
376 #define IDE_COMMAND_SEEK 0x70
377 #define IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91
378 #define IDE_COMMAND_ATAPI_PACKET 0xA0
379 #define IDE_COMMAND_ATAPI_IDENTIFY 0xA1
380 #define IDE_COMMAND_READ_MULTIPLE 0xC4
381 #define IDE_COMMAND_WRITE_MULTIPLE 0xC5
382 #define IDE_COMMAND_SET_MULTIPLE 0xC6
383 #define IDE_COMMAND_READ_DMA_Q 0xC7
384 #define IDE_COMMAND_READ_DMA 0xC8
385 #define IDE_COMMAND_WRITE_DMA 0xCA
386 #define IDE_COMMAND_WRITE_DMA_Q 0xCC
387 #define IDE_COMMAND_WRITE_MUL_FUA48 0xCE
388 #define IDE_COMMAND_GET_MEDIA_STATUS 0xDA
389 #define IDE_COMMAND_DOOR_LOCK 0xDE
390 #define IDE_COMMAND_DOOR_UNLOCK 0xDF
391 #define IDE_COMMAND_STANDBY_IMMED 0xE0 // flush and spin down
392 #define IDE_COMMAND_IDLE_IMMED 0xE1
393 #define IDE_COMMAND_STANDBY 0xE2 // flush and spin down and enable autopowerdown timer
394 #define IDE_COMMAND_IDLE 0xE3
395 #define IDE_COMMAND_READ_PM 0xE4 // SATA PM
396 #define IDE_COMMAND_SLEEP 0xE6 // flush, spin down and deactivate interface
397 #define IDE_COMMAND_FLUSH_CACHE 0xE7
398 #define IDE_COMMAND_WRITE_PM 0xE8 // SATA PM
399 #define IDE_COMMAND_IDENTIFY 0xEC
400 #define IDE_COMMAND_MEDIA_EJECT 0xED
401 #define IDE_COMMAND_FLUSH_CACHE48 0xEA
402 #define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF
403 #define IDE_COMMAND_SET_FEATURES 0xEF /* features command,
404 IDE_COMMAND_ENABLE_MEDIA_STATUS */
405 #define IDE_COMMAND_READ_NATIVE_SIZE 0xF8
406 #define IDE_COMMAND_SET_NATIVE_SIZE 0xF9
407
408 #define SCSIOP_ATA_PASSTHROUGH 0xCC //
409
410 //
411 // IDE status definitions
412 //
413
414 #define IDE_STATUS_SUCCESS 0x00
415 #define IDE_STATUS_ERROR 0x01
416 #define IDE_STATUS_INDEX 0x02
417 #define IDE_STATUS_CORRECTED_ERROR 0x04
418 #define IDE_STATUS_DRQ 0x08
419 #define IDE_STATUS_DSC 0x10
420 //#define IDE_STATUS_DWF 0x10 /* drive write fault */
421 #define IDE_STATUS_DMA 0x20 /* DMA ready */
422 #define IDE_STATUS_DWF 0x20 /* drive write fault */
423 #define IDE_STATUS_DRDY 0x40
424 #define IDE_STATUS_IDLE 0x50
425 #define IDE_STATUS_BUSY 0x80
426
427 #define IDE_STATUS_WRONG 0xff
428 #define IDE_STATUS_MASK 0xff
429
430
431 //
432 // IDE drive select/head definitions
433 //
434
435 #define IDE_DRIVE_SELECT 0xA0
436 #define IDE_DRIVE_1 0x00
437 #define IDE_DRIVE_2 0x10
438 #define IDE_DRIVE_SELECT_1 (IDE_DRIVE_SELECT | IDE_DRIVE_1)
439 #define IDE_DRIVE_SELECT_2 (IDE_DRIVE_SELECT | IDE_DRIVE_2)
440
441 #define IDE_USE_LBA 0x40
442
443 //
444 // IDE drive control definitions
445 //
446
447 #define IDE_DC_DISABLE_INTERRUPTS 0x02
448 #define IDE_DC_RESET_CONTROLLER 0x04
449 #define IDE_DC_A_4BIT 0x80
450 #define IDE_DC_USE_HOB 0x80 // use high-order byte(s)
451 #define IDE_DC_REENABLE_CONTROLLER 0x00
452
453 // IDE error definitions
454 //
455
456 #define IDE_ERROR_ICRC 0x80
457 #define IDE_ERROR_BAD_BLOCK 0x80
458 #define IDE_ERROR_DATA_ERROR 0x40
459 #define IDE_ERROR_MEDIA_CHANGE 0x20
460 #define IDE_ERROR_ID_NOT_FOUND 0x10
461 #define IDE_ERROR_MEDIA_CHANGE_REQ 0x08
462 #define IDE_ERROR_COMMAND_ABORTED 0x04
463 #define IDE_ERROR_END_OF_MEDIA 0x02
464 #define IDE_ERROR_NO_MEDIA 0x02
465 #define IDE_ERROR_ILLEGAL_LENGTH 0x01
466
467 //
468 // ATAPI register definition
469 //
470
471 typedef union _ATAPI_REGISTERS_1 {
472 struct _o {
473 UCHAR Data;
474 UCHAR Feature;
475 UCHAR Unused0;
476 UCHAR Unused1;
477 UCHAR ByteCountLow;
478 UCHAR ByteCountHigh;
479 UCHAR DriveSelect;
480 UCHAR Command;
481 } o;
482
483 struct _i {
484 UCHAR Data;
485 UCHAR Error;
486 UCHAR InterruptReason;
487 UCHAR Unused1;
488 UCHAR ByteCountLow;
489 UCHAR ByteCountHigh;
490 UCHAR DriveSelect;
491 UCHAR Status;
492 } i;
493
494 //IDE_REGISTERS_1 ide;
495
496 } ATAPI_REGISTERS_1, *PATAPI_REGISTERS_1;
497
498 #define IDX_ATAPI_IO1 IDX_IO1
499 #define IDX_ATAPI_IO1_SZ sizeof(ATAPI_REGISTERS_1)
500
501 #define IDX_ATAPI_IO1_i_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Data )+IDX_ATAPI_IO1)
502 #define IDX_ATAPI_IO1_i_Error (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Error )+IDX_ATAPI_IO1)
503 #define IDX_ATAPI_IO1_i_InterruptReason (FIELD_OFFSET(ATAPI_REGISTERS_1, i.InterruptReason)+IDX_ATAPI_IO1)
504 #define IDX_ATAPI_IO1_i_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Unused1 )+IDX_ATAPI_IO1)
505 #define IDX_ATAPI_IO1_i_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountLow )+IDX_ATAPI_IO1)
506 #define IDX_ATAPI_IO1_i_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountHigh )+IDX_ATAPI_IO1)
507 #define IDX_ATAPI_IO1_i_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, i.DriveSelect )+IDX_ATAPI_IO1)
508 #define IDX_ATAPI_IO1_i_Status (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Status )+IDX_ATAPI_IO1)
509
510 #define IDX_ATAPI_IO1_o_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Data )+IDX_ATAPI_IO1)
511 #define IDX_ATAPI_IO1_o_Feature (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Feature )+IDX_ATAPI_IO1)
512 #define IDX_ATAPI_IO1_o_Unused0 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused0 )+IDX_ATAPI_IO1)
513 #define IDX_ATAPI_IO1_o_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused1 )+IDX_ATAPI_IO1)
514 #define IDX_ATAPI_IO1_o_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountLow )+IDX_ATAPI_IO1)
515 #define IDX_ATAPI_IO1_o_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountHigh)+IDX_ATAPI_IO1)
516 #define IDX_ATAPI_IO1_o_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, o.DriveSelect )+IDX_ATAPI_IO1)
517 #define IDX_ATAPI_IO1_o_Command (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Command )+IDX_ATAPI_IO1)
518
519 /*
520 typedef union _ATAPI_REGISTERS_2 {
521 struct {
522 UCHAR AltStatus;
523 UCHAR DriveAddress;
524 };
525
526 //IDE_REGISTERS_2 ide;
527
528 } ATAPI_REGISTERS_2, *PATAPI_REGISTERS_2;
529
530 #define IDX_ATAPI_IO2 IDX_ATAPI_IO2_SZ
531 #define IDX_ATAPI_IO2_SZ sizeof(ATAPI_REGISTERS_2)
532 */
533
534 //
535 // ATAPI interrupt reasons
536 //
537
538 // for IDX_ATAPI_IO1_i_InterruptReason
539 #define ATAPI_IR_COD 0x01
540 #define ATAPI_IR_COD_Data 0x0
541 #define ATAPI_IR_COD_Cmd 0x1
542
543 #define ATAPI_IR_IO 0x02
544 #define ATAPI_IR_IO_toDev 0x00
545 #define ATAPI_IR_IO_toHost 0x02
546
547 #define ATAPI_IR_Mask 0x03
548
549 //
550 // ATA Features
551 //
552
553 #define ATA_F_DMA 0x01 /* enable DMA */
554 #define ATA_F_OVL 0x02 /* enable overlap */
555 #define ATA_F_DMAREAD 0x04 /* DMA Packet (ATAPI) read */
556
557 #define ATA_C_F_SETXFER 0x03 /* set transfer mode */
558
559 #define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
560 #define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
561
562 #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
563 #define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
564
565 #define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
566 #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
567
568 #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
569 #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
570
571 #define ATA_C_F_ENAB_MEDIASTAT 0x95 /* enable media status */
572 #define ATA_C_F_DIS_MEDIASTAT 0x31 /* disable media status */
573
574 #define ATA_C_F_ENAB_APM 0x05 /* enable advanced power management */
575 #define ATA_C_F_DIS_APM 0x85 /* disable advanced power management */
576 #define ATA_C_F_APM_CNT_MAX_PERF 0xfe /* maximum performance */
577 #define ATA_C_F_APM_CNT_MIN_NO_STANDBY 0x80 /* min. power w/o standby */
578 #define ATA_C_F_APM_CNT_MIN_STANDBY 0x01 /* min. power with standby */
579
580 #define ATA_C_F_ENAB_ACOUSTIC 0x42 /* enable acoustic management */
581 #define ATA_C_F_DIS_ACOUSTIC 0xc2 /* disable acoustic management */
582 #define ATA_C_F_AAM_CNT_MAX_PERF 0xfe /* maximum performance */
583 #define ATA_C_F_AAM_CNT_MAX_POWER_SAVE 0x80 /* min. power */
584
585 // New SMART Feature definitions
586 #ifndef READ_LOG_SECTOR
587 #define READ_LOG_SECTOR 0xD5
588 #define WRITE_LOG_SECTOR 0xD6
589 #define WRITE_THRESHOLDS 0xD7
590 #define AUTO_OFFLINE 0xDB
591 #endif // READ_LOG_SECTOR
592
593 //
594 // ATAPI interrupt reasons
595 //
596
597 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
598 #define ATA_I_IN 0x02 /* read (1) | write (0) */
599 #define ATA_I_RELEASE 0x04 /* released bus (1) */
600 #define ATA_I_TAGMASK 0xf8 /* tag mask */
601
602 // IDENTIFY data
603 //
604
605 typedef struct _IDENTIFY_DATA {
606 UCHAR AtapiCmdSize:2; // 00 00
607 #define ATAPI_PSIZE_12 0 /* 12 bytes */
608 #define ATAPI_PSIZE_16 1 /* 16 bytes */
609 UCHAR :3;
610 UCHAR DrqType:2; // 00 00
611 #define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
612 #define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
613 #define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
614 UCHAR Removable:1;
615
616 UCHAR DeviceType:5;
617 #define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
618 #define ATAPI_TYPE_TAPE 1 /* streaming tape */
619 #define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
620 #define ATAPI_TYPE_OPTICAL 7 /* optical disk */
621 UCHAR :1;
622 UCHAR CmdProtocol:2; // 00 00
623 #define ATAPI_PROTO_ATAPI 2
624 // USHORT GeneralConfiguration; // 00 00
625
626 USHORT NumberOfCylinders; // 02 1
627 USHORT Reserved1; // 04 2
628 USHORT NumberOfHeads; // 06 3
629 USHORT UnformattedBytesPerTrack; // 08 4 // Now obsolete
630 USHORT UnformattedBytesPerSector; // 0A 5 // Now obsolete
631 USHORT SectorsPerTrack; // 0C 6
632
633 USHORT VendorUnique1[3]; // 0E 7-9
634 UCHAR SerialNumber[20]; // 14 10-19
635
636 USHORT BufferType; // 28 20
637 #define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
638 #define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
639 #define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
640
641 USHORT BufferSectorSize; // 2A 21
642 USHORT NumberOfEccBytes; // 2C 22
643 USHORT FirmwareRevision[4]; // 2E 23-26
644 USHORT ModelNumber[20]; // 36 27-46
645 UCHAR MaximumBlockTransfer; // 5E 47
646 UCHAR VendorUnique2; // 5F
647
648 USHORT DoubleWordIo; // 60 48
649
650 USHORT Reserved62_0:8; // 62 49
651 USHORT SupportDma:1;
652 USHORT SupportLba:1;
653 USHORT DisableIordy:1;
654 USHORT SupportIordy:1;
655 USHORT SoftReset:1;
656 USHORT StandbyOverlap:1;
657 USHORT SupportQTag:1; /* supports queuing overlap */
658 USHORT SupportIDma:1; /* interleaved DMA supported */
659 /* USHORT Capabilities; // 62 49
660 #define IDENTIFY_CAPABILITIES_SUPPORT_DMA 0x0100
661 #define IDENTIFY_CAPABILITIES_SUPPORT_LBA 0x0200
662 #define IDENTIFY_CAPABILITIES_DISABLE_IORDY 0x0400
663 #define IDENTIFY_CAPABILITIES_SUPPORT_IORDY 0x0800
664 #define IDENTIFY_CAPABILITIES_SOFT_RESET 0x1000
665 #define IDENTIFY_CAPABILITIES_STDBY_OVLP 0x2000
666 #define IDENTIFY_CAPABILITIES_SUPPORT_QTAG 0x4000
667 #define IDENTIFY_CAPABILITIES_SUPPORT_IDMA 0x8000*/
668
669 USHORT DeviceStandbyMin:1; // 64 50
670 USHORT Reserved50_1:13;
671 USHORT DeviceCapability1:1;
672 USHORT DeviceCapability0:1;
673 // USHORT Reserved2;
674
675 UCHAR Vendor51; // 66 51
676 UCHAR PioCycleTimingMode; // 67
677
678 UCHAR Vendor52; // 68 52
679 UCHAR DmaCycleTimingMode; // 69
680
681 USHORT TranslationFieldsValid:1; // 6A 53 /* 54-58 */
682 USHORT PioTimingsValid:1; /* 64-70 */
683 USHORT UdmaModesValid:1; /* 88 */
684 USHORT Reserved3:13;
685
686 USHORT NumberOfCurrentCylinders; // 6C 54 \-
687 USHORT NumberOfCurrentHeads; // 6E 55 \-
688 USHORT CurrentSectorsPerTrack; // 70 56 /- obsolete USHORT[5]
689 ULONG CurrentSectorCapacity; // 72 57-58 /-
690
691 USHORT CurrentMultiSector:8; // 59
692 USHORT CurrentMultiSectorValid:1;
693 USHORT Reserved59_9_11:3;
694 USHORT SanitizeSupported:1;
695 USHORT CryptoScrambleExtSupported:1;
696 USHORT OverwriteExtSupported:1;
697 USHORT BlockEraseExtSupported:1;
698
699 ULONG UserAddressableSectors; // 60-61
700
701 union {
702 struct {
703 USHORT SingleWordDMASupport : 8; // 62 ATA, obsolete
704 USHORT SingleWordDMAActive : 8; //
705 };
706 struct {
707 USHORT UDMASupport : 7; // 62 ATAPI
708 USHORT MultiWordDMASupport : 3;
709 USHORT DMASupport : 1;
710 USHORT Reaseved62_11_14 : 4;
711 USHORT DMADirRequired : 1;
712 } AtapiDMA;
713 };
714
715 USHORT MultiWordDMASupport : 8; // 63
716 USHORT MultiWordDMAActive : 8;
717
718 USHORT AdvancedPIOModes : 8; // 64
719 USHORT Reserved4 : 8;
720
721 #define AdvancedPIOModes_3 1
722 #define AdvancedPIOModes_4 2
723 #define AdvancedPIOModes_5 4 // non-standard
724
725 USHORT MinimumMWXferCycleTime; // 65
726 USHORT RecommendedMWXferCycleTime; // 66
727 USHORT MinimumPIOCycleTime; // 67
728 USHORT MinimumPIOCycleTimeIORDY; // 68
729
730 USHORT Reserved69_0_4:5; // 69
731 USHORT ReadZeroAfterTrim:1;
732 USHORT Lba28Support:1;
733 USHORT Reserved69_7_IEEE1667:1;
734 USHORT MicrocodeDownloadDMA:1;
735 USHORT MaxPwdDMA:1;
736 USHORT WriteBufferDMA:1;
737 USHORT ReadBufferDMA:1;
738 USHORT DevConfigDMA:1;
739 USHORT LongSectorErrorReporting:1;
740 USHORT DeterministicReadAfterTrim:1;
741 USHORT CFastSupport:1;
742
743 USHORT Reserved70; // 70
744 USHORT ReleaseTimeOverlapped; // 71
745 USHORT ReleaseTimeServiceCommand; // 72
746 USHORT Reserved73_74[2]; // 73-74
747
748 USHORT QueueLength : 5; // 75
749 USHORT Reserved75_6 : 11;
750
751 USHORT SataCapabilities; // 76
752 #define ATA_SATA_GEN1 0x0002
753 #define ATA_SATA_GEN2 0x0004
754 #define ATA_SATA_GEN3 0x0008
755 #define ATA_SUPPORT_NCQ 0x0100
756 #define ATA_SUPPORT_IFPWRMNGTRCV 0x0200
757 #define ATA_SUPPORT_PHY_EVENT_COUNTER 0x0400
758 #define ATA_SUPPORT_NCQ_UNLOAD 0x0800
759 #define ATA_SUPPORT_NCQ_PRI_INFO 0x1000
760
761 USHORT Reserved77; // 77
762
763 USHORT SataSupport; // 78
764 #define ATA_SUPPORT_NONZERO 0x0002
765 #define ATA_SUPPORT_AUTOACTIVATE 0x0004
766 #define ATA_SUPPORT_IFPWRMNGT 0x0008
767 #define ATA_SUPPORT_INORDERDATA 0x0010
768
769 USHORT SataEnable; // 79
770 USHORT MajorRevision; // 80
771 USHORT MinorRevision; // 81
772
773 #define ATA_VER_MJ_ATA4 0x0010
774 #define ATA_VER_MJ_ATA5 0x0020
775 #define ATA_VER_MJ_ATA6 0x0040
776 #define ATA_VER_MJ_ATA7 0x0080
777 #define ATA_VER_MJ_ATA8_ASC 0x0100
778
779 struct {
780 USHORT Smart:1; // 82/85
781 USHORT Security:1;
782 USHORT Removable:1;
783 USHORT PowerMngt:1;
784 USHORT Packet:1;
785 USHORT WriteCache:1;
786 USHORT LookAhead:1;
787 USHORT ReleaseDRQ:1;
788 USHORT ServiceDRQ:1;
789 USHORT Reset:1;
790 USHORT Protected:1;
791 USHORT Reserved_82_11:1;
792 USHORT WriteBuffer:1;
793 USHORT ReadBuffer:1;
794 USHORT Nop:1;
795 USHORT Reserved_82_15:1;
796
797 USHORT Microcode:1; // 83/86
798 USHORT Queued:1; //
799 USHORT CFA:1; //
800 USHORT APM:1; //
801 USHORT Notify:1; //
802 USHORT Standby:1; //
803 USHORT Spinup:1; //
804 USHORT Reserver_83_7:1;
805 USHORT MaxSecurity:1; //
806 USHORT AutoAcoustic:1; //
807 USHORT Address48:1; //
808 USHORT ConfigOverlay:1; //
809 USHORT FlushCache:1; //
810 USHORT FlushCache48:1; //
811 USHORT SupportOne:1; //
812 USHORT SupportZero:1; //
813
814 USHORT SmartErrorLog:1; // 84/87
815 USHORT SmartSelfTest:1;
816 USHORT MediaSerialNo:1;
817 USHORT MediaCardPass:1;
818 USHORT Streaming:1;
819 USHORT Logging:1;
820 USHORT Reserver_84_6:8;
821 USHORT ExtendedOne:1; //
822 USHORT ExtendedZero:1; //
823 } FeaturesSupport, FeaturesEnabled;
824
825 USHORT UltraDMASupport : 8; // 88
826 USHORT UltraDMAActive : 8;
827
828 USHORT EraseTime; // 89
829 USHORT EnhancedEraseTime; // 90
830 USHORT CurentAPMLevel; // 91
831
832 USHORT MasterPasswdRevision; // 92
833
834 USHORT HwResMaster : 8; // 93
835 USHORT HwResSlave : 5;
836 USHORT HwResCableId : 1;
837 USHORT HwResValid : 2;
838
839 #define IDENTIFY_CABLE_ID_VALID 0x01
840
841 USHORT CurrentAcoustic : 8; // 94
842 USHORT VendorAcoustic : 8;
843
844 USHORT StreamMinReqSize; // 95
845 USHORT StreamTransferTime; // 96
846 USHORT StreamAccessLatency; // 97
847 ULONG StreamGranularity; // 98-99
848
849 ULONGLONG UserAddressableSectors48; // 100-103
850
851 USHORT StreamingTransferTimePIO; // 104
852 USHORT MaxLBARangeDescBlockCount; // 105 // in 512b blocks
853 union {
854 USHORT PhysLogSectorSize; // 106
855 struct {
856 USHORT PLSS_Size:4;
857 USHORT PLSS_Reserved:8;
858 USHORT PLSS_LargeL:1; // =1 if 117-118 are valid
859 USHORT PLSS_LargeP:1;
860 USHORT PLSS_Signature:2; // = 0x01 = 01b
861 };
862 };
863 USHORT InterSeekDelay; // 107
864 USHORT WorldWideName[4]; // 108-111
865 USHORT Reserved112[5]; // 112-116
866
867 ULONG LargeSectorSize; // 117-118
868
869 USHORT Reserved119[8]; // 119-126
870
871 USHORT RemovableStatus; // 127
872 USHORT SecurityStatus; // 128
873
874 USHORT Reserved129[31]; // 129-159
875 USHORT CfAdvPowerMode; // 160
876 USHORT Reserved161[7]; // 161-167
877 USHORT DeviceNominalFormFactor:4; // 168
878 USHORT Reserved168_4_15:12;
879 USHORT DataSetManagementSupported:1; // 169
880 USHORT Reserved169_1_15:15;
881 USHORT AdditionalProdNum[4]; // 170-173
882 USHORT Reserved174[2]; // 174-175
883 USHORT MediaSerial[30]; // 176-205
884 union {
885 USHORT SCT; // 206
886 struct {
887 USHORT SCT_Supported:1;
888 USHORT Reserved:1;
889 USHORT SCT_WriteSame:1;
890 USHORT SCT_ErrorRecovery:1;
891 USHORT SCT_Feature:1;
892 USHORT SCT_DataTables:1;
893 USHORT Reserved_6_15:10;
894 };
895 };
896 USHORT Reserved_CE_ATA[2]; // 207-208
897 USHORT LogicalSectorOffset:14; // 209
898 USHORT Reserved209_14_One:1;
899 USHORT Reserved209_15_Zero:1;
900
901 USHORT WriteReadVerify_CountMode2[2]; // 210-211
902 USHORT WriteReadVerify_CountMode3[2]; // 212-213
903
904 USHORT NVCache_PM_Supported:1; // 214
905 USHORT NVCache_PM_Enabled:1;
906 USHORT NVCache_Reserved_2_3:2;
907 USHORT NVCache_Enabled:1;
908 USHORT NVCache_Reserved_5_7:3;
909 USHORT NVCache_PM_Version:4;
910 USHORT NVCache_Version:4;
911
912 USHORT NVCache_Size_LogicalBlocks[2]; // 215-216
913 USHORT NominalMediaRotationRate; // 217
914 USHORT Reserved218; // 218
915 USHORT NVCache_DeviceSpinUpTime:8; // 219
916 USHORT NVCache_Reserved219_8_15:8;
917
918 USHORT WriteReadVerify_CurrentMode:8; // 220
919 USHORT WriteReadVerify_Reserved220_8_15:8;
920
921 USHORT Reserved221; // 221
922 union {
923 struct {
924 USHORT VersionFlags:12;
925 USHORT TransportType:4;
926 };
927 struct {
928 USHORT ATA8_APT:1;
929 USHORT ATA_ATAPI7:1;
930 USHORT Reserved:14;
931 } PATA;
932 struct {
933 USHORT ATA8_AST:1;
934 USHORT v10a:1;
935 USHORT II_Ext:1;
936 USHORT v25:1;
937 USHORT v26:1;
938 USHORT v30:1;
939 USHORT Reserved:10;
940 } SATA;
941 USHORT Flags;
942 } TransportMajor;
943 USHORT TransportMinor; // 223
944
945 USHORT Reserved224[10]; // 224-233
946
947 USHORT MinBlocks_MicrocodeDownload_Mode3; // 234
948 USHORT MaxBlocks_MicrocodeDownload_Mode3; // 235
949
950 USHORT Reserved236[19]; // 236-254
951
952 union {
953 USHORT Integrity; // 255
954 struct {
955 #define ATA_ChecksumValid 0xA5
956 USHORT ChecksumValid:8;
957 USHORT Checksum:8;
958 };
959 };
960 } IDENTIFY_DATA, *PIDENTIFY_DATA;
961
962 //
963 // Identify data without the Reserved4.
964 //
965
966 #define IDENTIFY_DATA2 IDENTIFY_DATA
967 #define PIDENTIFY_DATA2 PIDENTIFY_DATA
968
969 /*typedef struct _IDENTIFY_DATA2 {
970 UCHAR AtapiCmdSize:2; // 00 00
971 UCHAR :3;
972 UCHAR DrqType:2; // 00 00
973 UCHAR Removable:1;
974
975 UCHAR DeviceType:5;
976 UCHAR :1;
977 UCHAR CmdProtocol:2; // 00 00
978 // USHORT GeneralConfiguration; // 00
979
980 USHORT NumberOfCylinders; // 02
981 USHORT Reserved1; // 04
982 USHORT NumberOfHeads; // 06
983 USHORT UnformattedBytesPerTrack; // 08
984 USHORT UnformattedBytesPerSector; // 0A
985 USHORT SectorsPerTrack; // 0C
986 USHORT VendorUnique1[3]; // 0E
987 UCHAR SerialNumber[20]; // 14
988 USHORT BufferType; // 28
989 USHORT BufferSectorSize; // 2A
990 USHORT NumberOfEccBytes; // 2C
991 USHORT FirmwareRevision[4]; // 2E
992 USHORT ModelNumber[20]; // 36
993 UCHAR MaximumBlockTransfer; // 5E
994 UCHAR VendorUnique2; // 5F
995 USHORT DoubleWordIo; // 60
996 USHORT Capabilities; // 62
997 USHORT Reserved2; // 64
998 UCHAR VendorUnique3; // 66
999 UCHAR PioCycleTimingMode; // 67
1000 UCHAR VendorUnique4; // 68
1001 UCHAR DmaCycleTimingMode; // 69
1002 USHORT TranslationFieldsValid:1; // 6A
1003 USHORT Reserved3:15;
1004 USHORT NumberOfCurrentCylinders; // 6C
1005 USHORT NumberOfCurrentHeads; // 6E
1006 USHORT CurrentSectorsPerTrack; // 70
1007 ULONG CurrentSectorCapacity; // 72
1008 } IDENTIFY_DATA2, *PIDENTIFY_DATA2;*/
1009
1010 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)
1011
1012
1013 // IDENTIFY DMA timing cycle modes.
1014 #define IDENTIFY_DMA_CYCLES_MODE_0 0x00
1015 #define IDENTIFY_DMA_CYCLES_MODE_1 0x01
1016 #define IDENTIFY_DMA_CYCLES_MODE_2 0x02
1017
1018 // for IDE_COMMAND_DATA_SET_MGMT
1019 typedef struct _TRIM_DATA {
1020 ULONGLONG Lba:48;
1021 ULONGLONG BlockCount:16;
1022 } TRIM_DATA, *PTRIM_DATA;
1023
1024 /*
1025 #define PCI_DEV_HW_SPEC(idhi, idlo) \
1026 { #idlo, 4, #idhi, 4}
1027
1028 typedef struct _BROKEN_CONTROLLER_INFORMATION {
1029 PCHAR VendorId;
1030 ULONG VendorIdLength;
1031 PCHAR DeviceId;
1032 ULONG DeviceIdLength;
1033 }BROKEN_CONTROLLER_INFORMATION, *PBROKEN_CONTROLLER_INFORMATION;
1034
1035 BROKEN_CONTROLLER_INFORMATION const BrokenAdapters[] = {
1036 // CMD 640 ATA controller !WARNING! buggy chip data loss possible
1037 PCI_DEV_HW_SPEC( 0640, 1095 ), //{ "1095", 4, "0640", 4},
1038 // ??
1039 PCI_DEV_HW_SPEC( 0601, 1039 ), //{ "1039", 4, "0601", 4}
1040 // RZ 100? ATA controller !WARNING! buggy chip data loss possible
1041 PCI_DEV_HW_SPEC( 1000, 1042 ),
1042 PCI_DEV_HW_SPEC( 1001, 1042 )
1043 };
1044
1045 #define BROKEN_ADAPTERS (sizeof(BrokenAdapters) / sizeof(BROKEN_CONTROLLER_INFORMATION))
1046
1047 typedef struct _NATIVE_MODE_CONTROLLER_INFORMATION {
1048 PCHAR VendorId;
1049 ULONG VendorIdLength;
1050 PCHAR DeviceId;
1051 ULONG DeviceIdLength;
1052 }NATIVE_MODE_CONTROLLER_INFORMATION, *PNATIVE_MODE_CONTROLLER_INFORMATION;
1053
1054 NATIVE_MODE_CONTROLLER_INFORMATION const NativeModeAdapters[] = {
1055 PCI_DEV_HW_SPEC( 0105, 10ad ) //{ "10ad", 4, "0105", 4}
1056 };
1057
1058 #define NUM_NATIVE_MODE_ADAPTERS (sizeof(NativeModeAdapters) / sizeof(NATIVE_MODE_CONTROLLER_INFORMATION))
1059 */
1060 //
1061 // Beautification macros
1062 //
1063
1064 #ifndef USER_MODE
1065
1066 #define GetStatus(chan, Status) \
1067 Status = AtapiReadPort1(chan, IDX_IO2_AltStatus);
1068
1069 #define GetBaseStatus(chan, pStatus) \
1070 pStatus = AtapiReadPort1(chan, IDX_IO1_i_Status);
1071
1072 #define WriteCommand(chan, _Command) \
1073 AtapiWritePort1(chan, IDX_IO1_o_Command, _Command);
1074
1075
1076 #define SelectDrive(chan, unit) { \
1077 if(chan && chan->lun[unit] && chan->lun[unit]->DeviceFlags & DFLAGS_ATAPI_CHANGER) KdPrint3((" Select %d\n", unit)); \
1078 AtapiWritePort1(chan, IDX_IO1_o_DriveSelect, (unit) ? IDE_DRIVE_SELECT_2 : IDE_DRIVE_SELECT_1); \
1079 }
1080
1081
1082 #define ReadBuffer(chan, Buffer, Count, timing) \
1083 AtapiReadBuffer2(chan, IDX_IO1_i_Data, \
1084 Buffer, \
1085 Count, \
1086 timing);
1087
1088 #define WriteBuffer(chan, Buffer, Count, timing) \
1089 AtapiWriteBuffer2(chan, IDX_IO1_o_Data, \
1090 Buffer, \
1091 Count, \
1092 timing);
1093
1094 #define ReadBuffer2(chan, Buffer, Count, timing) \
1095 AtapiReadBuffer4(chan, IDX_IO1_i_Data, \
1096 Buffer, \
1097 Count, \
1098 timing);
1099
1100 #define WriteBuffer2(chan, Buffer, Count, timing) \
1101 AtapiWriteBuffer4(chan, IDX_IO1_o_Data, \
1102 Buffer, \
1103 Count, \
1104 timing);
1105
1106 UCHAR
1107 DDKFASTAPI
1108 WaitOnBusy(
1109 IN struct _HW_CHANNEL* chan/*,
1110 PIDE_REGISTERS_2 BaseIoAddress*/
1111 );
1112
1113 UCHAR
1114 DDKFASTAPI
1115 WaitOnBusyLong(
1116 IN struct _HW_CHANNEL* chan/*,
1117 PIDE_REGISTERS_2 BaseIoAddress*/
1118 );
1119
1120 UCHAR
1121 DDKFASTAPI
1122 WaitOnBaseBusy(
1123 IN struct _HW_CHANNEL* chan/*,
1124 PIDE_REGISTERS_1 BaseIoAddress*/
1125 );
1126
1127 UCHAR
1128 DDKFASTAPI
1129 WaitOnBaseBusyLong(
1130 IN struct _HW_CHANNEL* chan/*,
1131 PIDE_REGISTERS_1 BaseIoAddress*/
1132 );
1133
1134 UCHAR
1135 DDKFASTAPI
1136 WaitForDrq(
1137 IN struct _HW_CHANNEL* chan/*,
1138 PIDE_REGISTERS_2 BaseIoAddress*/
1139 );
1140
1141 UCHAR
1142 DDKFASTAPI
1143 WaitShortForDrq(
1144 IN struct _HW_CHANNEL* chan/*,
1145 PIDE_REGISTERS_2 BaseIoAddress*/
1146 );
1147
1148 VOID
1149 DDKFASTAPI
1150 AtapiSoftReset(
1151 IN struct _HW_CHANNEL* chan,/*
1152 PIDE_REGISTERS_1 BaseIoAddress*/
1153 ULONG DeviceNumber
1154 );
1155
1156
1157 #endif //USER_MODE
1158
1159 #define IS_RDP(OperationCode)\
1160 ((OperationCode == SCSIOP_ERASE)||\
1161 (OperationCode == SCSIOP_LOAD_UNLOAD)||\
1162 (OperationCode == SCSIOP_LOCATE)||\
1163 (OperationCode == SCSIOP_REWIND) ||\
1164 (OperationCode == SCSIOP_SPACE)||\
1165 (OperationCode == SCSIOP_SEEK)||\
1166 /* (OperationCode == SCSIOP_FORMAT_UNIT)||\
1167 (OperationCode == SCSIOP_BLANK)||*/ \
1168 (OperationCode == SCSIOP_WRITE_FILEMARKS))
1169
1170 #ifndef USER_MODE
1171
1172 PSCSI_REQUEST_BLOCK
1173 NTAPI
1174 BuildMechanismStatusSrb (
1175 IN PVOID HwDeviceExtension,
1176 IN PSCSI_REQUEST_BLOCK Srb
1177 );
1178
1179 PSCSI_REQUEST_BLOCK
1180 NTAPI
1181 BuildRequestSenseSrb (
1182 IN PVOID HwDeviceExtension,
1183 IN PSCSI_REQUEST_BLOCK Srb
1184 );
1185
1186 VOID
1187 NTAPI
1188 AtapiHwInitializeChanger (
1189 IN PVOID HwDeviceExtension,
1190 IN ULONG TargetId,
1191 IN PMECHANICAL_STATUS_INFORMATION_HEADER MechanismStatus
1192 );
1193
1194 ULONG
1195 NTAPI
1196 AtapiSendCommand(
1197 IN PVOID HwDeviceExtension,
1198 IN PSCSI_REQUEST_BLOCK Srb,
1199 IN ULONG CmdAction
1200 );
1201
1202 ULONG
1203 NTAPI
1204 IdeSendCommand(
1205 IN PVOID HwDeviceExtension,
1206 IN PSCSI_REQUEST_BLOCK Srb,
1207 IN ULONG CmdAction
1208 );
1209
1210 #define AtapiCopyMemory RtlCopyMemory
1211
1212 VOID
1213 NTAPI
1214 AtapiHexToString (
1215 ULONG Value,
1216 PCHAR *Buffer
1217 );
1218
1219 #define AtapiStringCmp(s1, s2, n) _strnicmp(s1, s2, n)
1220
1221 BOOLEAN
1222 NTAPI
1223 AtapiInterrupt(
1224 IN PVOID HwDeviceExtension
1225 );
1226
1227 BOOLEAN
1228 NTAPI
1229 AtapiInterrupt__(
1230 IN PVOID HwDeviceExtension,
1231 IN UCHAR c
1232 );
1233
1234 UCHAR
1235 NTAPI
1236 AtapiCheckInterrupt__(
1237 IN PVOID HwDeviceExtension,
1238 IN UCHAR c
1239 );
1240
1241 #define INTERRUPT_REASON_IGNORE 0
1242 #define INTERRUPT_REASON_OUR 1
1243 #define INTERRUPT_REASON_UNEXPECTED 2
1244
1245 BOOLEAN
1246 NTAPI
1247 AtapiHwInitialize(
1248 IN PVOID HwDeviceExtension
1249 );
1250
1251 ULONG
1252 NTAPI
1253 IdeBuildSenseBuffer(
1254 IN PVOID HwDeviceExtension,
1255 IN PSCSI_REQUEST_BLOCK Srb
1256 );
1257
1258 VOID
1259 NTAPI
1260 IdeMediaStatus(
1261 BOOLEAN EnableMSN,
1262 IN PVOID HwDeviceExtension,
1263 IN ULONG lChannel,
1264 IN ULONG DeviceNumber
1265 );
1266
1267 ULONG NTAPI
1268 AtapiFindController(
1269 IN PVOID HwDeviceExtension,
1270 IN PVOID Context,
1271 IN PVOID BusInformation,
1272 IN PCHAR ArgumentString,
1273 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1274 OUT PBOOLEAN Again
1275 );
1276
1277 ULONG
1278 NTAPI
1279 AtapiParseArgumentString(
1280 IN PCCH String,
1281 IN PCCH KeyWord
1282 );
1283
1284 BOOLEAN
1285 NTAPI
1286 IssueIdentify(
1287 IN PVOID HwDeviceExtension,
1288 IN ULONG DeviceNumber,
1289 IN ULONG Channel,
1290 IN UCHAR Command,
1291 IN BOOLEAN NoSetup
1292 );
1293
1294 BOOLEAN
1295 NTAPI
1296 SetDriveParameters(
1297 IN PVOID HwDeviceExtension,
1298 IN ULONG DeviceNumber,
1299 IN ULONG Channel
1300 );
1301
1302 ULONG
1303 NTAPI
1304 CheckDevice(
1305 IN PVOID HwDeviceExtension,
1306 IN ULONG Channel,
1307 IN ULONG deviceNumber,
1308 IN BOOLEAN ResetBus
1309 );
1310
1311 #define UNIATA_FIND_DEV_UNHIDE 0x01
1312
1313 BOOLEAN
1314 NTAPI
1315 FindDevices(
1316 IN PVOID HwDeviceExtension,
1317 IN ULONG Flags,
1318 IN ULONG Channel
1319 );
1320
1321 #endif //USER_MODE
1322
1323 #ifdef __cplusplus
1324 };
1325 #endif //__cplusplus
1326
1327 #ifndef USER_MODE
1328
1329 BOOLEAN
1330 NTAPI
1331 AtapiResetController(
1332 IN PVOID HwDeviceExtension,
1333 IN ULONG PathId
1334 );
1335
1336 BOOLEAN
1337 NTAPI
1338 AtapiStartIo(
1339 IN PVOID HwDeviceExtension,
1340 IN PSCSI_REQUEST_BLOCK Srb
1341 );
1342
1343 BOOLEAN
1344 NTAPI
1345 AtapiStartIo__(
1346 IN PVOID HwDeviceExtension,
1347 IN PSCSI_REQUEST_BLOCK Srb,
1348 IN BOOLEAN TopLevel
1349 );
1350
1351 extern UCHAR
1352 NTAPI
1353 AtaCommand48(
1354 // IN PVOID HwDeviceExtension,
1355 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1356 IN ULONG DeviceNumber,
1357 IN ULONG Channel,
1358 IN UCHAR command,
1359 IN ULONGLONG lba,
1360 IN USHORT count,
1361 IN USHORT feature,
1362 IN ULONG flags
1363 );
1364
1365 extern UCHAR
1366 NTAPI
1367 AtaCommand(
1368 // IN PVOID HwDeviceExtension,
1369 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1370 IN ULONG DeviceNumber,
1371 IN ULONG Channel,
1372 IN UCHAR command,
1373 IN USHORT cylinder,
1374 IN UCHAR head,
1375 IN UCHAR sector,
1376 IN UCHAR count,
1377 IN UCHAR feature,
1378 IN ULONG flags
1379 );
1380
1381 extern LONG
1382 NTAPI
1383 AtaPioMode(PIDENTIFY_DATA2 ident);
1384
1385 extern LONG
1386 NTAPI
1387 AtaWmode(PIDENTIFY_DATA2 ident);
1388
1389 extern LONG
1390 NTAPI
1391 AtaUmode(PIDENTIFY_DATA2 ident);
1392
1393 extern VOID
1394 NTAPI
1395 AtapiDpcDispatch(
1396 IN PKDPC Dpc,
1397 IN PVOID DeferredContext,
1398 IN PVOID SystemArgument1,
1399 IN PVOID SystemArgument2
1400 );
1401
1402 //#define AtaCommand(de, devn, chan, cmd, cyl, hd, sec, cnt, feat, flg)
1403
1404 extern LONG
1405 NTAPI
1406 AtaPio2Mode(LONG pio);
1407
1408 extern LONG
1409 NTAPI
1410 AtaPioMode(PIDENTIFY_DATA2 ident);
1411
1412 extern VOID
1413 NTAPI
1414 AtapiEnableInterrupts(
1415 IN PVOID HwDeviceExtension,
1416 IN ULONG c
1417 );
1418
1419 extern VOID
1420 NTAPI
1421 AtapiDisableInterrupts(
1422 IN PVOID HwDeviceExtension,
1423 IN ULONG c
1424 );
1425
1426 extern VOID
1427 UniataExpectChannelInterrupt(
1428 IN struct _HW_CHANNEL* chan,
1429 IN BOOLEAN Expecting
1430 );
1431
1432 #define CHAN_NOT_SPECIFIED (0xffffffffL)
1433 #define CHAN_NOT_SPECIFIED_CHECK_CABLE (0xfffffffeL)
1434 #define DEVNUM_NOT_SPECIFIED (0xffffffffL)
1435 #define IOMODE_NOT_SPECIFIED (0xffffffffL)
1436
1437 extern ULONG
1438 NTAPI
1439 AtapiRegCheckDevValue(
1440 IN PVOID HwDeviceExtension,
1441 IN ULONG chan,
1442 IN ULONG dev,
1443 IN PCWSTR Name,
1444 IN ULONG Default
1445 );
1446
1447 extern ULONG
1448 NTAPI
1449 AtapiRegCheckParameterValue(
1450 IN PVOID HwDeviceExtension,
1451 IN PCWSTR PathSuffix,
1452 IN PCWSTR Name,
1453 IN ULONG Default
1454 );
1455
1456 extern ULONG g_LogToDisplay;
1457
1458 extern "C"
1459 VOID
1460 _cdecl
1461 _PrintNtConsole(
1462 PCCH DebugMessage,
1463 ...
1464 );
1465
1466 VOID
1467 NTAPI
1468 UniataInitMapBM(
1469 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1470 IN struct _IDE_BUSMASTER_REGISTERS* BaseIoAddressBM_0,
1471 IN BOOLEAN MemIo
1472 );
1473
1474 VOID
1475 NTAPI
1476 UniataInitMapBase(
1477 IN struct _HW_CHANNEL* chan,
1478 IN PIDE_REGISTERS_1 BaseIoAddress1,
1479 IN PIDE_REGISTERS_2 BaseIoAddress2
1480 );
1481
1482 VOID
1483 NTAPI
1484 UniataInitSyncBaseIO(
1485 IN struct _HW_CHANNEL* chan
1486 );
1487
1488 UCHAR
1489 DDKFASTAPI
1490 UniataIsIdle(
1491 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1492 IN UCHAR Status
1493 );
1494
1495 VOID
1496 NTAPI
1497 UniataDumpATARegs(
1498 IN struct _HW_CHANNEL* chan
1499 );
1500
1501 ULONG
1502 NTAPI
1503 EncodeVendorStr(
1504 OUT PWCHAR Buffer,
1505 IN PUCHAR Str,
1506 IN ULONG Length
1507 );
1508
1509 ULONGLONG
1510 NTAPI
1511 UniAtaCalculateLBARegsBack(
1512 struct _HW_LU_EXTENSION* LunExt,
1513 ULONGLONG lba
1514 );
1515
1516 ULONG
1517 NTAPI
1518 UniataAnybodyHome(
1519 IN PVOID HwDeviceExtension,
1520 IN ULONG Channel,
1521 IN ULONG deviceNumber
1522 );
1523
1524 #define ATA_AT_HOME_HDD 0x01
1525 #define ATA_AT_HOME_ATAPI 0x02
1526 #define ATA_AT_HOME_XXX 0x04
1527 #define ATA_AT_HOME_NOBODY 0x00
1528
1529 #define ATA_CMD_FLAG_LBAIOsupp 0x01
1530 #define ATA_CMD_FLAG_48supp 0x02
1531 #define ATA_CMD_FLAG_48 0x04
1532 #define ATA_CMD_FLAG_DMA 0x08
1533 #define ATA_CMD_FLAG_FUA 0x10
1534 #define ATA_CMD_FLAG_In 0x40
1535 #define ATA_CMD_FLAG_Out 0x80
1536
1537 extern UCHAR AtaCommands48[256];
1538 extern UCHAR AtaCommandFlags[256];
1539
1540 /*
1541 We need LBA48 when requested LBA or BlockCount are too large.
1542 But for LBA-based commands we have *special* limitation
1543 */
1544 #define UniAta_need_lba48(command, lba, count, supp48) \
1545 ( ((AtaCommandFlags[command] & ATA_CMD_FLAG_LBAIOsupp) && (supp48) && (((lba+count) >= ATA_MAX_IOLBA28) || (count > 256)) ) || \
1546 (lba > ATA_MAX_LBA28) || (count > 255) )
1547
1548 #define UniAtaClearAtaReq(AtaReq) \
1549 { \
1550 RtlZeroMemory((PCHAR)(AtaReq), FIELD_OFFSET(ATA_REQ, ata)); \
1551 }
1552
1553
1554 //#define ATAPI_DEVICE(de, ldev) (de->lun[ldev].DeviceFlags & DFLAGS_ATAPI_DEVICE)
1555 #define ATAPI_DEVICE(chan, dev) ((chan->lun[dev]->DeviceFlags & DFLAGS_ATAPI_DEVICE) ? TRUE : FALSE)
1556
1557 #ifdef _DEBUG
1558 #define PrintNtConsole _PrintNtConsole
1559 #else //_DEBUG
1560 #define PrintNtConsole(x) {;}
1561 #endif //_DEBUG
1562
1563 #endif //USER_MODE
1564
1565 __inline
1566 BOOLEAN
1567 ata_is_sata(
1568 PIDENTIFY_DATA ident
1569 )
1570 {
1571 return (ident->SataCapabilities && ident->SataCapabilities != 0xffff);
1572 } // end ata_is_sata()
1573
1574 #define IDENT_MODE_MAX FALSE
1575 #define IDENT_MODE_ACTIVE TRUE
1576
1577 __inline
1578 LONG
1579 ata_cur_mode_from_ident(
1580 PIDENTIFY_DATA ident,
1581 BOOLEAN Active
1582 )
1583 {
1584 USHORT mode;
1585 if(ata_is_sata(ident)) {
1586 if(ident->SataCapabilities & ATA_SATA_GEN3) {
1587 return ATA_SA600;
1588 } else
1589 if(ident->SataCapabilities & ATA_SATA_GEN2) {
1590 return ATA_SA300;
1591 } else
1592 if(ident->SataCapabilities & ATA_SATA_GEN1) {
1593 return ATA_SA150;
1594 }
1595 return ATA_SA150;
1596 }
1597
1598 if (ident->UdmaModesValid) {
1599 mode = Active ? ident->UltraDMAActive : ident->UltraDMASupport;
1600 if (mode & 0x40)
1601 return ATA_UDMA0+6;
1602 if (mode & 0x20)
1603 return ATA_UDMA0+5;
1604 if (mode & 0x10)
1605 return ATA_UDMA0+4;
1606 if (mode & 0x08)
1607 return ATA_UDMA0+3;
1608 if (mode & 0x04)
1609 return ATA_UDMA0+2;
1610 if (mode & 0x02)
1611 return ATA_UDMA0+1;
1612 if (mode & 0x01)
1613 return ATA_UDMA0+0;
1614 }
1615
1616 mode = Active ? ident->MultiWordDMAActive : ident->MultiWordDMASupport;
1617 if (ident->MultiWordDMAActive & 0x04)
1618 return ATA_WDMA0+2;
1619 if (ident->MultiWordDMAActive & 0x02)
1620 return ATA_WDMA0+1;
1621 if (ident->MultiWordDMAActive & 0x01)
1622 return ATA_WDMA0+0;
1623
1624 mode = Active ? ident->SingleWordDMAActive : ident->SingleWordDMASupport;
1625 if (ident->SingleWordDMAActive & 0x04)
1626 return ATA_SDMA0+2;
1627 if (ident->SingleWordDMAActive & 0x02)
1628 return ATA_SDMA0+1;
1629 if (ident->SingleWordDMAActive & 0x01)
1630 return ATA_SDMA0+0;
1631
1632 if (ident->PioTimingsValid) {
1633 mode = ident->AdvancedPIOModes;
1634 if (mode & AdvancedPIOModes_5)
1635 return ATA_PIO0+5;
1636 if (mode & AdvancedPIOModes_4)
1637 return ATA_PIO0+4;
1638 if (mode & AdvancedPIOModes_3)
1639 return ATA_PIO0+3;
1640 }
1641 mode = ident->PioCycleTimingMode;
1642 if (ident->PioCycleTimingMode == 2)
1643 return ATA_PIO0+2;
1644 if (ident->PioCycleTimingMode == 1)
1645 return ATA_PIO0+1;
1646 if (ident->PioCycleTimingMode == 0)
1647 return ATA_PIO0+0;
1648
1649 return ATA_PIO;
1650 } // end ata_cur_mode_from_ident()
1651
1652 #pragma pack(pop)
1653
1654 #endif // __GLOBAL_H__
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