drivers/storage/inc/ideuser.h

   1 /*++
   2
   3 Copyright (C) Microsoft Corporation, 1999 - 1999
   4
   5 Module Name:
   6
   7     ideuser.h
   8
   9 Abstract:
  10
  11     These are the structures and defines that are used in the
  12     PCI IDE mini drivers.
  13
  14 Revision History:
  15
  16 --*/
  17
  18 #if !defined (___ideuser_h___)
  19 #define ___ideuser_h___
  20
  21
  22 #define PIO_MODE0           (1 << 0)
  23 #define PIO_MODE1           (1 << 1)
  24 #define PIO_MODE2           (1 << 2)
  25 #define PIO_MODE3           (1 << 3)
  26 #define PIO_MODE4           (1 << 4)
  27
  28 #define SWDMA_MODE0         (1 << 5)
  29 #define SWDMA_MODE1         (1 << 6)
  30 #define SWDMA_MODE2         (1 << 7)
  31
  32 #define MWDMA_MODE0         (1 << 8)
  33 #define MWDMA_MODE1         (1 << 9)
  34 #define MWDMA_MODE2         (1 << 10)
  35
  36 #define UDMA_MODE0          (1 << 11)
  37 #define UDMA_MODE1          (1 << 12)
  38 #define UDMA_MODE2          (1 << 13)
  39 #define UDMA_MODE3          (1 << 14)
  40 #define UDMA_MODE4          (1 << 15)
  41 #define UDMA_MODE5          (1 << 16)
  42
  43 #define PIO_SUPPORT         (PIO_MODE0      | PIO_MODE1     | PIO_MODE2    | PIO_MODE3     | PIO_MODE4)
  44 #define SWDMA_SUPPORT       (SWDMA_MODE0    | SWDMA_MODE1   | SWDMA_MODE2)
  45 #define MWDMA_SUPPORT       (MWDMA_MODE0    | MWDMA_MODE1   | MWDMA_MODE2)
  46 #define UDMA33_SUPPORT      (UDMA_MODE0     | UDMA_MODE1    | UDMA_MODE2)
  47 #define UDMA66_SUPPORT      (UDMA_MODE3     | UDMA_MODE4)
  48 #define UDMA100_SUPPORT     (UDMA_MODE5 )
  49 #define UDMA_SUPPORT        (UNINITIALIZED_TRANSFER_MODE & (~(PIO_SUPPORT | SWDMA_SUPPORT | MWDMA_SUPPORT)))
  50
  51 #define DMA_SUPPORT         (SWDMA_SUPPORT  | MWDMA_SUPPORT | UDMA_SUPPORT)
  52 #define ALL_MODE_SUPPORT    (PIO_SUPPORT | DMA_SUPPORT)
  53
  54 #define PIO0                        0
  55 #define PIO1                        1
  56 #define PIO2                        2
  57 #define PIO3                        3
  58 #define PIO4                        4
  59 #define SWDMA0                      5
  60 #define SWDMA1                      6
  61 #define SWDMA2                      7
  62 #define MWDMA0                      8
  63 #define MWDMA1                      9
  64 #define MWDMA2                      10
  65 #define UDMA0                       11
  66
  67 #define MAX_XFER_MODE               17
  68 #define UNINITIALIZED_CYCLE_TIME    0xffffffff
  69 #define UNINITIALIZED_TRANSFER_MODE 0x7fffffff
  70 #define IS_DEFAULT(mode)    (!(mode & 0x80000000))
  71
  72 #define GenTransferModeMask(i, mode) {\
  73     ULONG temp=0xffffffff; \
  74     mode |= (temp >> (31-(i)));\
  75 }
  76
  77 //
  78 // mode should not be 0
  79 //
  80 #define GetHighestTransferMode(mode, i) {\
  81     ULONG temp=(mode); \
  82     ASSERT(temp); \
  83     i=0; \
  84     while ( temp) { \
  85         temp = (temp >> 1);\
  86         i++;\
  87     } \
  88     i--; \
  89 }
  90
  91 #define GetHighestDMATransferMode(mode, i) {\
  92     ULONG temp=mode >> 5;\
  93     i=5; \
  94     while ( temp) { \
  95         temp = (temp >> 1); \
  96         i++; \
  97     } \
  98     i--; \
  99 }
 100 #define GetHighestPIOTransferMode(mode, i) { \
 101     ULONG temp = (mode & PIO_SUPPORT); \
 102     i=0; \
 103     temp = temp >> 1; \
 104     while (temp) { \
 105         temp = temp >> 1; \
 106         i++; \
 107     } \
 108 }
 109
 110 #define SetDefaultTiming(timingTable, length) {\
 111     timingTable[0]=PIO_MODE0_CYCLE_TIME; \
 112     timingTable[1]=PIO_MODE1_CYCLE_TIME; \
 113     timingTable[2]=PIO_MODE2_CYCLE_TIME; \
 114     timingTable[3]=PIO_MODE3_CYCLE_TIME; \
 115     timingTable[4]=PIO_MODE4_CYCLE_TIME; \
 116     timingTable[5]=SWDMA_MODE0_CYCLE_TIME; \
 117     timingTable[6]=SWDMA_MODE1_CYCLE_TIME; \
 118     timingTable[7]=SWDMA_MODE2_CYCLE_TIME; \
 119     timingTable[8]=MWDMA_MODE0_CYCLE_TIME; \
 120     timingTable[9]=MWDMA_MODE1_CYCLE_TIME; \
 121     timingTable[10]=MWDMA_MODE2_CYCLE_TIME; \
 122     timingTable[11]=UDMA_MODE0_CYCLE_TIME; \
 123     timingTable[12]=UDMA_MODE1_CYCLE_TIME; \
 124     timingTable[13]=UDMA_MODE2_CYCLE_TIME; \
 125     timingTable[14]=UDMA_MODE3_CYCLE_TIME; \
 126     timingTable[15]=UDMA_MODE4_CYCLE_TIME; \
 127     timingTable[16]=UDMA_MODE5_CYCLE_TIME; \
 128     length = MAX_XFER_MODE; \
 129 }
 130
 131 #endif // ___ideuser_h___
 132