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Handled SCSIOP_TEST_UNIT_READY
[reactos.git] / drivers / storage / storahci / storahci.h
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GNU GPLv2 only as published by the Free Software Foundation
4 * PURPOSE: To Implement AHCI Miniport driver targeting storport NT 5.2
5 * PROGRAMMERS: Aman Priyadarshi (aman.eureka@gmail.com)
6 */
7
8 #include <ntddk.h>
9 #include <ata.h>
10 #include <storport.h>
11
12 #define DEBUG 1
13 #pragma warning(disable:4214) // bit field types other than int
14 #pragma warning(disable:4201) // nameless struct/union
15
16 #define MAXIMUM_AHCI_PORT_COUNT 32
17 #define MAXIMUM_AHCI_PRDT_ENTRIES 32
18 #define MAXIMUM_AHCI_PORT_NCS 30
19 #define MAXIMUM_QUEUE_BUFFER_SIZE 255
20 #define MAXIMUM_TRANSFER_LENGTH (128*1024) // 128 KB
21
22 #define DEVICE_ATA_BLOCK_SIZE 512
23
24 // device type (DeviceParams)
25 #define AHCI_DEVICE_TYPE_ATA 1
26 #define AHCI_DEVICE_TYPE_ATAPI 2
27 #define AHCI_DEVICE_TYPE_NODEVICE 3
28
29 // section 3.1.2
30 #define AHCI_Global_HBA_CAP_S64A (1 << 31)
31
32 // FIS Types : http://wiki.osdev.org/AHCI
33 #define FIS_TYPE_REG_H2D 0x27 // Register FIS - host to device
34 #define FIS_TYPE_REG_D2H 0x34 // Register FIS - device to host
35 #define FIS_TYPE_DMA_ACT 0x39 // DMA activate FIS - device to host
36 #define FIS_TYPE_DMA_SETUP 0x41 // DMA setup FIS - bidirectional
37 #define FIS_TYPE_BIST 0x58 // BIST activate FIS - bidirectional
38 #define FIS_TYPE_PIO_SETUP 0x5F // PIO setup FIS - device to host
39 #define FIS_TYPE_DEV_BITS 0xA1 // Set device bits FIS - device to host
40
41 #define AHCI_ATA_CFIS_FisType 0
42 #define AHCI_ATA_CFIS_PMPort_C 1
43 #define AHCI_ATA_CFIS_CommandReg 2
44 #define AHCI_ATA_CFIS_FeaturesLow 3
45 #define AHCI_ATA_CFIS_LBA0 4
46 #define AHCI_ATA_CFIS_LBA1 5
47 #define AHCI_ATA_CFIS_LBA2 6
48 #define AHCI_ATA_CFIS_Device 7
49 #define AHCI_ATA_CFIS_LBA3 8
50 #define AHCI_ATA_CFIS_LBA4 9
51 #define AHCI_ATA_CFIS_LBA5 10
52 #define AHCI_ATA_CFIS_FeaturesHigh 11
53 #define AHCI_ATA_CFIS_SectorCountLow 12
54 #define AHCI_ATA_CFIS_SectorCountHigh 13
55
56 // ATA Functions
57 #define ATA_FUNCTION_ATA_COMMAND 0x100
58 #define ATA_FUNCTION_ATA_IDENTIFY 0x101
59 #define ATA_FUNCTION_ATA_READ 0x102
60
61 // ATAPI Functions
62 #define ATA_FUNCTION_ATAPI_COMMAND 0x200
63
64 // ATA Flags
65 #define ATA_FLAGS_DATA_IN (1 << 1)
66 #define ATA_FLAGS_DATA_OUT (1 << 2)
67 #define ATA_FLAGS_48BIT_COMMAND (1 << 3)
68 #define ATA_FLAGS_USE_DMA (1 << 4)
69
70 #define IsAtaCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATA_COMMAND)
71 #define IsAtapiCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATAPI_COMMAND)
72 #define IsDataTransferNeeded(SrbExtension) (SrbExtension->Flags & (ATA_FLAGS_DATA_IN | ATA_FLAGS_DATA_OUT))
73 #define IsAdapterCAPS64(CAP) (CAP & AHCI_Global_HBA_CAP_S64A)
74
75 // 3.1.1 NCS = CAP[12:08] -> Align
76 #define AHCI_Global_Port_CAP_NCS(x) (((x) & 0xF00) >> 8)
77
78 #define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
79 #ifdef DBG
80 #define AhciDebugPrint(format, ...) StorPortDebugPrint(0, format, __VA_ARGS__)
81 #endif
82
83 typedef
84 VOID
85 (*PAHCI_COMPLETION_ROUTINE) (
86 __in PVOID PortExtension,
87 __in PVOID Srb
88 );
89
90 //////////////////////////////////////////////////////////////
91 // ---- Support Structures --- //
92 //////////////////////////////////////////////////////////////
93
94 // section 3.3.5
95 typedef union _AHCI_INTERRUPT_STATUS
96 {
97 struct
98 {
99 ULONG DHRS:1; //Device to Host Register FIS Interrupt
100 ULONG PSS :1; //PIO Setup FIS Interrupt
101 ULONG DSS :1; //DMA Setup FIS Interrupt
102 ULONG SDBS :1; //Set Device Bits Interrupt
103 ULONG UFS :1; //Unknown FIS Interrupt
104 ULONG DPS :1; //Descriptor Processed
105 ULONG PCS :1; //Port Connect Change Status
106 ULONG DMPS :1; //Device Mechanical Presence Status (DMPS)
107 ULONG Reserved :14;
108 ULONG PRCS :1; //PhyRdy Change Status
109 ULONG IPMS :1; //Incorrect Port Multiplier Status
110 ULONG OFS :1; //Overflow Status
111 ULONG Reserved2 :1;
112 ULONG INFS :1; //Interface Non-fatal Error Status
113 ULONG IFS :1; //Interface Fatal Error Status
114 ULONG HBDS :1; //Host Bus Data Error Status
115 ULONG HBFS :1; //Host Bus Fatal Error Status
116 ULONG TFES :1; //Task File Error Status
117 ULONG CPDS :1; //Cold Port Detect Status
118 };
119
120 ULONG Status;
121 } AHCI_INTERRUPT_STATUS;
122
123 typedef struct _AHCI_FIS_DMA_SETUP
124 {
125 ULONG ULONG0_1; // FIS_TYPE_DMA_SETUP
126 // Port multiplier
127 // Reserved
128 // Data transfer direction, 1 - device to host
129 // Interrupt bit
130 // Auto-activate. Specifies if DMA Activate FIS is needed
131 UCHAR Reserved[2]; // Reserved
132 ULONG DmaBufferLow; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
133 ULONG DmaBufferHigh;
134 ULONG Reserved2; // More reserved
135 ULONG DmaBufferOffset; // Byte offset into buffer. First 2 bits must be 0
136 ULONG TranferCount; // Number of bytes to transfer. Bit 0 must be 0
137 ULONG Reserved3; // Reserved
138 } AHCI_FIS_DMA_SETUP;
139
140 typedef struct _AHCI_PIO_SETUP_FIS
141 {
142 UCHAR FisType;
143 UCHAR Reserved1 :5;
144 UCHAR D :1;
145 UCHAR I :1;
146 UCHAR Reserved2 :1;
147 UCHAR Status;
148 UCHAR Error;
149
150 UCHAR SectorNumber;
151 UCHAR CylLow;
152 UCHAR CylHigh;
153 UCHAR Dev_Head;
154
155 UCHAR SectorNumb_Exp;
156 UCHAR CylLow_Exp;
157 UCHAR CylHigh_Exp;
158 UCHAR Reserved3;
159
160 UCHAR SectorCount;
161 UCHAR SectorCount_Exp;
162 UCHAR Reserved4;
163 UCHAR E_Status;
164
165 USHORT TransferCount;
166 UCHAR Reserved5[2];
167 } AHCI_PIO_SETUP_FIS;
168
169 typedef struct _AHCI_D2H_REGISTER_FIS
170 {
171 UCHAR FisType;
172 UCHAR Reserved1 :6;
173 UCHAR I:1;
174 UCHAR Reserved2 :1;
175 UCHAR Status;
176 UCHAR Error;
177
178 UCHAR SectorNumber;
179 UCHAR CylLow;
180 UCHAR CylHigh;
181 UCHAR Dev_Head;
182
183 UCHAR SectorNum_Exp;
184 UCHAR CylLow_Exp;
185 UCHAR CylHigh_Exp;
186 UCHAR Reserved;
187
188 UCHAR SectorCount;
189 UCHAR SectorCount_Exp;
190 UCHAR Reserved3[2];
191
192 UCHAR Reserved4[4];
193 } AHCI_D2H_REGISTER_FIS;
194
195 typedef struct _AHCI_SET_DEVICE_BITS_FIS
196 {
197 UCHAR FisType;
198
199 UCHAR PMPort: 4;
200 UCHAR Reserved1 :2;
201 UCHAR I :1;
202 UCHAR N :1;
203
204 UCHAR Status_Lo :3;
205 UCHAR Reserved2 :1;
206 UCHAR Status_Hi :3;
207 UCHAR Reserved3 :1;
208
209 UCHAR Error;
210
211 UCHAR Reserved5[4];
212 } AHCI_SET_DEVICE_BITS_FIS;
213
214 typedef struct _AHCI_QUEUE
215 {
216 PVOID Buffer[MAXIMUM_QUEUE_BUFFER_SIZE]; // because Storahci hold Srb queue of 255 size
217 ULONG Head;
218 ULONG Tail;
219 } AHCI_QUEUE, *PAHCI_QUEUE;
220
221 //////////////////////////////////////////////////////////////
222 // --------------------------- //
223 //////////////////////////////////////////////////////////////
224
225 typedef union _AHCI_COMMAND_HEADER_DESCRIPTION
226 {
227 struct
228 {
229 ULONG CFL : 5; // Command FIS Length
230 ULONG A : 1; // IsATAPI
231 ULONG W : 1; // Write
232 ULONG P : 1; // Prefetchable
233
234 ULONG R : 1; // Reset
235 ULONG B : 1; // BIST
236 ULONG C : 1; //Clear Busy upon R_OK
237 ULONG RSV : 1;
238 ULONG PMP : 4; //Port Multiplier Port
239
240 ULONG PRDTL : 16; //Physical Region Descriptor Table Length
241 };
242
243 ULONG Status;
244 } AHCI_COMMAND_HEADER_DESCRIPTION;
245
246 typedef union _AHCI_GHC
247 {
248 struct
249 {
250 ULONG HR : 1;
251 ULONG IE : 1;
252 ULONG MRSM : 1;
253 ULONG RSV0 : 28;
254 ULONG AE : 1;
255 };
256
257 ULONG Status;
258 } AHCI_GHC;
259
260 // section 3.3.7
261 typedef union _AHCI_PORT_CMD
262 {
263 struct
264 {
265 ULONG ST : 1;
266 ULONG SUD : 1;
267 ULONG POD : 1;
268 ULONG CLO : 1;
269 ULONG FRE : 1;
270 ULONG RSV0 : 3;
271 ULONG CCS : 5;
272 ULONG MPSS : 1;
273 ULONG FR : 1;
274 ULONG CR : 1;
275 ULONG CPS : 1;
276 ULONG PMA : 1;
277 ULONG HPCP : 1;
278 ULONG MPSP : 1;
279 ULONG CPD : 1;
280 ULONG ESP : 1;
281 ULONG FBSCP : 1;
282 ULONG APSTE : 1;
283 ULONG ATAPI : 1;
284 ULONG DLAE : 1;
285 ULONG ALPE : 1;
286 ULONG ASP : 1;
287 ULONG ICC : 4;
288 };
289
290 ULONG Status;
291 } AHCI_PORT_CMD;
292
293 typedef union _AHCI_SERIAL_ATA_CONTROL
294 {
295 struct
296 {
297 ULONG DET :4;
298 ULONG SPD :4;
299 ULONG IPM :4;
300 ULONG SPM :4;
301 ULONG PMP :4;
302 ULONG DW11_Reserved :12;
303 };
304
305 ULONG Status;
306 } AHCI_SERIAL_ATA_CONTROL;
307
308 typedef union _AHCI_SERIAL_ATA_STATUS
309 {
310 struct
311 {
312 ULONG DET :4;
313 ULONG SPD :4;
314 ULONG IPM :4;
315 ULONG RSV0 :20;
316 };
317
318 ULONG Status;
319 } AHCI_SERIAL_ATA_STATUS;
320
321 typedef union _AHCI_TASK_FILE_DATA
322 {
323 struct
324 {
325 struct _STS
326 {
327 UCHAR ERR : 1;
328 UCHAR CS1 : 2;
329 UCHAR DRQ : 1;
330 UCHAR CS2 : 3;
331 UCHAR BSY : 1;
332 } STS;
333 UCHAR ERR;
334 USHORT RSV;
335 };
336
337 ULONG Status;
338 } AHCI_TASK_FILE_DATA;
339
340 typedef struct _AHCI_PRDT
341 {
342 ULONG DBA;
343 ULONG DBAU;
344 ULONG RSV0;
345
346 ULONG DBC : 22;
347 ULONG RSV1 : 9;
348 ULONG I : 1;
349 } AHCI_PRDT, *PAHCI_PRDT;
350
351 // 4.2.3 Command Table
352 typedef struct _AHCI_COMMAND_TABLE
353 {
354 // (16 * 32) + 64 + 16 + 48 = 648
355 // 128 byte aligned :D
356 UCHAR CFIS[64];
357 UCHAR ACMD[16];
358 UCHAR RSV0[48];
359 AHCI_PRDT PRDT[MAXIMUM_AHCI_PRDT_ENTRIES];
360 } AHCI_COMMAND_TABLE, *PAHCI_COMMAND_TABLE;
361
362 // 4.2.2 Command Header
363 typedef struct _AHCI_COMMAND_HEADER
364 {
365 AHCI_COMMAND_HEADER_DESCRIPTION DI; // DW 0
366 ULONG PRDBC; // DW 1
367 ULONG CTBA; // DW 2
368 ULONG CTBA_U; // DW 3
369 ULONG Reserved[4]; // DW 4-7
370 } AHCI_COMMAND_HEADER, *PAHCI_COMMAND_HEADER;
371
372 // Received FIS
373 typedef struct _AHCI_RECEIVED_FIS
374 {
375 struct _AHCI_FIS_DMA_SETUP DmaSetupFIS; // 0x00 -- DMA Setup FIS
376 ULONG pad0; // 4 BYTE padding
377 struct _AHCI_PIO_SETUP_FIS PioSetupFIS; // 0x20 -- PIO Setup FIS
378 ULONG pad1[3]; // 12 BYTE padding
379 struct _AHCI_D2H_REGISTER_FIS RegisterFIS; // 0x40 -- Register – Device to Host FIS
380 ULONG pad2; // 4 BYTE padding
381 struct _AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS; // 0x58 -- Set Device Bit FIS
382 ULONG UnknowFIS[16]; // 0x60 -- Unknown FIS
383 ULONG Reserved[24]; // 0xA0 -- Reserved
384 } AHCI_RECEIVED_FIS, *PAHCI_RECEIVED_FIS;
385
386 // Holds Port Information
387 typedef struct _AHCI_PORT
388 {
389 ULONG CLB; // 0x00, command list base address, 1K-byte aligned
390 ULONG CLBU; // 0x04, command list base address upper 32 bits
391 ULONG FB; // 0x08, FIS base address, 256-byte aligned
392 ULONG FBU; // 0x0C, FIS base address upper 32 bits
393 ULONG IS; // 0x10, interrupt status
394 ULONG IE; // 0x14, interrupt enable
395 ULONG CMD; // 0x18, command and status
396 ULONG RSV0; // 0x1C, Reserved
397 ULONG TFD; // 0x20, task file data
398 ULONG SIG; // 0x24, signature
399 ULONG SSTS; // 0x28, SATA status (SCR0:SStatus)
400 ULONG SCTL; // 0x2C, SATA control (SCR2:SControl)
401 ULONG SERR; // 0x30, SATA error (SCR1:SError)
402 ULONG SACT; // 0x34, SATA active (SCR3:SActive)
403 ULONG CI; // 0x38, command issue
404 ULONG SNTF; // 0x3C, SATA notification (SCR4:SNotification)
405 ULONG FBS; // 0x40, FIS-based switch control
406 ULONG RSV1[11]; // 0x44 ~ 0x6F, Reserved
407 ULONG Vendor[4]; // 0x70 ~ 0x7F, vendor specific
408 } AHCI_PORT, *PAHCI_PORT;
409
410 typedef union _AHCI_INTERRUPT_ENABLE
411 {
412 struct
413 {
414 ULONG DHRE :1;
415 ULONG PSE :1;
416 ULONG DSE :1;
417 ULONG SDBE :1;
418 ULONG UFE :1;
419 ULONG DPE :1;
420 ULONG PCE :1;
421 ULONG DMPE :1;
422 ULONG DW5_Reserved :14;
423 ULONG PRCE :1;
424 ULONG IPME :1;
425 ULONG OFE :1;
426 ULONG DW5_Reserved2 :1;
427 ULONG INFE :1;
428 ULONG IFE :1;
429 ULONG HBDE :1;
430 ULONG HBFE :1;
431 ULONG TFEE :1;
432 ULONG CPDE :1;
433 };
434
435 ULONG Status;
436 } AHCI_INTERRUPT_ENABLE;
437
438 typedef struct _AHCI_MEMORY_REGISTERS
439 {
440 // 0x00 - 0x2B, Generic Host Control
441 ULONG CAP; // 0x00, Host capability
442 ULONG GHC; // 0x04, Global host control
443 ULONG IS; // 0x08, Interrupt status
444 ULONG PI; // 0x0C, Port implemented
445 ULONG VS; // 0x10, Version
446 ULONG CCC_CTL; // 0x14, Command completion coalescing control
447 ULONG CCC_PTS; // 0x18, Command completion coalescing ports
448 ULONG EM_LOC; // 0x1C, Enclosure management location
449 ULONG EM_CTL; // 0x20, Enclosure management control
450 ULONG CAP2; // 0x24, Host capabilities extended
451 ULONG BOHC; // 0x28, BIOS/OS handoff control and status
452 ULONG Reserved[0x1d]; // 0x2C - 0x9F, Reserved
453 ULONG VendorSpecific[0x18]; // 0xA0 - 0xFF, Vendor specific registers
454 AHCI_PORT PortList[MAXIMUM_AHCI_PORT_COUNT];
455 } AHCI_MEMORY_REGISTERS, *PAHCI_MEMORY_REGISTERS;
456
457 // Holds information for each attached attached port to a given adapter.
458 typedef struct _AHCI_PORT_EXTENSION
459 {
460 ULONG PortNumber;
461 ULONG QueueSlots; // slots which we have already assigned task (Slot)
462 ULONG CommandIssuedSlots; // slots which has been programmed
463 ULONG MaxPortQueueDepth;
464
465 struct
466 {
467 UCHAR RemovableDevice;
468 UCHAR Lba48BitMode;
469 UCHAR AccessType;
470 UCHAR DeviceType;
471 UCHAR IsActive;
472 LARGE_INTEGER MaxLba;
473 ULONG BytesPerLogicalSector;
474 ULONG BytesPerPhysicalSector;
475 // UCHAR VendorId[41];
476 // UCHAR RevisionID[9];
477 // UCHAR SerialNumber[21];
478 } DeviceParams;
479
480 STOR_DPC CommandCompletion;
481 PAHCI_PORT Port; // AHCI Port Infomation
482 AHCI_QUEUE SrbQueue; // pending Srbs
483 AHCI_QUEUE CompletionQueue;
484 PSCSI_REQUEST_BLOCK Slot[MAXIMUM_AHCI_PORT_NCS]; // Srbs which has been alloted a port
485 PAHCI_RECEIVED_FIS ReceivedFIS;
486 PAHCI_COMMAND_HEADER CommandList;
487 STOR_DEVICE_POWER_STATE DevicePowerState; // Device Power State
488 PIDENTIFY_DEVICE_DATA IdentifyDeviceData;
489 STOR_PHYSICAL_ADDRESS IdentifyDeviceDataPhysicalAddress;
490 struct _AHCI_ADAPTER_EXTENSION* AdapterExtension; // Port's Adapter Information
491 } AHCI_PORT_EXTENSION, *PAHCI_PORT_EXTENSION;
492
493 // Holds Adapter Information
494 typedef struct _AHCI_ADAPTER_EXTENSION
495 {
496 ULONG SystemIoBusNumber;
497 ULONG SlotNumber;
498 ULONG AhciBaseAddress;
499 PULONG IS;// Interrupt Status, In case of MSIM == `1`
500 ULONG PortImplemented;// bit-mapping of ports which are implemented
501 ULONG PortCount;
502
503 USHORT VendorID;
504 USHORT DeviceID;
505 USHORT RevisionID;
506
507 ULONG Version;
508 ULONG CAP;
509 ULONG CAP2;
510 ULONG LastInterruptPort;
511 ULONG CurrentCommandSlot;
512
513 PVOID NonCachedExtension; // holds virtual address to noncached buffer allocated for Port Extension
514
515 struct
516 {
517 // Message per port or shared port?
518 ULONG MessagePerPort : 1;
519 ULONG Removed : 1;
520 ULONG Reserved : 30; // not in use -- maintain 4 byte alignment
521 } StateFlags;
522
523 PAHCI_MEMORY_REGISTERS ABAR_Address;
524 AHCI_PORT_EXTENSION PortExtension[MAXIMUM_AHCI_PORT_COUNT];
525 } AHCI_ADAPTER_EXTENSION, *PAHCI_ADAPTER_EXTENSION;
526
527 typedef struct _LOCAL_SCATTER_GATHER_LIST
528 {
529 ULONG NumberOfElements;
530 ULONG_PTR Reserved;
531 STOR_SCATTER_GATHER_ELEMENT List[MAXIMUM_AHCI_PRDT_ENTRIES];
532 } LOCAL_SCATTER_GATHER_LIST, *PLOCAL_SCATTER_GATHER_LIST;
533
534 typedef struct _AHCI_SRB_EXTENSION
535 {
536 AHCI_COMMAND_TABLE CommandTable;
537 ULONG AtaFunction;
538 ULONG Flags;
539
540 UCHAR CommandReg;
541 UCHAR FeaturesLow;
542 UCHAR LBA0;
543 UCHAR LBA1;
544 UCHAR LBA2;
545 UCHAR Device;
546 UCHAR LBA3;
547 UCHAR LBA4;
548 UCHAR LBA5;
549 UCHAR FeaturesHigh;
550
551 UCHAR SectorCountLow;
552 UCHAR SectorCountHigh;
553
554 ULONG SlotIndex;
555 LOCAL_SCATTER_GATHER_LIST Sgl;
556 PLOCAL_SCATTER_GATHER_LIST pSgl;
557 PAHCI_COMPLETION_ROUTINE CompletionRoutine;
558
559 // for alignment purpose -- 128 byte alignment
560 // do not try to access (R/W) this field
561 UCHAR Reserved[128];
562 } AHCI_SRB_EXTENSION, *PAHCI_SRB_EXTENSION;
563
564 //////////////////////////////////////////////////////////////
565 // Declarations //
566 //////////////////////////////////////////////////////////////
567
568 VOID
569 AhciProcessIO (
570 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
571 __in UCHAR PathId,
572 __in PSCSI_REQUEST_BLOCK Srb
573 );
574
575 BOOLEAN
576 AhciAdapterReset (
577 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
578 );
579
580 __inline
581 VOID
582 AhciZeroMemory (
583 __out PCHAR Buffer,
584 __in ULONG BufferSize
585 );
586
587 __inline
588 BOOLEAN
589 IsPortValid (
590 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
591 __in ULONG pathId
592 );
593
594 UCHAR DeviceRequestReadWrite (
595 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
596 __in PSCSI_REQUEST_BLOCK Srb,
597 __in PCDB Cdb
598 );
599
600 UCHAR DeviceRequestCapacity (
601 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
602 __in PSCSI_REQUEST_BLOCK Srb,
603 __in PCDB Cdb
604 );
605
606 UCHAR
607 DeviceInquiryRequest (
608 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
609 __in PSCSI_REQUEST_BLOCK Srb,
610 __in PCDB Cdb
611 );
612
613 UCHAR DeviceRequestComplete (
614 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
615 __in PSCSI_REQUEST_BLOCK Srb,
616 __in PCDB Cdb
617 );
618
619 UCHAR DeviceReportLuns (
620 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
621 __in PSCSI_REQUEST_BLOCK Srb,
622 __in PCDB Cdb
623 );
624
625 __inline
626 BOOLEAN
627 AddQueue (
628 __inout PAHCI_QUEUE Queue,
629 __in PVOID Srb
630 );
631
632 __inline
633 PVOID
634 RemoveQueue (
635 __inout PAHCI_QUEUE Queue
636 );
637
638 __inline
639 PAHCI_SRB_EXTENSION
640 GetSrbExtension(
641 __in PSCSI_REQUEST_BLOCK Srb
642 );
643
644 __inline
645 ULONG64
646 AhciGetLba (
647 __in PCDB Cdb,
648 __in ULONG CdbLength
649 );
650
651 //////////////////////////////////////////////////////////////
652 // Assertions //
653 //////////////////////////////////////////////////////////////
654
655 // I assert every silly mistake I can do while coding
656 // because god never help me debugging the code
657 // but these asserts do :')
658
659 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, CAP) == 0x00);
660 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, GHC) == 0x04);
661 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, IS) == 0x08);
662 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, PI) == 0x0C);
663 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, VS) == 0x10);
664 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, CCC_CTL) == 0x14);
665 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, CCC_PTS) == 0x18);
666 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, EM_LOC) == 0x1C);
667 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, EM_CTL) == 0x20);
668 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, CAP2) == 0x24);
669 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, BOHC) == 0x28);
670 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, Reserved) == 0x2C);
671 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, VendorSpecific) == 0xA0);
672 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS, PortList) == 0x100);
673
674 C_ASSERT(FIELD_OFFSET(AHCI_PORT, CLB) == 0x00);
675 C_ASSERT(FIELD_OFFSET(AHCI_PORT, CLBU) == 0x04);
676 C_ASSERT(FIELD_OFFSET(AHCI_PORT, FB) == 0x08);
677 C_ASSERT(FIELD_OFFSET(AHCI_PORT, FBU) == 0x0C);
678 C_ASSERT(FIELD_OFFSET(AHCI_PORT, IS) == 0x10);
679 C_ASSERT(FIELD_OFFSET(AHCI_PORT, IE) == 0x14);
680 C_ASSERT(FIELD_OFFSET(AHCI_PORT, CMD) == 0x18);
681 C_ASSERT(FIELD_OFFSET(AHCI_PORT, RSV0) == 0x1C);
682 C_ASSERT(FIELD_OFFSET(AHCI_PORT, TFD) == 0x20);
683 C_ASSERT(FIELD_OFFSET(AHCI_PORT, SIG) == 0x24);
684 C_ASSERT(FIELD_OFFSET(AHCI_PORT, SSTS) == 0x28);
685 C_ASSERT(FIELD_OFFSET(AHCI_PORT, SCTL) == 0x2C);
686 C_ASSERT(FIELD_OFFSET(AHCI_PORT, SERR) == 0x30);
687 C_ASSERT(FIELD_OFFSET(AHCI_PORT, SACT) == 0x34);
688 C_ASSERT(FIELD_OFFSET(AHCI_PORT, CI) == 0x38);
689 C_ASSERT(FIELD_OFFSET(AHCI_PORT, SNTF) == 0x3C);
690 C_ASSERT(FIELD_OFFSET(AHCI_PORT, FBS) == 0x40);
691 C_ASSERT(FIELD_OFFSET(AHCI_PORT, RSV1) == 0x44);
692 C_ASSERT(FIELD_OFFSET(AHCI_PORT, Vendor) == 0x70);
693
694 C_ASSERT((sizeof(AHCI_COMMAND_TABLE) % 128) == 0);
695
696 C_ASSERT(sizeof(AHCI_GHC) == sizeof(ULONG));
697 C_ASSERT(sizeof(AHCI_PORT_CMD) == sizeof(ULONG));
698 C_ASSERT(sizeof(AHCI_TASK_FILE_DATA) == sizeof(ULONG));
699 C_ASSERT(sizeof(AHCI_INTERRUPT_ENABLE) == sizeof(ULONG));
700 C_ASSERT(sizeof(AHCI_SERIAL_ATA_STATUS) == sizeof(ULONG));
701 C_ASSERT(sizeof(AHCI_SERIAL_ATA_CONTROL) == sizeof(ULONG));
702 C_ASSERT(sizeof(AHCI_COMMAND_HEADER_DESCRIPTION) == sizeof(ULONG));
703
704 C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE, CFIS) == 0x00);
705 C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE, ACMD) == 0x40);
706 C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE, RSV0) == 0x50);
707 C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE, PRDT) == 0x80);
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