drivers/usb/nt4compat/usbdriver/ohci.h

   1 /*
   2  * Copyright (c) 2007 by Aleksey Bragin
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #ifndef __OHCI_H__
  20 #define __OHCI_H__
  21
  22 #define OHCI_DEVICE_NAME "\\Device\\OHCI"
  23 #define OHCI_DOS_DEVICE_NAME "\\DosDevices\\OHCI"
  24
  25 /* Host Controller Operational Registers */
  26
  27 #define OHCI_REVISION       0x0
  28 #define OHCI_CONTROL        0x4
  29 #define OHCI_CMDSTATUS      0x8
  30 #define OHCI_INTRSTATUS     0xc
  31 #define OHCI_INTRENABLE     0x10
  32 #define OHCI_INTRDISABLE    0x14
  33
  34 /* OHCI CONTROL AND STATUS REGISTER MASKS */
  35
  36 /*
  37  * HcControl (control) register masks
  38  */
  39 #define OHCI_CTRL_CBSR  (3 << 0)        /* control/bulk service ratio */
  40 #define OHCI_CTRL_PLE   (1 << 2)        /* periodic list enable */
  41 #define OHCI_CTRL_IE    (1 << 3)        /* isochronous enable */
  42 #define OHCI_CTRL_CLE   (1 << 4)        /* control list enable */
  43 #define OHCI_CTRL_BLE   (1 << 5)        /* bulk list enable */
  44 #define OHCI_CTRL_HCFS  (3 << 6)        /* host controller functional state */
  45 #define OHCI_CTRL_IR    (1 << 8)        /* interrupt routing */
  46 #define OHCI_CTRL_RWC   (1 << 9)        /* remote wakeup connected */
  47 #define OHCI_CTRL_RWE   (1 << 10)       /* remote wakeup enable */
  48
  49 /* pre-shifted values for HCFS */
  50 #       define OHCI_USB_RESET   (0 << 6)
  51 #       define OHCI_USB_RESUME  (1 << 6)
  52 #       define OHCI_USB_OPER    (2 << 6)
  53 #       define OHCI_USB_SUSPEND (3 << 6)
  54
  55 /*
  56  * HcCommandStatus (cmdstatus) register masks
  57  */
  58 #define OHCI_HCR        (1 << 0)        /* host controller reset */
  59 #define OHCI_CLF        (1 << 1)        /* control list filled */
  60 #define OHCI_BLF        (1 << 2)        /* bulk list filled */
  61 #define OHCI_OCR        (1 << 3)        /* ownership change request */
  62 #define OHCI_SOC        (3 << 16)       /* scheduling overrun count */
  63
  64 /*
  65  * masks used with interrupt registers:
  66  * HcInterruptStatus (intrstatus)
  67  * HcInterruptEnable (intrenable)
  68  * HcInterruptDisable (intrdisable)
  69  */
  70 #define OHCI_INTR_SO    (1 << 0)        /* scheduling overrun */
  71 #define OHCI_INTR_WDH   (1 << 1)        /* writeback of done_head */
  72 #define OHCI_INTR_SF    (1 << 2)        /* start frame */
  73 #define OHCI_INTR_RD    (1 << 3)        /* resume detect */
  74 #define OHCI_INTR_UE    (1 << 4)        /* unrecoverable error */
  75 #define OHCI_INTR_FNO   (1 << 5)        /* frame number overflow */
  76 #define OHCI_INTR_RHSC  (1 << 6)        /* root hub status change */
  77 #define OHCI_INTR_OC    (1 << 30)       /* ownership change */
  78 #define OHCI_INTR_MIE   (1 << 31)       /* master interrupt enable */
  79
  80
  81 /* OHCI ROOT HUB REGISTER MASKS */
  82
  83 /* roothub.portstatus [i] bits */
  84 #define RH_PS_CCS            0x00000001         /* current connect status */
  85 #define RH_PS_PES            0x00000002         /* port enable status*/
  86 #define RH_PS_PSS            0x00000004         /* port suspend status */
  87 #define RH_PS_POCI           0x00000008         /* port over current indicator */
  88 #define RH_PS_PRS            0x00000010         /* port reset status */
  89 #define RH_PS_PPS            0x00000100         /* port power status */
  90 #define RH_PS_LSDA           0x00000200         /* low speed device attached */
  91 #define RH_PS_CSC            0x00010000         /* connect status change */
  92 #define RH_PS_PESC           0x00020000         /* port enable status change */
  93 #define RH_PS_PSSC           0x00040000         /* port suspend status change */
  94 #define RH_PS_OCIC           0x00080000         /* over current indicator change */
  95 #define RH_PS_PRSC           0x00100000         /* port reset status change */
  96
  97 /* roothub.status bits */
  98 #define RH_HS_LPS            0x00000001         /* local power status */
  99 #define RH_HS_OCI            0x00000002         /* over current indicator */
 100 #define RH_HS_DRWE           0x00008000         /* device remote wakeup enable */
 101 #define RH_HS_LPSC           0x00010000         /* local power status change */
 102 #define RH_HS_OCIC           0x00020000         /* over current indicator change */
 103 #define RH_HS_CRWE           0x80000000         /* clear remote wakeup enable */
 104
 105 /* roothub.b masks */
 106 #define RH_B_DR         0x0000ffff              /* device removable flags */
 107 #define RH_B_PPCM       0xffff0000              /* port power control mask */
 108
 109 /* roothub.a masks */
 110 #define RH_A_NDP        (0xff << 0)             /* number of downstream ports */
 111 #define RH_A_PSM        (1 << 8)                /* power switching mode */
 112 #define RH_A_NPS        (1 << 9)                /* no power switching */
 113 #define RH_A_DT         (1 << 10)               /* device type (mbz) */
 114 #define RH_A_OCPM       (1 << 11)               /* over current protection mode */
 115 #define RH_A_NOCP       (1 << 12)               /* no over current protection */
 116 #define RH_A_POTPGT     (0xff << 24)            /* power on to power good time */
 117
 118 /*
 119  * OHCI Endpoint Descriptor (ED) ... holds TD queue
 120  * See OHCI spec, section 4.2
 121  *
 122  * This is a "Queue Head" for those transfers, which is why
 123  * both EHCI and UHCI call similar structures a "QH".
 124  */
 125 typedef struct _OHCI_ED {
 126         /* first fields are hardware-specified */
 127         ULONG                   hwINFO;         /* endpoint config bitmap */
 128         /* info bits defined by hcd */
 129 #define ED_DEQUEUE      (1 << 27)
 130         /* info bits defined by the hardware */
 131 #define ED_ISO          (1 << 15)
 132 #define ED_SKIP         (1 << 14)
 133 #define ED_LOWSPEED     (1 << 13)
 134 #define ED_OUT          (0x01 << 11)
 135 #define ED_IN           (0x02 << 11)
 136         ULONG                   hwTailP;        /* tail of TD list */
 137         ULONG                   hwHeadP;        /* head of TD list (hc r/w) */
 138 #define ED_C            (0x02)                  /* toggle carry */
 139 #define ED_H            (0x01)                  /* halted */
 140         ULONG                   hwNextED;       /* next ED in list */
 141
 142         /* rest are purely for the driver's use */
 143 #if 0
 144         dma_addr_t              dma;            /* addr of ED */
 145         struct _OHCI_TD         *dummy;         /* next TD to activate */
 146
 147         /* host's view of schedule */
 148         struct _OHCI_ED         *ed_next;       /* on schedule or rm_list */
 149         struct _OHCI_ED         *ed_prev;       /* for non-interrupt EDs */
 150         struct list_head        td_list;        /* "shadow list" of our TDs */
 151
 152         /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
 153          * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
 154          */
 155         UCHAR                   state;          /* ED_{IDLE,UNLINK,OPER} */
 156 #define ED_IDLE         0x00            /* NOT linked to HC */
 157 #define ED_UNLINK       0x01            /* being unlinked from hc */
 158 #define ED_OPER         0x02            /* IS linked to hc */
 159
 160         UCHAR                   type;           /* PIPE_{BULK,...} */
 161
 162         /* periodic scheduling params (for intr and iso) */
 163         UCHAR                   branch;
 164         USHORT                  interval;
 165         USHORT                  load;
 166         USHORT                  last_iso;       /* iso only */
 167
 168         /* HC may see EDs on rm_list until next frame (frame_no == tick) */
 169         USHORT                  tick;
 170 #endif
 171 } OHCI_ED, *POHCI_ED;
 172
 173 #define ED_MASK ((u32)~0x0f)            /* strip hw status in low addr bits */
 174
 175
 176 /*
 177  * OHCI Transfer Descriptor (TD) ... one per transfer segment
 178  * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
 179  * and 4.3.2 (iso)
 180  */
 181 typedef struct _OHCI_TD {
 182         /* first fields are hardware-specified */
 183         ULONG           hwINFO;         /* transfer info bitmask */
 184
 185         /* hwINFO bits for both general and iso tds: */
 186 #define TD_CC       0xf0000000                  /* condition code */
 187 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
 188 //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
 189 #define TD_DI       0x00E00000                  /* frames before interrupt */
 190 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
 191         /* these two bits are available for definition/use by HCDs in both
 192          * general and iso tds ... others are available for only one type
 193          */
 194 #define TD_DONE     0x00020000                  /* retired to donelist */
 195 #define TD_ISO      0x00010000                  /* copy of ED_ISO */
 196
 197         /* hwINFO bits for general tds: */
 198 #define TD_EC       0x0C000000                  /* error count */
 199 #define TD_T        0x03000000                  /* data toggle state */
 200 #define TD_T_DATA0  0x02000000                          /* DATA0 */
 201 #define TD_T_DATA1  0x03000000                          /* DATA1 */
 202 #define TD_T_TOGGLE 0x00000000                          /* uses ED_C */
 203 #define TD_DP       0x00180000                  /* direction/pid */
 204 #define TD_DP_SETUP 0x00000000                  /* SETUP pid */
 205 #define TD_DP_IN    0x00100000                          /* IN pid */
 206 #define TD_DP_OUT   0x00080000                          /* OUT pid */
 207                                                         /* 0x00180000 rsvd */
 208 #define TD_R        0x00040000                  /* round: short packets OK? */
 209
 210         /* (no hwINFO #defines yet for iso tds) */
 211
 212         ULONG           hwCBP;          /* Current Buffer Pointer (or 0) */
 213         ULONG           hwNextTD;       /* Next TD Pointer */
 214         ULONG           hwBE;           /* Memory Buffer End Pointer */
 215
 216         /* PSW is only for ISO.  Only 1 PSW entry is used, but on
 217          * big-endian PPC hardware that's the second entry.
 218          */
 219 #define MAXPSW  2
 220         USHORT          hwPSW [MAXPSW];
 221
 222         /* rest are purely for the driver's use */
 223 #if 0
 224         UCHAR           index;
 225         struct ed       *ed;
 226         struct td       *td_hash;       /* dma-->td hashtable */
 227         struct td       *next_dl_td;
 228         struct urb      *urb;
 229
 230         dma_addr_t      td_dma;         /* addr of this TD */
 231         dma_addr_t      data_dma;       /* addr of data it points to */
 232
 233         struct list_head td_list;       /* "shadow list", TDs on same ED */
 234 #endif
 235 } OHCI_TD, *POHCI_TD;
 236
 237 /*
 238  * The HCCA (Host Controller Communications Area) is a 256 byte
 239  * structure defined section 4.4.1 of the OHCI spec. The HC is
 240  * told the base address of it.  It must be 256-byte aligned.
 241  */
 242 typedef struct _OHCI_HCCA
 243 {
 244 #define NUM_INTS 32
 245         ULONG   int_table [NUM_INTS];   /* periodic schedule */
 246
 247         /*
 248          * OHCI defines u16 frame_no, followed by u16 zero pad.
 249          * Since some processors can't do 16 bit bus accesses,
 250          * portable access must be a 32 bits wide.
 251          */
 252         ULONG   frame_no;               /* current frame number */
 253         ULONG   done_head;              /* info returned for an interrupt */
 254         UCHAR   reserved_for_hc [116];
 255         UCHAR   what [4];               /* spec only identifies 252 bytes :) */
 256 } OHCI_HCCA, *POHCI_HCCA;
 257
 258 /*
 259  * This is the structure of the OHCI controller's memory mapped I/O region.
 260  * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
 261  * Layout is in section 7 (and appendix B) of the spec.
 262  */
 263 typedef struct _OHCI_REGS
 264 {
 265         /* control and status registers (section 7.1) */
 266         ULONG   revision;
 267         ULONG   control;
 268         ULONG   cmdstatus;
 269         ULONG   intrstatus;
 270         ULONG   intrenable;
 271         ULONG   intrdisable;
 272
 273         /* memory pointers (section 7.2) */
 274         ULONG   hcca;
 275         ULONG   ed_periodcurrent;
 276         ULONG   ed_controlhead;
 277         ULONG   ed_controlcurrent;
 278         ULONG   ed_bulkhead;
 279         ULONG   ed_bulkcurrent;
 280         ULONG   donehead;
 281
 282         /* frame counters (section 7.3) */
 283         ULONG   fminterval;
 284         ULONG   fmremaining;
 285         ULONG   fmnumber;
 286         ULONG   periodicstart;
 287         ULONG   lsthresh;
 288
 289         /* Root hub ports (section 7.4) */
 290         struct  ohci_roothub_regs {
 291                 ULONG   a;
 292                 ULONG   b;
 293                 ULONG   status;
 294 #define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports (RH_A_NDP) */
 295                 ULONG   portstatus [MAX_ROOT_PORTS];
 296         } roothub;
 297
 298         /* and optional "legacy support" registers (appendix B) at 0x0100 */
 299 } OHCI_REGS, *POHCI_REGS;
 300
 301 typedef struct _OHCI_DEV
 302 {
 303     HCD     hcd_interf;
 304
 305     PHYSICAL_ADDRESS    ohci_reg_base;                                          // io space
 306     BOOLEAN                             port_mapped;
 307     PBYTE                               port_base;                                                      // note: added by ehci_caps.length, operational regs base addr, not the actural base
 308     struct _OHCI_REGS   *regs;
 309     struct _OHCI_HCCA   *hcca;
 310     PVOID               td_cache;
 311     PVOID               ed_cache;
 312
 313     PHYSICAL_ADDRESS    hcca_logic_addr;
 314     PHYSICAL_ADDRESS    td_logic_addr;
 315     PHYSICAL_ADDRESS    ed_logic_addr;
 316
 317     USHORT              num_ports;
 318
 319     LIST_HEAD           urb_list;                           // active urb-list
 320
 321         //
 322     //for iso and int bandwidth claim, bandwidth schedule
 323         //
 324         KSPIN_LOCK                      pending_endp_list_lock;                         //lock to access the following two
 325         LIST_HEAD                       pending_endp_list;
 326         UHCI_PENDING_ENDP_POOL  pending_endp_pool;
 327
 328     KTIMER                              reset_timer;                                            //used to reset the host controller
 329     struct _OHCI_DEVICE_EXTENSION    *pdev_ext;
 330     PUSB_DEV            root_hub;                                                       //root hub
 331 } OHCI_DEV, *POHCI_DEV;
 332
 333 typedef struct _OHCI_DEVICE_EXTENSION
 334 {
 335     DEVEXT_HEADER               dev_ext_hdr;
 336     PDEVICE_OBJECT      pdev_obj;
 337     PDRIVER_OBJECT      pdrvr_obj;
 338     POHCI_DEV                   ohci;
 339
 340     //device resources
 341     PADAPTER_OBJECT     padapter;
 342     ULONG                               map_regs;
 343     PCM_RESOURCE_LIST   res_list;
 344     ULONG               pci_addr;       // bus number | slot number | funciton number
 345     UHCI_INTERRUPT      res_interrupt;
 346     union
 347     {
 348         UHCI_PORT                       res_port;
 349         EHCI_MEMORY             res_memory;
 350     };
 351
 352     PKINTERRUPT                 ohci_int;
 353     KDPC                                ohci_dpc;
 354 } OHCI_DEVICE_EXTENSION, *POHCI_DEVICE_EXTENSION;
 355
 356 #define ohci_from_hcd( hCD ) ( struct_ptr( ( hCD ), OHCI_DEV, hcd_interf ) )
 357
 358 #endif /* __OHCI_H__ */