1 #ifndef __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H
2 #define __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H
4 #define X86_EFLAGS_TF 0x00000100 /* Trap flag */
5 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Enable flag */
6 #define X86_EFLAGS_IOPL 0x00003000 /* I/O Privilege Level bits */
7 #define X86_EFLAGS_NT 0x00004000 /* Nested Task flag */
8 #define X86_EFLAGS_RF 0x00010000 /* Resume flag */
9 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
10 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
12 #define X86_CR0_PE 0x00000001 /* enable Protected Mode */
13 #define X86_CR0_NE 0x00000020 /* enable native FPU error reporting */
14 #define X86_CR0_TS 0x00000008 /* enable exception on FPU instruction for task switch */
15 #define X86_CR0_EM 0x00000004 /* enable FPU emulation (disable FPU) */
16 #define X86_CR0_MP 0x00000002 /* enable FPU monitoring */
17 #define X86_CR0_WP 0x00010000 /* enable Write Protect (copy on write) */
18 #define X86_CR0_PG 0x80000000 /* enable Paging */
20 #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
21 #define X86_CR4_PGE 0x00000080 /* enable global pages */
22 #define X86_CR4_OSFXSR 0x00000200 /* enable FXSAVE/FXRSTOR instructions */
23 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable #XF exception */
25 #define X86_FEATURE_VME 0x00000002 /* Virtual 8086 Extensions are present */
26 #define X86_FEATURE_TSC 0x00000010 /* time stamp counters are present */
27 #define X86_FEATURE_PAE 0x00000040 /* physical address extension is present */
28 #define X86_FEATURE_CX8 0x00000100 /* CMPXCHG8B instruction present */
29 #define X86_FEATURE_SYSCALL 0x00000800 /* SYSCALL/SYSRET support present */
30 #define X86_FEATURE_PGE 0x00002000 /* Page Global Enable */
31 #define X86_FEATURE_MMX 0x00800000 /* MMX extension present */
32 #define X86_FEATURE_FXSR 0x01000000 /* FXSAVE/FXRSTOR instructions present */
33 #define X86_FEATURE_SSE 0x02000000 /* SSE extension present */
34 #define X86_FEATURE_SSE2 0x04000000 /* SSE2 extension present */
35 #define X86_FEATURE_HT 0x10000000 /* Hyper-Threading present */
37 #define X86_EXT_FEATURE_SSE3 0x00000001 /* SSE3 extension present */
38 #define X86_EXT_FEATURE_3DNOW 0x40000000 /* 3DNOW! extension present */
40 #define FRAME_EDITED 0xFFF8
42 #define X86_MSR_GSBASE 0xC0000101
43 #define X86_MSR_KERNEL_GSBASE 0xC0000102
44 #define X86_MSR_EFER 0xC0000080
45 #define X86_MSR_STAR 0xC0000081
46 #define X86_MSR_LSTAR 0xC0000082
47 #define X86_MSR_CSTAR 0xC0000083
48 #define X86_MSR_SFMASK 0xC0000084
54 #define EFER_SVME 0x100
55 #define EFER_FFXSR 0x400
63 typedef struct _KIDT_INIT
69 } KIDT_INIT
, *PKIDT_INIT
;
71 extern ULONG Ke386CacheAlignment
;
72 extern ULONG KeI386NpxPresent
;
73 extern ULONG KeI386XMMIPresent
;
74 extern ULONG KeI386FxsrPresent
;
75 extern ULONG KeI386CpuType
;
76 extern ULONG KeI386CpuStep
;
79 // INT3 is 1 byte long
81 #define KD_BREAKPOINT_TYPE UCHAR
82 #define KD_BREAKPOINT_SIZE sizeof(UCHAR)
83 #define KD_BREAKPOINT_VALUE 0xCC
86 // Macros for getting and setting special purpose registers in portable code
88 #define KeGetContextPc(Context) \
91 #define KeSetContextPc(Context, ProgramCounter) \
92 ((Context)->Rip = (ProgramCounter))
94 #define KeGetTrapFramePc(TrapFrame) \
97 #define KiGetLinkedTrapFrame(x) \
98 (PKTRAP_FRAME)((x)->Rdx)
100 #define KeGetContextReturnRegister(Context) \
103 #define KeSetContextReturnRegister(Context, ReturnValue) \
104 ((Context)->Rax = (ReturnValue))
107 // Macro to get trap and exception frame from a thread stack
109 #define KeGetTrapFrame(Thread) \
110 (PKTRAP_FRAME)((ULONG_PTR)((Thread)->InitialStack) - \
114 // Macro to get context switches from the PRCB
115 // All architectures but x86 have it in the PRCB's KeContextSwitches
117 #define KeGetContextSwitches(Prcb) \
118 (Prcb->KeContextSwitches)
121 // Macro to get the second level cache size field name which differs between
122 // CISC and RISC architectures, as the former has unified I/D cache
124 #define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelCacheSize
126 #define KeGetExceptionFrame(Thread) \
127 (PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \
128 sizeof(KEXCEPTION_FRAME))
131 // Returns the Interrupt State from a Trap Frame.
132 // ON = TRUE, OFF = FALSE
134 #define KeGetTrapFrameInterruptState(TrapFrame) \
135 BooleanFlagOn((TrapFrame)->EFlags, EFLAGS_INTERRUPT_MASK)
137 /* Diable interrupts and return whether they were enabled before */
140 KeDisableInterrupts(VOID
)
144 /* Get EFLAGS and check if the interrupt bit is set */
145 Flags
= __readeflags();
147 /* Disable interrupts */
149 return (Flags
& EFLAGS_INTERRUPT_MASK
) ? TRUE
: FALSE
;
152 /* Restore previous interrupt state */
155 KeRestoreInterrupts(BOOLEAN WereEnabled
)
157 if (WereEnabled
) _enable();
161 // Invalidates the TLB entry for a specified address
165 KeInvalidateTlbEntry(IN PVOID Address
)
167 /* Invalidate the TLB entry for this address */
173 KeFlushProcessTb(VOID
)
175 /* Flush the TLB by resetting CR3 */
176 __writecr3(__readcr3());
181 KiRundownThread(IN PKTHREAD Thread
)
184 DbgPrint("KiRundownThread is unimplemented\n");
190 /* Registers an interrupt handler with an IDT vector */
193 KeRegisterInterruptHandler(IN ULONG Vector
,
199 /* Get the entry from the HAL */
200 Entry
= HalVectorToIDTEntry(Vector
);
202 /* Now set the data */
203 Idt
= &KeGetPcr()->IdtBase
[Entry
];
204 Idt
->OffsetLow
= (ULONG_PTR
)Handler
& 0xffff;
205 Idt
->OffsetMiddle
= ((ULONG_PTR
)Handler
>> 16) & 0xffff;
206 Idt
->OffsetHigh
= (ULONG_PTR
)Handler
>> 32;
207 Idt
->Selector
= KGDT64_R0_CODE
;
216 /* Returns the registered interrupt handler for a given IDT vector */
219 KeQueryInterruptHandler(IN ULONG Vector
)
224 /* Get the entry from the HAL */
225 Entry
= HalVectorToIDTEntry(Vector
);
227 /* Get the IDT entry */
228 Idt
= &KeGetPcr()->IdtBase
[Entry
];
230 /* Return the address */
231 return (PVOID
)((ULONG64
)Idt
->OffsetHigh
<< 32 |
232 (ULONG64
)Idt
->OffsetMiddle
<< 16 |
233 (ULONG64
)Idt
->OffsetLow
);
238 KiEndInterrupt(IN KIRQL Irql
,
239 IN PKTRAP_FRAME TrapFrame
)
241 DbgPrint("KiEndInterrupt is unimplemented\n");
244 #define Ki386PerfEnd(x)
250 KiInitializeTss(IN PKTSS Tss
, IN UINT64 Stack
);
252 VOID
KiDivideErrorFault(VOID
);
253 VOID
KiDebugTrapOrFault(VOID
);
254 VOID
KiNmiInterrupt(VOID
);
255 VOID
KiBreakpointTrap(VOID
);
256 VOID
KiOverflowTrap(VOID
);
257 VOID
KiBoundFault(VOID
);
258 VOID
KiInvalidOpcodeFault(VOID
);
259 VOID
KiNpxNotAvailableFault(VOID
);
260 VOID
KiDoubleFaultAbort(VOID
);
261 VOID
KiNpxSegmentOverrunAbort(VOID
);
262 VOID
KiInvalidTssFault(VOID
);
263 VOID
KiSegmentNotPresentFault(VOID
);
264 VOID
KiStackFault(VOID
);
265 VOID
KiGeneralProtectionFault(VOID
);
266 VOID
KiPageFault(VOID
);
267 VOID
KiFloatingErrorFault(VOID
);
268 VOID
KiAlignmentFault(VOID
);
269 VOID
KiMcheckAbort(VOID
);
270 VOID
KiXmmException(VOID
);
271 VOID
KiApcInterrupt(VOID
);
272 VOID
KiRaiseAssertion(VOID
);
273 VOID
KiDebugServiceTrap(VOID
);
274 VOID
KiDpcInterrupt(VOID
);
275 VOID
KiIpiInterrupt(VOID
);
278 KiGdtPrepareForApplicationProcessorInit(ULONG Id
);
280 Ki386InitializeLdt(VOID
);
282 Ki386SetProcessorFeatures(VOID
);
286 KiGetCacheInformation(VOID
);
296 KiIsNpxErrataPresent(
302 KiSetProcessorType(VOID
);
306 KiGetFeatureBits(VOID
);
310 KiInitializeCpuFeatures(VOID
);
312 ULONG
KeAllocateGdtSelector(ULONG Desc
[2]);
313 VOID
KeFreeGdtSelector(ULONG Entry
);
315 NtEarlyInitVdm(VOID
);
317 KeApplicationProcessorInitDispatcher(VOID
);
319 KeCreateApplicationProcessorIdleThread(ULONG Id
);
323 Ke386InitThreadWithContext(PKTHREAD Thread
,
324 PKSYSTEM_ROUTINE SystemRoutine
,
325 PKSTART_ROUTINE StartRoutine
,
328 #define KeArchInitThreadWithContext(Thread,SystemRoutine,StartRoutine,StartContext,Context) \
329 Ke386InitThreadWithContext(Thread,SystemRoutine,StartRoutine,StartContext,Context)
331 #ifdef _NTOSKRNL_ /* FIXME: Move flags above to NDK instead of here */
334 KiThreadStartup(PKSYSTEM_ROUTINE SystemRoutine
,
335 PKSTART_ROUTINE StartRoutine
,
338 KTRAP_FRAME TrapFrame
);
344 extern NTKERNELAPI
volatile KSYSTEM_TIME KeTickCount
;
346 #endif /* __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H */