2 * Lowlevel memory managment definitions
8 PULONG
MmGetPageDirectory(VOID
);
11 #define _MI_PAGING_LEVELS 3
13 #define _MI_PAGING_LEVELS 2
16 #define PAGE_MASK(x) ((x)&(~0xfff))
17 #define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
19 /* Base addresses of PTE and PDE */
20 #define PAGETABLE_MAP (0xc0000000)
21 #define PAGEDIRECTORY_MAP (0xc0000000 + (PAGETABLE_MAP / (1024)))
23 /* FIXME: These are different for PAE */
24 #define PTE_BASE 0xC0000000
25 #define PDE_BASE 0xC0300000
26 #define PDE_TOP 0xC0300FFF
27 #define PTE_TOP 0xC03FFFFF
28 #define HYPER_SPACE 0xC0400000
30 /* Converting address to a corresponding PDE or PTE entry */
31 #define MiAddressToPde(x) \
32 ((PMMPTE)(((((ULONG)(x)) >> 22) << 2) + PAGEDIRECTORY_MAP))
33 #define MiAddressToPte(x) \
34 ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PAGETABLE_MAP))
35 #define MiAddressToPteOffset(x) \
36 ((((ULONG)(x)) << 10) >> 22)
39 // Convert a PTE into a corresponding address
41 #define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
43 #define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
44 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
45 #define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
47 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
49 /* Easy accessing PFN in PTE */
50 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
52 #define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
53 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
54 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
55 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
56 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
57 #if !defined(CONFIG_SMP)
58 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
60 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
62 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
63 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
64 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
65 #if !defined(CONFIG_SMP)
66 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
68 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
71 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
74 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
75 ((((x)) % (4*1024*1024)) / (4*1024))
77 #define NR_SECTION_PAGE_TABLES 1024
78 #define NR_SECTION_PAGE_ENTRIES 1024
80 #define TEB_BASE 0x7FFDE000
82 #define MI_HYPERSPACE_PTES (256 - 1)
83 #define MI_ZERO_PTES (32)
84 #define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
85 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
86 MI_HYPERSPACE_PTES * PAGE_SIZE)
87 #define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
90 /* On x86, these two are the same */
95 * FIXME - different architectures have different cache line sizes...
97 #define MM_CACHE_LINE_SIZE 32