reactos/drivers/bus/acpi/include/actbl2.h

   1 /******************************************************************************
   2  *
   3  * Name: actbl2.h - ACPI Specification Revision 2.0 Tables
   4  *       $Revision: 1.1 $
   5  *
   6  *****************************************************************************/
   7
   8 /*
   9  *  Copyright (C) 2000, 2001 R. Byron Moore
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  */
  25
  26 #ifndef __ACTBL2_H__
  27 #define __ACTBL2_H__
  28
  29 /**************************************/
  30 /* Prefered Power Management Profiles */
  31 /**************************************/
  32 #define PM_UNSPECIFIED        0
  33 #define PM_DESKTOP            1
  34 #define PM_MOBILE             2
  35 #define PM_WORKSTATION        3
  36 #define PM_ENTERPRISE_SERVER  4
  37 #define PM_SOHO_SERVER        5
  38 #define PM_APPLIANCE_PC       6
  39
  40 /*********************************************/
  41 /* ACPI Boot Arch Flags, See spec Table 5-10 */
  42 /*********************************************/
  43 #define BAF_LEGACY_DEVICES             0x0001
  44 #define BAF_8042_KEYBOARD_CONTROLLER   0x0002
  45
  46 #define FADT2_REVISION_ID     3
  47
  48 #pragma pack(1)
  49
  50 /*************************************/
  51 /* ACPI Specification Rev 2.0 for    */
  52 /* the Root System Description Table */
  53 /*************************************/
  54 typedef struct
  55 {
  56         ACPI_TABLE_HEADER   header;                 /* Table header */
  57         u32                 table_offset_entry [1]; /* Array of pointers to  */
  58                            /* other tables' headers */
  59 } RSDT_DESCRIPTOR_REV2;
  60
  61
  62 /********************************************/
  63 /* ACPI Specification Rev 2.0 for the       */
  64 /* Extended System Description Table (XSDT) */
  65 /********************************************/
  66 typedef struct
  67 {
  68         ACPI_TABLE_HEADER   header;                 /* Table header */
  69         UINT64              table_offset_entry [1]; /* Array of pointers to  */
  70                            /* other tables' headers */
  71 } XSDT_DESCRIPTOR_REV2;
  72
  73 /***************************************/
  74 /* ACPI Specification Rev 2.0 for      */
  75 /* the Firmware ACPI Control Structure */
  76 /***************************************/
  77 typedef struct
  78 {
  79         NATIVE_CHAR         signature[4];           /* signature "FACS" */
  80         u32                 length;                 /* length of structure, in bytes */
  81         u32                 hardware_signature;     /* hardware configuration signature */
  82         u32                 firmware_waking_vector; /* 32bit physical address of the Firmware Waking Vector. */
  83         u32                 global_lock;            /* Global Lock used to synchronize access to shared hardware resources */
  84         u32                 S4_bios_f       : 1;    /* Indicates if S4_bIOS support is present */
  85         u32                 reserved1       : 31;   /* must be 0 */
  86         UINT64              Xfirmware_waking_vector; /* 64bit physical address of the Firmware Waking Vector. */
  87         u8                  version;                /* Version of this table */
  88         u8                  reserved3 [31];         /* reserved - must be zero */
  89
  90 } FACS_DESCRIPTOR_REV2;
  91
  92
  93 /***************************************/
  94 /* ACPI Specification Rev 2.0 for      */
  95 /* the Generic Address Structure (GAS) */
  96 /***************************************/
  97 typedef struct
  98 {
  99         u8                  address_space_id;   /* Address space where struct or register exists. */
 100         u8                  register_bit_width; /* Size in bits of given register */
 101         u8                  register_bit_offset; /* Bit offset within the register */
 102         u8                  reserved;           /* Must be 0 */
 103         UINT64              address;            /* 64-bit address of struct or register */
 104
 105 } ACPI_GAS;
 106
 107
 108 /************************************/
 109 /* ACPI Specification Rev 2.0 for   */
 110 /* the Fixed ACPI Description Table */
 111 /************************************/
 112 typedef struct
 113 {
 114         ACPI_TABLE_HEADER   header;            /* table header */
 115         u32                 V1_firmware_ctrl;  /* 32-bit physical address of FACS */
 116         u32                 V1_dsdt;           /* 32-bit physical address of DSDT */
 117         u8                  reserved1;         /* System Interrupt Model isn't used in ACPI 2.0*/
 118         u8                  prefer_PM_profile; /* Conveys preferred power management profile to OSPM. */
 119         u16                 sci_int;           /* System vector of SCI interrupt */
 120         u32                 smi_cmd;           /* Port address of SMI command port */
 121         u8                  acpi_enable;       /* value to write to smi_cmd to enable ACPI */
 122         u8                  acpi_disable;      /* value to write to smi_cmd to disable ACPI */
 123         u8                  S4_bios_req;       /* Value to write to SMI CMD to enter S4_bIOS state */
 124         u8                  pstate_cnt;        /* processor performance state control*/
 125         u32                 V1_pm1a_evt_blk;   /* Port address of Power Mgt 1a Acpi_event Reg Blk */
 126         u32                 V1_pm1b_evt_blk;   /* Port address of Power Mgt 1b Acpi_event Reg Blk */
 127         u32                 V1_pm1a_cnt_blk;   /* Port address of Power Mgt 1a Control Reg Blk */
 128         u32                 V1_pm1b_cnt_blk;   /* Port address of Power Mgt 1b Control Reg Blk */
 129         u32                 V1_pm2_cnt_blk;    /* Port address of Power Mgt 2 Control Reg Blk */
 130         u32                 V1_pm_tmr_blk;     /* Port address of Power Mgt Timer Ctrl Reg Blk */
 131         u32                 V1_gpe0blk;        /* Port addr of General Purpose Acpi_event 0 Reg Blk */
 132         u32                 V1_gpe1_blk;       /* Port addr of General Purpose Acpi_event 1 Reg Blk */
 133         u8                  pm1_evt_len;       /* Byte Length of ports at pm1_x_evt_blk */
 134         u8                  pm1_cnt_len;       /* Byte Length of ports at pm1_x_cnt_blk */
 135         u8                  pm2_cnt_len;       /* Byte Length of ports at pm2_cnt_blk */
 136         u8                  pm_tm_len;         /* Byte Length of ports at pm_tm_blk */
 137         u8                  gpe0blk_len;       /* Byte Length of ports at gpe0_blk */
 138         u8                  gpe1_blk_len;      /* Byte Length of ports at gpe1_blk */
 139         u8                  gpe1_base;         /* offset in gpe model where gpe1 events start */
 140         u8                  cst_cnt;           /* Support for the _CST object and C States change notification.*/
 141         u16                 plvl2_lat;         /* worst case HW latency to enter/exit C2 state */
 142         u16                 plvl3_lat;         /* worst case HW latency to enter/exit C3 state */
 143         u16                 flush_size;        /* number of flush strides that need to be read */
 144         u16                 flush_stride;      /* Processor's memory cache line width, in bytes */
 145         u8                  duty_offset;       /* Processor_\92s duty cycle index in processor's P_CNT reg*/
 146         u8                  duty_width;        /* Processor_\92s duty cycle value bit width in P_CNT register.*/
 147         u8                  day_alrm;          /* index to day-of-month alarm in RTC CMOS RAM */
 148         u8                  mon_alrm;          /* index to month-of-year alarm in RTC CMOS RAM */
 149         u8                  century;           /* index to century in RTC CMOS RAM */
 150         u16                 iapc_boot_arch;    /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
 151         u8                  reserved2;         /* reserved */
 152         u32                 wb_invd     : 1;   /* wbinvd instruction works properly */
 153         u32                 wb_invd_flush : 1; /* wbinvd flushes but does not invalidate */
 154         u32                 proc_c1     : 1;   /* all processors support C1 state */
 155         u32                 plvl2_up    : 1;   /* C2 state works on MP system */
 156         u32                 pwr_button  : 1;   /* Power button is handled as a generic feature */
 157         u32                 sleep_button : 1;  /* Sleep button is handled as a generic feature, or not present */
 158         u32                 fixed_rTC   : 1;   /* RTC wakeup stat not in fixed register space */
 159         u32                 rtcs4       : 1;   /* RTC wakeup stat not possible from S4 */
 160         u32                 tmr_val_ext : 1;   /* tmr_val is 32 bits */
 161         u32                 dock_cap    : 1;   /* Supports Docking */
 162         u32                 reset_reg_sup : 1; /* Indicates system supports system reset via the FADT RESET_REG*/
 163         u32                 sealed_case : 1;   /* Indicates system has no internal expansion capabilities and case is sealed. */
 164         u32                 headless    : 1;   /* Indicates system does not have local video capabilities or local input devices.*/
 165         u32                 cpu_sw_sleep : 1;  /* Indicates to OSPM that a processor native instruction */
 166                          /* must be executed after writing the SLP_TYPx register. */
 167         u32                 reserved6   : 18;  /* reserved - must be zero */
 168
 169         ACPI_GAS            reset_register;    /* Reset register address in GAS format */
 170         u8                  reset_value;       /* Value to write to the Reset_register port to reset the system. */
 171         u8                  reserved7[3];      /* These three bytes must be zero */
 172         UINT64              Xfirmware_ctrl;     /* 64-bit physical address of FACS */
 173         UINT64              Xdsdt;              /* 64-bit physical address of DSDT */
 174         ACPI_GAS            Xpm1a_evt_blk;      /* Extended Power Mgt 1a Acpi_event Reg Blk address */
 175         ACPI_GAS            Xpm1b_evt_blk;      /* Extended Power Mgt 1b Acpi_event Reg Blk address */
 176         ACPI_GAS            Xpm1a_cnt_blk;      /* Extended Power Mgt 1a Control Reg Blk address */
 177         ACPI_GAS            Xpm1b_cnt_blk;      /* Extended Power Mgt 1b Control Reg Blk address */
 178         ACPI_GAS            Xpm2_cnt_blk;       /* Extended Power Mgt 2 Control Reg Blk address */
 179         ACPI_GAS            Xpm_tmr_blk;        /* Extended Power Mgt Timer Ctrl Reg Blk address */
 180         ACPI_GAS            Xgpe0blk;           /* Extended General Purpose Acpi_event 0 Reg Blk address */
 181         ACPI_GAS            Xgpe1_blk;          /* Extended General Purpose Acpi_event 1 Reg Blk address */
 182
 183 }  FADT_DESCRIPTOR_REV2;
 184
 185
 186 #pragma pack()
 187
 188 #endif /* __ACTBL2_H__ */
 189