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[UNIATA]
[reactos.git] / reactos / drivers / storage / ide / uniata / bsmaster.h
1 /*++
2
3 Copyright (c) 2002-2012 Alexandr A. Telyatnikov (Alter)
4
5 Module Name:
6 bsmaster.h
7
8 Abstract:
9 This file contains DMA/UltraDMA and IDE BusMastering related definitions,
10 internal structures and useful macros
11
12 Author:
13 Alexander A. Telyatnikov (Alter)
14
15 Environment:
16 kernel mode only
17
18 Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31 Revision History:
32
33 Code was created by
34 Alter, Copyright (c) 2002-2008
35
36 Some definitions were taken from FreeBSD 4.3-4.6 ATA driver by
37 Søren Schmidt, Copyright (c) 1998,1999,2000,2001
38
39 --*/
40
41 #ifndef __IDE_BUSMASTER_H__
42 #define __IDE_BUSMASTER_H__
43
44 #include "config.h"
45
46 #include "tools.h"
47
48 //
49 //
50 //
51 #define ATA_IDLE 0x0
52 #define ATA_IMMEDIATE 0x1
53 #define ATA_WAIT_INTR 0x2
54 #define ATA_WAIT_READY 0x3
55 #define ATA_ACTIVE 0x4
56 #define ATA_ACTIVE_ATA 0x5
57 #define ATA_ACTIVE_ATAPI 0x6
58 #define ATA_REINITING 0x7
59 #define ATA_WAIT_BASE_READY 0x8
60 #define ATA_WAIT_IDLE 0x9
61
62
63 #include "bm_devs.h"
64
65 #include "uata_ctl.h"
66
67 #define MAX_RETRIES 6
68 #define RETRY_UDMA2 1
69 #define RETRY_WDMA 2
70 #define RETRY_PIO 3
71
72
73 #define IO_WD1 0x1F0 /* Primary Fixed Disk Controller */
74 #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */
75 #define IP_PC98_BANK 0x432
76
77 #define PCI_ADDRESS_IOMASK 0xfffffff0
78
79 #define ATA_BM_OFFSET1 0x08
80 #define ATA_IOSIZE 0x08
81 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */
82 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
83 #define ATA_ALTIOSIZE 0x01 /* alternate registers size */
84 #define ATA_BMIOSIZE 0x20
85 #define ATA_PC98_BANKIOSIZE 0x01
86 //#define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
87 // Hitachi 1 Tb HDD didn't allow LBA28 with BCount > 1 beyond this LBA
88 #define ATA_MAX_IOLBA28 DEF_U64(0x0fffff80)
89 #define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
90
91 #define ATA_DMA_ENTRIES 256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
92 #define ATA_DMA_EOT 0x80000000
93
94 #define DEV_BSIZE 512
95
96 #define ATAPI_MAGIC_LSB 0x14
97 #define ATAPI_MAGIC_MSB 0xeb
98
99 #define AHCI_MAX_PORT 32
100
101 #define SATA_MAX_PM_UNITS 16
102
103 typedef struct _BUSMASTER_CTX {
104 PBUSMASTER_CONTROLLER_INFORMATION* BMListPtr;
105 ULONG* BMListLen;
106 } BUSMASTER_CTX, *PBUSMASTER_CTX;
107
108 #define PCI_DEV_CLASS_STORAGE 0x01
109
110 #define PCI_DEV_SUBCLASS_IDE 0x01
111 #define PCI_DEV_SUBCLASS_RAID 0x04
112 #define PCI_DEV_SUBCLASS_ATA 0x05
113 #define PCI_DEV_SUBCLASS_SATA 0x06
114
115 #define PCI_DEV_PROGIF_AHCI_1_0 0x01
116
117 /* structure for holding DMA address data */
118 typedef struct BM_DMA_ENTRY {
119 ULONG base;
120 ULONG count;
121 } BM_DMA_ENTRY, *PBM_DMA_ENTRY;
122
123 typedef struct _IDE_BUSMASTER_REGISTERS {
124 UCHAR Command;
125 UCHAR DeviceSpecific0;
126 UCHAR Status;
127 UCHAR DeviceSpecific1;
128 ULONG PRD_Table;
129 } IDE_BUSMASTER_REGISTERS, *PIDE_BUSMASTER_REGISTERS;
130
131 #define BM_STATUS_ACTIVE 0x01
132 #define BM_STATUS_ERR 0x02
133 #define BM_STATUS_INTR 0x04
134 #define BM_STATUS_MASK 0x07
135 #define BM_STATUS_DRIVE_0_DMA 0x20
136 #define BM_STATUS_DRIVE_1_DMA 0x40
137 #define BM_STATUS_SIMPLEX_ONLY 0x80
138
139 #define BM_COMMAND_START_STOP 0x01
140 /*#define BM_COMMAND_WRITE 0x08
141 #define BM_COMMAND_READ 0x00*/
142 #define BM_COMMAND_WRITE 0x00
143 #define BM_COMMAND_READ 0x08
144
145 #define BM_DS0_SII_DMA_ENABLE (1 << 0) /* DMA run switch */
146 #define BM_DS0_SII_IRQ (1 << 3) /* ??? */
147 #define BM_DS0_SII_DMA_SATA_IRQ (1 << 4) /* OR of all SATA IRQs */
148 #define BM_DS0_SII_DMA_ERROR (1 << 17) /* PCI bus error */
149 #define BM_DS0_SII_DMA_COMPLETE (1 << 18) /* cmd complete / IRQ pending */
150
151
152 #define IDX_BM_IO (IDX_IO2_o+IDX_IO2_o_SZ)
153 //#define IDX_BM_IO_SZ sizeof(IDE_BUSMASTER_REGISTERS)
154 #define IDX_BM_IO_SZ 5
155
156 #define IDX_BM_Command (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)
157 #define IDX_BM_DeviceSpecific0 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)
158 #define IDX_BM_Status (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)
159 #define IDX_BM_DeviceSpecific1 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)
160 #define IDX_BM_PRD_Table (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)
161
162 typedef struct _IDE_AHCI_REGISTERS {
163 // HBA Capabilities
164 struct {
165 ULONG NOP:5; // number of ports
166 ULONG SXS:1; // Supports External SATA
167 ULONG EMS:1; // Enclosure Management Supported
168 ULONG CCCS:1; // Command Completion Coalescing Supported
169 ULONG NCS:5; // number of command slots
170 ULONG PSC:1; // partial state capable
171 ULONG SSC:1; // slumber state capable
172 ULONG PMD:1; // PIO multiple DRQ block
173 ULONG FBSS:1; // FIS-based Switching Supported
174
175 ULONG SPM:1; // port multiplier
176 ULONG SAM:1; // AHCI mode only
177 ULONG SNZO:1; // non-zero DMA offset
178 ULONG ISS:4; // interface speed
179 ULONG SCLO:1; // command list override
180 ULONG SAL:1; // activity LED
181 ULONG SALP:1; // aggressive link power management
182 ULONG SSS:1; // staggered spin-up
183 ULONG SIS:1; // interlock switch
184 ULONG SSNTF:1; // Supports SNotification Register
185 ULONG SNCQ:1; // native command queue
186 ULONG S64A:1; // 64bit addr
187 } CAP;
188
189 #define AHCI_CAP_NOP_MASK 0x0000001f
190 #define AHCI_CAP_CCC 0x00000080
191 #define AHCI_CAP_NCS_MASK 0x00001f00
192 #define AHCI_CAP_PMD 0x00008000
193 #define AHCI_CAP_SPM 0x00020000
194 #define AHCI_CAP_SAM 0x00040000
195 #define AHCI_CAP_ISS_MASK 0x00f00000
196 #define AHCI_CAP_SCLO 0x01000000
197 #define AHCI_CAP_SNTF 0x20000000
198 #define AHCI_CAP_NCQ 0x40000000
199 #define AHCI_CAP_S64A 0x80000000
200
201 // Global HBA Control
202 struct {
203 ULONG HR:1; // HBA Reset
204 ULONG IE:1; // interrupt enable
205 ULONG Reserved2_30:1;
206 ULONG AE:1; // AHCI enable
207 } GHC;
208
209 #define AHCI_GHC 0x04
210 #define AHCI_GHC_HR 0x00000001
211 #define AHCI_GHC_IE 0x00000002
212 #define AHCI_GHC_AE 0x80000000
213
214 // Interrupt status (bit mask)
215 ULONG IS; // 0x08
216 // Ports implemented (bit mask)
217 ULONG PI; // 0x0c
218 // AHCI Version
219 ULONG VS; // 0x10
220
221 ULONG CCC_CTL; // 0x14
222 ULONG CCC_PORTS; // 0x18
223 ULONG EM_LOC; // 0x1c
224 ULONG EM_CTL; // 0x20
225
226 // Extended HBA Capabilities
227 struct { // 0x24
228 ULONG BOH:1; // BIOS/OS Handoff
229 ULONG NVMP:1; // NVMHCI Present
230 ULONG APST:1; // Automatic Partial to Slumber Transitions
231 ULONG Reserved:29;
232 } CAP2;
233
234 #define AHCI_CAP2_BOH 0x00000001
235 #define AHCI_CAP2_NVMP 0x00000002
236 #define AHCI_CAP2_APST 0x00000004
237
238 // BIOS/OS Handoff Control and Status
239 struct { // 0x28
240 ULONG BB:1; // BIOS Busy
241 ULONG OOC:1; // OS Ownership Change
242 ULONG SOOE:1; // SMI on OS Ownership Change Enable
243 ULONG OOS:1; // OS Owned Semaphore
244 ULONG BOS:1; // BIOS Owned Semaphore
245 ULONG Reserved:27;
246 } BOHC;
247
248 UCHAR Reserved2[0x74];
249
250 UCHAR VendorSpec[0x60];
251 } IDE_AHCI_REGISTERS, *PIDE_AHCI_REGISTERS;
252
253 #define IDX_AHCI_CAP (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))
254 #define IDX_AHCI_GHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))
255 #define IDX_AHCI_IS (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))
256 #define IDX_AHCI_VS (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))
257 #define IDX_AHCI_PI (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))
258 #define IDX_AHCI_CAP2 (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP2))
259 #define IDX_AHCI_BOHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, BOHC))
260
261
262 typedef union _SATA_SSTATUS_REG {
263
264 struct {
265 ULONG DET:4; // Device Detection
266
267 #define SStatus_DET_NoDev 0x00
268 #define SStatus_DET_Dev_NoPhy 0x01
269 #define SStatus_DET_Dev_Ok 0x03
270 #define SStatus_DET_Offline 0x04
271
272 ULONG SPD:4; // Current Interface Speed
273
274 #define SStatus_SPD_NoDev 0x00
275 #define SStatus_SPD_Gen1 0x01
276 #define SStatus_SPD_Gen2 0x02
277 #define SStatus_SPD_Gen3 0x03
278
279 ULONG IPM:4; // Interface Power Management
280
281 #define SStatus_IPM_NoDev 0x00
282 #define SStatus_IPM_Active 0x01
283 #define SStatus_IPM_Partial 0x02
284 #define SStatus_IPM_Slumber 0x06
285
286 ULONG Reserved:20;
287 };
288 ULONG Reg;
289
290 } SATA_SSTATUS_REG, *PSATA_SSTATUS_REG;
291
292
293 typedef union _SATA_SCONTROL_REG {
294
295 struct {
296 ULONG DET:4; // Device Detection Init
297
298 #define SControl_DET_DoNothing 0x00
299 #define SControl_DET_Idle 0x00
300 #define SControl_DET_Init 0x01
301 #define SControl_DET_Disable 0x04
302
303 ULONG SPD:4; // Speed Allowed
304
305 #define SControl_SPD_NoRestrict 0x00
306 #define SControl_SPD_LimGen1 0x01
307 #define SControl_SPD_LimGen2 0x02
308 #define SControl_SPD_LimGen3 0x03
309
310 ULONG IPM:4; // Interface Power Management Transitions Allowed
311
312 #define SControl_IPM_NoRestrict 0x00
313 #define SControl_IPM_NoPartial 0x01
314 #define SControl_IPM_NoSlumber 0x02
315 #define SControl_IPM_NoPartialSlumber 0x03
316
317 ULONG SPM:4; // Select Power Management, unused by AHCI
318 ULONG PMP:4; // Port Multiplier Port, unused by AHCI
319 ULONG Reserved:12;
320 };
321 ULONG Reg;
322
323 } SATA_SCONTROL_REG, *PSATA_SCONTROL_REG;
324
325
326 typedef union _SATA_SERROR_REG {
327
328 struct {
329 struct {
330 UCHAR I:1; // Recovered Data Integrity Error
331 UCHAR M:1; // Recovered Communications Error
332 UCHAR Reserved_2_7:6;
333
334 UCHAR T:1; // Transient Data Integrity Error
335 UCHAR C:1; // Persistent Communication or Data Integrity Error
336 UCHAR P:1; // Protocol Error
337 UCHAR E:1; // Internal Error
338 UCHAR Reserved_12_15:4;
339 } ERR;
340
341 struct {
342 UCHAR N:1; // PhyRdy Change, PIS.PRCS
343 UCHAR I:1; // Phy Internal Error
344 UCHAR W:1; // Comm Wake
345 UCHAR B:1; // 10B to 8B Decode Error
346 UCHAR D:1; // Disparity Error, not used by AHCI
347 UCHAR C:1; // CRC Error
348 UCHAR H:1; // Handshake Error
349 UCHAR S:1; // Link Sequence Error
350
351 UCHAR T:1; // Transport state transition error
352 UCHAR F:1; // Unknown FIS Type
353 UCHAR X:1; // Exchanged
354 UCHAR Reserved_27_31:5;
355 } DIAG;
356 };
357 ULONG Reg;
358
359 } SATA_SERROR_REG, *PSATA_SERROR_REG;
360
361
362 typedef struct _IDE_SATA_REGISTERS {
363 union {
364 SATA_SSTATUS_REG SStatus;
365 ULONG SStatus_Reg;
366 };
367 union {
368 SATA_SERROR_REG SError;
369 ULONG SError_Reg;
370 };
371 union {
372 SATA_SCONTROL_REG SControl;
373 ULONG SControl_Reg;
374 };
375
376 // SATA 1.2
377
378 ULONG SActive;
379 union {
380 ULONG Reg;
381 struct {
382 USHORT PMN; // PM Notify, bitmask
383 USHORT Reserved;
384 };
385 } SNTF;
386 ULONG SReserved[11];
387 } IDE_SATA_REGISTERS, *PIDE_SATA_REGISTERS;
388
389 #define IDX_SATA_IO (IDX_BM_IO+IDX_BM_IO_SZ)
390 //#define IDX_SATA_IO_SZ sizeof(IDE_SATA_REGISTERS)
391 #define IDX_SATA_IO_SZ 5
392
393 #define IDX_SATA_SStatus (0+IDX_SATA_IO)
394 #define IDX_SATA_SError (1+IDX_SATA_IO)
395 #define IDX_SATA_SControl (2+IDX_SATA_IO)
396 #define IDX_SATA_SActive (3+IDX_SATA_IO)
397 #define IDX_SATA_SNTF_PMN (4+IDX_SATA_IO)
398
399 #define IDX_INDEXED_IO (IDX_SATA_IO+IDX_SATA_IO_SZ)
400 #define IDX_INDEXED_IO_SZ 2
401
402 #define IDX_INDEXED_ADDR (0+IDX_INDEXED_IO)
403 #define IDX_INDEXED_DATA (1+IDX_INDEXED_IO)
404
405 #define IDX_MAX_REG (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)
406
407
408 typedef union _AHCI_IS_REG {
409 struct {
410 ULONG DHRS:1;// Device to Host Register FIS Interrupt
411 ULONG PSS:1; // PIO Setup FIS Interrupt
412 ULONG DSS:1; // DMA Setup FIS Interrupt
413 ULONG SDBS:1;// Set Device Bits Interrupt
414 ULONG UFS:1; // Unknown FIS Interrupt
415 ULONG DPS:1; // Descriptor Processed
416 ULONG PCS:1; // Port Connect Change Status
417 ULONG DMPS:1;// Device Mechanical Presence Status
418
419 ULONG Reserved_8_21:14;
420 ULONG PRCS:1;// PhyRdy Change Status
421 ULONG IPMS:1;// Incorrect Port Multiplier Status
422
423 ULONG OFS:1; // Overflow Status
424 ULONG Reserved_25:1;
425 ULONG INFS:1;// Interface Non-fatal Error Status
426 ULONG IFS:1; // Interface Fatal Error Status
427 ULONG HBDS:1;// Host Bus Data Error Status
428 ULONG HBFS:1;// Host Bus Fatal Error Status
429 ULONG TFES:1;// Task File Error Status
430 ULONG CPDS:1;// Cold Port Detect Status
431 };
432 ULONG Reg;
433 } AHCI_IS_REG, *PAHCI_IS_REG;
434
435 #define ATA_AHCI_P_IX_DHR 0x00000001
436 #define ATA_AHCI_P_IX_PS 0x00000002
437 #define ATA_AHCI_P_IX_DS 0x00000004
438 #define ATA_AHCI_P_IX_SDB 0x00000008
439 #define ATA_AHCI_P_IX_UF 0x00000010
440 #define ATA_AHCI_P_IX_DP 0x00000020
441 #define ATA_AHCI_P_IX_PC 0x00000040
442 #define ATA_AHCI_P_IX_DI 0x00000080
443
444 #define ATA_AHCI_P_IX_PRC 0x00400000
445 #define ATA_AHCI_P_IX_IPM 0x00800000
446 #define ATA_AHCI_P_IX_OF 0x01000000
447 #define ATA_AHCI_P_IX_INF 0x04000000
448 #define ATA_AHCI_P_IX_IF 0x08000000
449 #define ATA_AHCI_P_IX_HBD 0x10000000
450 #define ATA_AHCI_P_IX_HBF 0x20000000
451 #define ATA_AHCI_P_IX_TFE 0x40000000
452 #define ATA_AHCI_P_IX_CPD 0x80000000
453
454 #define AHCI_CLB_ALIGNEMENT_MASK ((ULONGLONG)(1024-1))
455 #define AHCI_FIS_ALIGNEMENT_MASK ((ULONGLONG)(256-1))
456 #define AHCI_CMD_ALIGNEMENT_MASK ((ULONGLONG)(128-1))
457
458 typedef struct _IDE_AHCI_PORT_REGISTERS {
459 union {
460 struct {
461 ULONG CLB; // command list base address, 1K-aligned
462 ULONG CLBU; // command list base address (upper 32bits)
463 };
464 ULONGLONG CLB64;
465 }; // 0x100 + 0x80*c + 0x0000
466
467 union {
468 struct {
469 ULONG FB; // FIS base address
470 ULONG FBU; // FIS base address (upper 32bits)
471 };
472 ULONGLONG FB64;
473 }; // 0x100 + 0x80*c + 0x0008
474
475 union {
476 ULONG IS_Reg; // interrupt status
477 AHCI_IS_REG IS;
478 }; // 0x100 + 0x80*c + 0x0010
479
480 union {
481 ULONG Reg; // interrupt enable
482 struct {
483 ULONG DHRE:1;// Device to Host Register FIS Interrupt Enable
484 ULONG PSE:1; // PIO Setup FIS Interrupt Enable
485 ULONG DSE:1; // DMA Setup FIS Interrupt Enable
486 ULONG SDBE:1;// Set Device Bits FIS Interrupt Enable
487 ULONG UFE:1; // Unknown FIS Interrupt Enable
488 ULONG DPE:1; // Descriptor Processed Interrupt Enable
489 ULONG PCE:1; // Port Change Interrupt Enable
490 ULONG DPME:1;// Device Mechanical Presence Enable
491
492 ULONG Reserved_8_21:14;
493 ULONG PRCE:1;// PhyRdy Change Interrupt Enable
494 ULONG IPME:1;// Incorrect Port Multiplier Enable
495 ULONG OFE:1; // Overflow Enable
496 ULONG Reserved_25:1;
497 ULONG INFE:1;// Interface Non-fatal Error Enable
498 ULONG IFE:1; // Interface Fatal Error Enable
499 ULONG HBDE:1;// Host Bus Data Error Enable
500 ULONG HBFE:1;// Host Bus Fatal Error Enable
501 ULONG TFEE:1;// Task File Error Enable
502 ULONG CPDE:1;// Cold Port Detect Enable
503 };
504 } IE; // 0x100 + 0x80*c + 0x0014
505
506 union {
507 ULONG Reg; // command register
508 struct {
509
510 ULONG ST:1; // Start
511 ULONG SUD:1; // Spin-Up Device
512 ULONG POD:1; // Power On Device
513 ULONG CLO:1; // Command List Override
514 ULONG FRE:1; // FIS Receive Enable
515 ULONG Reserved_5_7:3;
516
517 ULONG CCS:5; // Current Command Slot
518 ULONG MPSS:1;// Mechanical Presence Switch State
519 ULONG FR:1; // FIS Receive Running
520 ULONG CR:1; // Command List Running
521
522 ULONG CPS:1; // Cold Presence State
523 ULONG PMA:1; // Port Multiplier Attached
524 ULONG HPCP:1;// Hot Plug Capable Port
525 ULONG MPSP:1;// Mechanical Presence Switch Attached to Port
526 ULONG CPD:1; // Cold Presence Detection
527 ULONG ESP:1; // External SATA Port
528 ULONG Reserved_22_23:2;
529
530 ULONG ATAPI:1; // Device is ATAPI
531 ULONG DLAE:1;// Drive LED on ATAPI Enable
532 ULONG ALPE:1;// Aggressive Link Power Management Enable
533 ULONG ASP:1; // Aggressive Slumber / Partial
534 ULONG ICC:4; // Interface Communication Control
535
536 #define SATA_CMD_ICC_Idle 0x00
537 #define SATA_CMD_ICC_NoOp 0x00
538 #define SATA_CMD_ICC_Active 0x01
539 #define SATA_CMD_ICC_Partial 0x02
540 #define SATA_CMD_ICC_Slumber 0x06
541 };
542 } CMD; // 0x100 + 0x80*c + 0x0018
543
544 ULONG Reserved;
545
546 union {
547 ULONG Reg; // Task File Data
548 struct {
549 struct {
550 UCHAR ERR:1;
551 UCHAR cs1:2;// command-specific
552 UCHAR DRQ:1;
553 UCHAR cs2:3;// command-specific
554 UCHAR BSY:1;
555 } STS;
556 UCHAR ERR; // Contains the latest copy of the task file error register.
557 UCHAR Reserved[2];
558 };
559 } TFD; // 0x100 + 0x80*c + 0x0020
560
561 union {
562 ULONG Reg; // signature
563 struct {
564 UCHAR SectorCount;
565 UCHAR LbaLow;
566 UCHAR LbaMid;
567 UCHAR LbaHigh;
568 };
569 } SIG; // 0x100 + 0x80*c + 0x0024
570 union {
571 ULONG SStatus; // SCR0
572 SATA_SSTATUS_REG SSTS;
573 }; // 0x100 + 0x80*c + 0x0028
574 union {
575 ULONG SControl; // SCR2
576 SATA_SCONTROL_REG SCTL;
577 }; // 0x100 + 0x80*c + 0x002c
578 union {
579 ULONG SError; // SCR1
580 SATA_SERROR_REG SERR;
581 }; // 0x100 + 0x80*c + 0x0030
582 union {
583 ULONG SACT; // SCR3
584 ULONG SActive; // bitmask
585 }; // 0x100 + 0x80*c + 0x0034
586
587 ULONG CI; // Command issue, bitmask, 0x100 + 0x80*c + 0x0038
588
589 // AHCI 1.1
590 union {
591 ULONG Reg;
592 struct {
593 USHORT PMN; // PM Notify, bitmask
594 USHORT Reserved;
595 };
596 } SNTF; // 0x100 + 0x80*c + 0x003c
597
598 // AHCI 1.2
599 union {
600 ULONG Reg;
601 struct {
602 ULONG EN:1; // Enable
603 ULONG DEC:1; // Device Error Clear
604 ULONG SDE:1; // Single Device Error
605 ULONG Reserved_3_7:5; // Reserved
606 ULONG DEV:4; // Device To Issue
607 ULONG ADO:4; // Active Device Optimization (recommended parallelism)
608 ULONG DWE:4; // Device With Error
609 ULONG Reserved_20_31:12; // Reserved
610 };
611 } FBS; // 0x100 + 0x80*c + 0x0040
612
613 ULONG Reserved_44_7f[11];
614 UCHAR VendorSpec[16];
615
616 } IDE_AHCI_PORT_REGISTERS, *PIDE_AHCI_PORT_REGISTERS;
617
618 #define IDX_AHCI_P_CLB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))
619 #define IDX_AHCI_P_FB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))
620 #define IDX_AHCI_P_IS (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
621 #define IDX_AHCI_P_IE (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))
622 #define IDX_AHCI_P_CI (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
623 #define IDX_AHCI_P_TFD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
624 #define IDX_AHCI_P_SIG (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
625 #define IDX_AHCI_P_CMD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
626 #define IDX_AHCI_P_ACT (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
627
628 #define IDX_AHCI_P_SNTF (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
629
630 // AHCI commands ( -> IDX_AHCI_P_CMD)
631 #define ATA_AHCI_P_CMD_ST 0x00000001
632 #define ATA_AHCI_P_CMD_SUD 0x00000002
633 #define ATA_AHCI_P_CMD_POD 0x00000004
634 #define ATA_AHCI_P_CMD_CLO 0x00000008
635 #define ATA_AHCI_P_CMD_FRE 0x00000010
636 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
637 #define ATA_AHCI_P_CMD_ISS 0x00002000
638 #define ATA_AHCI_P_CMD_FR 0x00004000
639 #define ATA_AHCI_P_CMD_CR 0x00008000
640 #define ATA_AHCI_P_CMD_CPS 0x00010000
641 #define ATA_AHCI_P_CMD_PMA 0x00020000
642 #define ATA_AHCI_P_CMD_HPCP 0x00040000
643 #define ATA_AHCI_P_CMD_ISP 0x00080000
644 #define ATA_AHCI_P_CMD_CPD 0x00100000
645 #define ATA_AHCI_P_CMD_ATAPI 0x01000000
646 #define ATA_AHCI_P_CMD_DLAE 0x02000000
647 #define ATA_AHCI_P_CMD_ALPE 0x04000000
648 #define ATA_AHCI_P_CMD_ASP 0x08000000
649 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
650 #define ATA_AHCI_P_CMD_NOOP 0x00000000
651 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000
652 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000
653 #define ATA_AHCI_P_CMD_SLUMBER 0x60000000
654
655
656 typedef struct _IDE_AHCI_PRD_ENTRY {
657 union {
658 ULONG base;
659 ULONGLONG base64;
660 struct {
661 ULONG DBA;
662 union {
663 ULONG DBAU;
664 ULONG baseu;
665 };
666 };
667 };
668 ULONG Reserved1;
669
670 union {
671 struct {
672 ULONG DBC:22;
673 ULONG Reserved2:9;
674 ULONG I:1;
675 };
676 ULONG DBC_ULONG;
677 };
678
679 } IDE_AHCI_PRD_ENTRY, *PIDE_AHCI_PRD_ENTRY;
680
681 #define ATA_AHCI_DMA_ENTRIES (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */
682 #define ATA_AHCI_MAX_TAGS 32
683
684 #define AHCI_FIS_TYPE_ATA_H2D 0x27
685 #define AHCI_FIS_TYPE_ATA_D2H 0x34
686 #define AHCI_FIS_TYPE_DMA_D2H 0x39
687 #define AHCI_FIS_TYPE_DMA_BiDi 0x41
688 #define AHCI_FIS_TYPE_DATA_BiDi 0x46
689 #define AHCI_FIS_TYPE_BIST_BiDi 0x58
690 #define AHCI_FIS_TYPE_PIO_D2H 0x5f
691 #define AHCI_FIS_TYPE_DEV_BITS_D2H 0xA1
692
693 typedef struct _AHCI_ATA_H2D_FIS {
694 UCHAR FIS_Type; // = 0x27
695 UCHAR Reserved1:7;
696 UCHAR Cmd:1; // update Command register
697 UCHAR Command; // [2]
698 UCHAR Feature; // [3]
699
700 UCHAR BlockNumber; // [4]
701 UCHAR CylinderLow; // [5]
702 UCHAR CylinderHigh; // [6]
703 UCHAR DriveSelect; // [7]
704
705 UCHAR BlockNumberExp; // [8]
706 UCHAR CylinderLowExp; // [9]
707 UCHAR CylinderHighExp; // [10]
708 UCHAR FeatureExp; // [11]
709
710 UCHAR BlockCount; // [12]
711 UCHAR BlockCountExp; // [13]
712 UCHAR Reserved14; // [14]
713 UCHAR Control; // [15]
714
715 } AHCI_ATA_H2D_FIS, *PAHCI_ATA_H2D_FIS;
716
717 #define IDX_AHCI_o_Command (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Command))
718 #define IDX_AHCI_o_Feature (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Feature))
719 #define IDX_AHCI_o_BlockNumber (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumber ))
720 #define IDX_AHCI_o_CylinderLow (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLow ))
721 #define IDX_AHCI_o_CylinderHigh (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHigh))
722 #define IDX_AHCI_o_DriveSelect (FIELD_OFFSET(AHCI_ATA_H2D_FIS, DriveSelect ))
723 #define IDX_AHCI_o_BlockCount (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCount))
724 #define IDX_AHCI_o_Control (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Control))
725 #define IDX_AHCI_o_FeatureExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, FeatureExp))
726 #define IDX_AHCI_o_BlockNumberExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumberExp ))
727 #define IDX_AHCI_o_CylinderLowExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLowExp ))
728 #define IDX_AHCI_o_CylinderHighExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHighExp))
729 #define IDX_AHCI_o_BlockCountExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCountExp))
730
731 #define AHCI_FIS_COMM_PM (0x80 | AHCI_DEV_SEL_PM)
732
733 #define AHCI_DEV_SEL_1 0x00
734 #define AHCI_DEV_SEL_2 0x01
735 #define AHCI_DEV_SEL_PM 0x0f
736
737 /* 128-byte aligned */
738 typedef struct _IDE_AHCI_CMD {
739 UCHAR cfis[64];
740 UCHAR acmd[16];
741 UCHAR Reserved[48];
742 IDE_AHCI_PRD_ENTRY prd_tab[ATA_AHCI_DMA_ENTRIES]; // also 128-byte aligned
743 } IDE_AHCI_CMD, *PIDE_AHCI_CMD;
744
745
746 /* cmd_flags */
747 #define ATA_AHCI_CMD_ATAPI 0x0020
748 #define ATA_AHCI_CMD_WRITE 0x0040
749 #define ATA_AHCI_CMD_PREFETCH 0x0080
750 #define ATA_AHCI_CMD_RESET 0x0100
751 #define ATA_AHCI_CMD_BIST 0x0200
752 #define ATA_AHCI_CMD_CLR_BUSY 0x0400
753
754 /* 128-byte aligned */
755 typedef struct _IDE_AHCI_CMD_LIST {
756 USHORT cmd_flags;
757 USHORT prd_length; /* PRD entries */
758 ULONG bytecount;
759 ULONGLONG cmd_table_phys; /* points to IDE_AHCI_CMD */
760 ULONG Reserved[4];
761 } IDE_AHCI_CMD_LIST, *PIDE_AHCI_CMD_LIST;
762
763 /* 256-byte aligned */
764 typedef struct _IDE_AHCI_RCV_FIS {
765 UCHAR dsfis[28];
766 UCHAR Reserved1[4];
767 UCHAR psfis[20];
768 UCHAR Reserved2[12];
769 UCHAR rfis[20];
770 UCHAR Reserved3[4];
771 UCHAR SDBFIS[8];
772 UCHAR ufis[64];
773 UCHAR Reserved4[96];
774 } IDE_AHCI_RCV_FIS, *PIDE_AHCI_RCV_FIS;
775
776 /* 1K-byte aligned */
777 typedef struct _IDE_AHCI_CHANNEL_CTL_BLOCK {
778 IDE_AHCI_CMD_LIST cmd_list[ATA_AHCI_MAX_TAGS]; // 1K-size (32*32)
779 IDE_AHCI_RCV_FIS rcv_fis;
780 IDE_AHCI_CMD cmd; // for single internal commands w/o associated AtaReq
781 } IDE_AHCI_CHANNEL_CTL_BLOCK, *PIDE_AHCI_CHANNEL_CTL_BLOCK;
782
783
784 #define IsBusMaster(pciData) \
785 ( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/)) == \
786 (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/))
787
788 #define PCI_IDE_PROGIF_NATIVE_1 0x01
789 #define PCI_IDE_PROGIF_NATIVE_2 0x04
790 #define PCI_IDE_PROGIF_NATIVE_ALL 0x05
791
792 #define IsMasterDev(pciData) \
793 ( ((pciData)->ProgIf & 0x80) && \
794 ((pciData)->ProgIf & PCI_IDE_PROGIF_NATIVE_ALL) != PCI_IDE_PROGIF_NATIVE_ALL )
795
796 //#define INT_Q_SIZE 32
797 #define MIN_REQ_TTL 4
798
799 union _ATA_REQ;
800
801 typedef union _ATA_REQ {
802 // ULONG reqId; // serial
803 struct {
804
805 //union {
806
807 struct {
808 union _ATA_REQ* next_req;
809 union _ATA_REQ* prev_req;
810
811 PSCSI_REQUEST_BLOCK Srb; // Current request on controller.
812
813 PUSHORT DataBuffer; // Data buffer pointer.
814 ULONG WordsLeft; // Data words left.
815 ULONG TransferLength; // Originally requested transfer length
816 LONGLONG lba;
817 ULONG WordsTransfered;// Data words already transfered.
818 ULONG bcount;
819
820 UCHAR retry;
821 UCHAR ttl;
822 // UCHAR tag;
823 UCHAR Flags;
824 UCHAR ReqState;
825
826 PSCSI_REQUEST_BLOCK OriginalSrb; // Mechanism Status Srb Data
827
828 ULONG dma_entries;
829 union {
830 // for ATA
831 struct {
832 ULONG dma_base;
833 ULONG dma_baseu;
834 } ata;
835 // for AHCI
836 struct {
837 ULONGLONG ahci_base64;
838 ULONGLONG in_lba;
839 PIDE_AHCI_CMD ahci_cmd_ptr;
840 ULONG in_bcount;
841 ULONG in_status;
842 USHORT io_cmd_flags; // out
843 UCHAR in_error;
844 } ahci;
845 };
846 };
847 //UCHAR padding_128b[128]; // Note: we assume, NT allocates block > 4k as PAGE-aligned
848 //};
849 struct {
850 union {
851 BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
852 IDE_AHCI_CMD ahci_cmd0; // for AHCI, 128-byte aligned
853 };
854 };
855 };
856
857 UCHAR padding_4kb[PAGE_SIZE];
858
859 } ATA_REQ, *PATA_REQ;
860
861 #define REQ_FLAG_FORCE_DOWNRATE 0x01
862 #define REQ_FLAG_DMA_OPERATION 0x02
863 #define REQ_FLAG_REORDERABLE_CMD 0x04
864 #define REQ_FLAG_RW_MASK 0x08
865 #define REQ_FLAG_READ 0x08
866 #define REQ_FLAG_WRITE 0x00
867 #define REQ_FLAG_FORCE_DOWNRATE_LBA48 0x10
868 #define REQ_FLAG_DMA_DBUF 0x20
869 #define REQ_FLAG_DMA_DBUF_PRD 0x40
870 #define REQ_FLAG_LBA48 0x80
871
872 // Request states
873 #define REQ_STATE_NONE 0x00
874 #define REQ_STATE_QUEUED 0x10
875
876 #define REQ_STATE_PREPARE_TO_TRANSFER 0x20
877 #define REQ_STATE_PREPARE_TO_NEXT 0x21
878 #define REQ_STATE_READY_TO_TRANSFER 0x30
879
880 #define REQ_STATE_EXPECTING_INTR 0x40
881 #define REQ_STATE_ATAPI_EXPECTING_CMD_INTR 0x41
882 #define REQ_STATE_ATAPI_EXPECTING_DATA_INTR 0x42
883 #define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2 0x43
884 #define REQ_STATE_ATAPI_DO_NOTHING_INTR 0x44
885
886 #define REQ_STATE_EARLY_INTR 0x48
887
888 #define REQ_STATE_PROCESSING_INTR 0x50
889
890 #define REQ_STATE_DPC_INTR_REQ 0x51
891 #define REQ_STATE_DPC_RESET_REQ 0x52
892 #define REQ_STATE_DPC_COMPLETE_REQ 0x53
893
894 #define REQ_STATE_DPC_WAIT_BUSY0 0x57
895 #define REQ_STATE_DPC_WAIT_BUSY1 0x58
896 #define REQ_STATE_DPC_WAIT_BUSY 0x59
897 #define REQ_STATE_DPC_WAIT_DRQ 0x5a
898 #define REQ_STATE_DPC_WAIT_DRQ0 0x5b
899 #define REQ_STATE_DPC_WAIT_DRQ_ERR 0x5c
900
901 #define REQ_STATE_TRANSFER_COMPLETE 0x7f
902
903 // Command actions:
904 #define CMD_ACTION_PREPARE 0x01
905 #define CMD_ACTION_EXEC 0x02
906 #define CMD_ACTION_ALL (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)
907
908 // predefined Reorder costs
909 #define REORDER_COST_MAX ((DEF_I64(0x1) << 60) - 1)
910 #define REORDER_COST_TTL (REORDER_COST_MAX - 1)
911 #define REORDER_COST_INTERSECT (REORDER_COST_MAX - 2)
912 #define REORDER_COST_DENIED (REORDER_COST_MAX - 3)
913 #define REORDER_COST_RESELECT (REORDER_COST_MAX/4)
914
915 #define REORDER_COST_SWITCH_RW_CD (REORDER_COST_MAX/8)
916 #define REORDER_MCOST_SWITCH_RW_CD (0)
917 #define REORDER_MCOST_SEEK_BACK_CD (16)
918
919 #define REORDER_COST_SWITCH_RW_HDD (0)
920 #define REORDER_MCOST_SWITCH_RW_HDD (4)
921 #define REORDER_MCOST_SEEK_BACK_HDD (2)
922
923 /*typedef struct _ATA_QUEUE {
924 struct _ATA_REQ* head_req; // index
925 struct _ATA_REQ* tail_req; // index
926 ULONG req_count;
927 ULONG dma_base;
928 BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
929 } ATA_QUEUE, *PATA_QUEUE;*/
930
931 struct _HW_DEVICE_EXTENSION;
932 struct _HW_LU_EXTENSION;
933
934 typedef struct _IORES {
935 union {
936 ULONG Addr; /* Base address*/
937 PVOID pAddr; /* Base address in pointer form */
938 };
939 ULONG MemIo:1; /* Memory mapping (1) vs IO ports (0) */
940 ULONG Proc:1; /* Need special processing via IO_Proc */
941 ULONG Reserved:30;
942 } IORES, *PIORES;
943
944 // Channel extension
945 typedef struct _HW_CHANNEL {
946
947 PATA_REQ cur_req;
948 ULONG cur_cdev;
949 /* PATA_REQ first_req;
950 PATA_REQ last_req;*/
951 ULONG queue_depth;
952 ULONG ChannelSelectWaitCount;
953
954 UCHAR DpcState;
955
956 BOOLEAN ExpectingInterrupt; // Indicates expecting an interrupt
957 BOOLEAN RDP; // Indicate last tape command was DSC Restrictive.
958 // Indicates whether '0x1f0' is the base address. Used
959 // in SMART Ioctl calls.
960 BOOLEAN PrimaryAddress;
961 // Placeholder for the sub-command value of the last
962 // SMART command.
963 UCHAR SmartCommand;
964 // Reorder anabled
965 BOOLEAN UseReorder;
966 // Placeholder for status register after a GET_MEDIA_STATUS command
967 UCHAR ReturningMediaStatus;
968
969 BOOLEAN CopyDmaBuffer;
970 //BOOLEAN MemIo;
971 BOOLEAN AltRegMap;
972
973 UCHAR Reserved[3];
974
975 MECHANICAL_STATUS_INFORMATION_HEADER MechStatusData;
976 SENSE_DATA MechStatusSense;
977 ULONG MechStatusRetryCount;
978 SCSI_REQUEST_BLOCK InternalSrb;
979
980 ULONG MaxTransferMode; // may differ from Controller's value due to 40-pin cable
981
982 ULONG ChannelCtrlFlags;
983 ULONG ResetInProgress; // flag
984 LONG DisableIntr;
985 LONG CheckIntr;
986
987 ULONG lChannel;
988
989 #define CHECK_INTR_ACTIVE 0x03
990 #define CHECK_INTR_DETECTED 0x02
991 #define CHECK_INTR_CHECK 0x01
992 #define CHECK_INTR_IDLE 0x00
993
994 ULONG NextDpcChan;
995 PHW_TIMER HwScsiTimer;
996 LONGLONG DpcTime;
997 #if 0
998 PHW_TIMER HwScsiTimer1;
999 PHW_TIMER HwScsiTimer2;
1000 LONGLONG DpcTime1;
1001 // PHW_TIMER CurDpc;
1002 // LARGE_INTEGER ActivationTime;
1003
1004 // KDPC Dpc;
1005 // KTIMER Timer;
1006 // PHW_TIMER HwScsiTimer;
1007 // KSPIN_LOCK QueueSpinLock;
1008 // KIRQL QueueOldIrql;
1009 #endif
1010 struct _HW_DEVICE_EXTENSION* DeviceExtension;
1011 struct _HW_LU_EXTENSION* lun[IDE_MAX_LUN_PER_CHAN];
1012
1013 ULONG NumberLuns;
1014 ULONG PmLunMap;
1015
1016 // Double-buffering support
1017 PVOID DB_PRD;
1018 ULONG DB_PRD_PhAddr;
1019 PVOID DB_IO;
1020 ULONG DB_IO_PhAddr;
1021
1022 PUCHAR DmaBuffer;
1023
1024 //
1025 PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock0; // unaligned
1026 PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock; // 128-byte aligned
1027 ULONGLONG AHCI_CTL_PhAddr;
1028 IORES BaseIoAHCI_Port;
1029 ULONG AhciPrevCI;
1030 ULONG AhciCompleteCI;
1031 ULONG AhciLastIS;
1032 //PVOID AHCI_FIS; // is not actually used by UniATA now, but is required by AHCI controller
1033 //ULONGLONG AHCI_FIS_PhAddr;
1034 // Note: in contrast to FBSD, we keep PRD and CMD item in AtaReq structure
1035 PATA_REQ AhciInternalAtaReq;
1036 PSCSI_REQUEST_BLOCK AhciInternalSrb;
1037
1038 #ifdef QUEUE_STATISTICS
1039 LONGLONG QueueStat[MAX_QUEUE_STAT];
1040 LONGLONG ReorderCount;
1041 LONGLONG IntersectCount;
1042 LONGLONG TryReorderCount;
1043 LONGLONG TryReorderHeadCount;
1044 LONGLONG TryReorderTailCount; /* in-order requests */
1045 #endif //QUEUE_STATISTICS
1046
1047 //ULONG BaseMemAddress;
1048 //ULONG BaseMemAddressOffset;
1049 IORES RegTranslation[IDX_MAX_REG];
1050
1051 } HW_CHANNEL, *PHW_CHANNEL;
1052
1053 #define CTRFLAGS_DMA_ACTIVE 0x0001
1054 #define CTRFLAGS_DMA_RO 0x0002
1055 #define CTRFLAGS_DMA_OPERATION 0x0004
1056 #define CTRFLAGS_INTR_DISABLED 0x0008
1057 #define CTRFLAGS_DPC_REQ 0x0010
1058 #define CTRFLAGS_ENABLE_INTR_REQ 0x0020
1059 #define CTRFLAGS_LBA48 0x0040
1060 #define CTRFLAGS_DSC_BSY 0x0080
1061 #define CTRFLAGS_NO_SLAVE 0x0100
1062 //#define CTRFLAGS_PATA 0x0200
1063 #define CTRFLAGS_AHCI_PM 0x0400
1064 #define CTRFLAGS_AHCI_PM2 0x0800
1065
1066 #define CTRFLAGS_PERMANENT (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)
1067
1068 #define GEOM_AUTO 0xffffffff
1069 #define GEOM_STD 0x0000
1070 #define GEOM_UNIATA 0x0001
1071 #define GEOM_ORIG 0x0002
1072 #define GEOM_MANUAL 0x0003
1073
1074 #define DPC_STATE_NONE 0x00
1075 #define DPC_STATE_ISR 0x10
1076 #define DPC_STATE_DPC 0x20
1077 #define DPC_STATE_TIMER 0x30
1078 #define DPC_STATE_COMPLETE 0x40
1079
1080 // Logical unit extension
1081 typedef struct _HW_LU_EXTENSION {
1082 IDENTIFY_DATA2 IdentifyData;
1083 ULONGLONG NumOfSectors;
1084 ULONG DeviceFlags; // Flags word for each possible device. DFLAGS_XXX
1085 ULONG DiscsPresent; // Indicates number of platters on changer-ish devices.
1086 BOOLEAN DWordIO; // Indicates use of 32-bit PIO
1087 UCHAR ReturningMediaStatus;
1088
1089 UCHAR TransferMode; // current transfer mode
1090 UCHAR LimitedTransferMode; // user-defined or IDE cable limitation
1091 UCHAR OrigTransferMode; // transfer mode, returned by device IDENTIFY (can be changed via IOCTL)
1092
1093 UCHAR MaximumBlockXfer;
1094 UCHAR Padding0[2]; // padding
1095 ULONG ErrorCount; // Count of errors. Used to turn off features.
1096 // ATA_QUEUE cmd_queue;
1097 LONGLONG ReadCmdCost;
1098 LONGLONG WriteCmdCost;
1099 LONGLONG OtherCmdCost;
1100 LONGLONG RwSwitchCost;
1101 LONGLONG RwSwitchMCost;
1102 LONGLONG SeekBackMCost;
1103 //
1104 PATA_REQ first_req;
1105 PATA_REQ last_req;
1106 ULONG queue_depth;
1107 ULONG last_write;
1108
1109 ULONG LunSelectWaitCount;
1110 ULONG AtapiReadyWaitDelay;
1111
1112 // tuning options
1113 ULONG opt_GeomType;
1114 ULONG opt_MaxTransferMode;
1115 ULONG opt_PreferedTransferMode;
1116 BOOLEAN opt_ReadCacheEnable;
1117 BOOLEAN opt_WriteCacheEnable;
1118 UCHAR opt_ReadOnly;
1119 // padding
1120 BOOLEAN opt_reserved[1];
1121
1122 struct _SBadBlockListItem* bbListDescr;
1123 struct _SBadBlockRange* arrBadBlocks;
1124 ULONG nBadBlocks;
1125
1126 // Controller-specific LUN options
1127 union {
1128 /* for tricky controllers, those can change Logical-to-Physical LUN mapping.
1129 mainly for mapping SATA ports to compatible PATA registers
1130 Treated as PHYSICAL port number, regardless of logical mapping.
1131 */
1132 ULONG SATA_lun_map;
1133 };
1134
1135 struct _HW_DEVICE_EXTENSION* DeviceExtension;
1136 struct _HW_CHANNEL* chan;
1137 ULONG Lun;
1138
1139 #ifdef IO_STATISTICS
1140
1141 LONGLONG ModeErrorCount[MAX_RETRIES];
1142 LONGLONG RecoverCount[MAX_RETRIES];
1143 LONGLONG IoCount;
1144 LONGLONG BlockIoCount;
1145
1146 #endif//IO_STATISTICS
1147 } HW_LU_EXTENSION, *PHW_LU_EXTENSION;
1148
1149 // Device extension
1150 typedef struct _HW_DEVICE_EXTENSION {
1151 CHAR Signature[32];
1152 //PIDE_REGISTERS_1 BaseIoAddress1[IDE_MAX_CHAN]; // Base register locations
1153 //PIDE_REGISTERS_2 BaseIoAddress2[IDE_MAX_CHAN];
1154 ULONG BusInterruptLevel; // Interrupt level
1155 ULONG InterruptMode; // Interrupt Mode (Level or Edge)
1156 ULONG BusInterruptVector;
1157 // Number of channels being supported by one instantiation
1158 // of the device extension. Normally (and correctly) one, but
1159 // with so many broken PCI IDE controllers being sold, we have
1160 // to support them.
1161 ULONG NumberChannels;
1162 ULONG NumberLuns;
1163 ULONG FirstChannelToCheck;
1164 #if 0
1165 HW_LU_EXTENSION lun[IDE_MAX_LUN];
1166 HW_CHANNEL chan[AHCI_MAX_PORT/*IDE_MAX_CHAN*/];
1167 #else
1168 PHW_LU_EXTENSION lun; // lun array
1169 PHW_CHANNEL chan; // channel array
1170 #endif
1171 UCHAR LastInterruptedChannel;
1172 // Indicates the number of blocks transferred per int. according to the
1173 // identify data.
1174 BOOLEAN DriverMustPoll; // Driver is being used by the crash dump utility or ntldr.
1175 BOOLEAN BusMaster;
1176 BOOLEAN UseDpc; // Indicates use of DPC on long waits
1177 IDENTIFY_DATA FullIdentifyData; // Identify data for device
1178 // BusMaster specific data
1179 // PBM_DMA_ENTRY dma_tab_0;
1180 //KSPIN_LOCK DpcSpinLock;
1181
1182 ULONG ActiveDpcChan;
1183 ULONG FirstDpcChan;
1184 ULONG ExpectingInterrupt; // Indicates entire controller expecting an interrupt
1185 /*
1186 PHW_TIMER HwScsiTimer1;
1187 PHW_TIMER HwScsiTimer2;
1188 LONGLONG DpcTime1;
1189 LONGLONG DpcTime2;
1190 */
1191 ULONG queue_depth;
1192
1193 PDEVICE_OBJECT Isr2DevObj;
1194
1195 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0;
1196 IORES BaseIoAddressBM_0;
1197 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM[IDE_MAX_CHAN];
1198
1199 // Device identification
1200 ULONG DevID;
1201 ULONG RevID;
1202 ULONG slotNumber;
1203 ULONG SystemIoBusNumber;
1204 ULONG DevIndex;
1205
1206 ULONG InitMethod; // vendor specific
1207
1208 ULONG Channel;
1209
1210 ULONG HbaCtrlFlags;
1211 BOOLEAN simplexOnly;
1212 //BOOLEAN MemIo;
1213 BOOLEAN AltRegMap;
1214 BOOLEAN UnknownDev;
1215 BOOLEAN MasterDev;
1216 BOOLEAN Host64;
1217 BOOLEAN DWordIO; // Indicates use of 32-bit PIO
1218 UCHAR Reserved1[2];
1219
1220 LONG ReCheckIntr;
1221
1222 ULONG MaxTransferMode; // max transfer mode supported by controller
1223 ULONG HwFlags;
1224 INTERFACE_TYPE OrigAdapterInterfaceType;
1225 INTERFACE_TYPE AdapterInterfaceType;
1226 ULONG MaximumDmaTransferLength;
1227 ULONG AlignmentMask;
1228 ULONG DmaSegmentLength;
1229 ULONG DmaSegmentAlignmentMask; // must be PAGE-aligned
1230
1231 //ULONG BaseMemAddress;
1232
1233 //PIDE_SATA_REGISTERS BaseIoAddressSATA_0;
1234 IORES BaseIoAddressSATA_0;
1235 //PIDE_SATA_REGISTERS BaseIoAddressSATA[IDE_MAX_CHAN];
1236
1237 IORES BaseIoAHCI_0;
1238 //PIDE_AHCI_PORT_REGISTERS BaseIoAHCIPort[AHCI_MAX_PORT];
1239 ULONG AHCI_CAP;
1240 PATA_REQ AhciInternalAtaReq0;
1241 PSCSI_REQUEST_BLOCK AhciInternalSrb0;
1242
1243 BOOLEAN opt_AtapiDmaZeroTransfer; // default FALSE
1244 BOOLEAN opt_AtapiDmaControlCmd; // default FALSE
1245 BOOLEAN opt_AtapiDmaRawRead; // default TRUE
1246 BOOLEAN opt_AtapiDmaReadWrite; // default TRUE
1247
1248 PCCH FullDevName;
1249
1250 // Controller specific state/options
1251 union {
1252 ULONG HwCfg;
1253 };
1254
1255 } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
1256
1257 typedef struct _ISR2_DEVICE_EXTENSION {
1258 PHW_DEVICE_EXTENSION HwDeviceExtension;
1259 ULONG DevIndex;
1260 } ISR2_DEVICE_EXTENSION, *PISR2_DEVICE_EXTENSION;
1261
1262 #define HBAFLAGS_DMA_DISABLED 0x01
1263 #define HBAFLAGS_DMA_DISABLED_LBA48 0x02
1264
1265 extern UCHAR pciBuffer[256];
1266 extern PBUSMASTER_CONTROLLER_INFORMATION BMList;
1267 extern ULONG BMListLen;
1268 extern ULONG IsaCount;
1269 extern ULONG MCACount;
1270
1271 //extern const CHAR retry_Wdma[MAX_RETRIES+1];
1272 //extern const CHAR retry_Udma[MAX_RETRIES+1];
1273
1274 extern VOID
1275 NTAPI
1276 UniataEnumBusMasterController(
1277 IN PVOID DriverObject,
1278 PVOID Argument2
1279 );
1280
1281 extern ULONG NTAPI
1282 UniataFindCompatBusMasterController1(
1283 IN PVOID HwDeviceExtension,
1284 IN PVOID Context,
1285 IN PVOID BusInformation,
1286 IN PCHAR ArgumentString,
1287 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1288 OUT PBOOLEAN Again
1289 );
1290
1291 extern ULONG NTAPI
1292 UniataFindCompatBusMasterController2(
1293 IN PVOID HwDeviceExtension,
1294 IN PVOID Context,
1295 IN PVOID BusInformation,
1296 IN PCHAR ArgumentString,
1297 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1298 OUT PBOOLEAN Again
1299 );
1300
1301 #define UNIATA_ALLOCATE_NEW_LUNS 0x00
1302
1303 extern BOOLEAN NTAPI
1304 UniataAllocateLunExt(
1305 PHW_DEVICE_EXTENSION deviceExtension,
1306 ULONG NewNumberChannels
1307 );
1308
1309 extern VOID NTAPI
1310 UniataFreeLunExt(
1311 PHW_DEVICE_EXTENSION deviceExtension
1312 );
1313
1314 extern ULONG NTAPI
1315 UniataFindBusMasterController(
1316 IN PVOID HwDeviceExtension,
1317 IN PVOID Context,
1318 IN PVOID BusInformation,
1319 IN PCHAR ArgumentString,
1320 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1321 OUT PBOOLEAN Again
1322 );
1323
1324 extern ULONG NTAPI
1325 UniataFindFakeBusMasterController(
1326 IN PVOID HwDeviceExtension,
1327 IN PVOID Context,
1328 IN PVOID BusInformation,
1329 IN PCHAR ArgumentString,
1330 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1331 OUT PBOOLEAN Again
1332 );
1333
1334 extern NTSTATUS
1335 NTAPI
1336 UniataConnectIntr2(
1337 IN PVOID HwDeviceExtension
1338 );
1339
1340 extern NTSTATUS
1341 NTAPI
1342 UniataDisconnectIntr2(
1343 IN PVOID HwDeviceExtension
1344 );
1345
1346 extern ULONG
1347 NTAPI
1348 ScsiPortGetBusDataByOffset(
1349 IN PVOID HwDeviceExtension,
1350 IN BUS_DATA_TYPE BusDataType,
1351 IN ULONG BusNumber,
1352 IN ULONG SlotNumber,
1353 IN PVOID Buffer,
1354 IN ULONG Offset,
1355 IN ULONG Length
1356 );
1357
1358 #define PCIBUSNUM_NOT_SPECIFIED (0xffffffffL)
1359 #define PCISLOTNUM_NOT_SPECIFIED (0xffffffffL)
1360
1361 extern ULONG
1362 NTAPI
1363 AtapiFindListedDev(
1364 PBUSMASTER_CONTROLLER_INFORMATION BusMasterAdapters,
1365 ULONG lim,
1366 IN PVOID HwDeviceExtension,
1367 IN ULONG BusNumber,
1368 IN ULONG SlotNumber,
1369 OUT PCI_SLOT_NUMBER* _slotData // optional
1370 );
1371
1372 extern ULONG
1373 NTAPI
1374 AtapiFindDev(
1375 IN PVOID HwDeviceExtension,
1376 IN BUS_DATA_TYPE BusDataType,
1377 IN ULONG BusNumber,
1378 IN ULONG SlotNumber,
1379 IN ULONG dev_id,
1380 IN ULONG RevID
1381 );
1382
1383 extern VOID
1384 NTAPI
1385 AtapiDmaAlloc(
1386 IN PVOID HwDeviceExtension,
1387 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1388 IN ULONG lChannel // logical channel,
1389 );
1390
1391 extern BOOLEAN
1392 NTAPI
1393 AtapiDmaSetup(
1394 IN PVOID HwDeviceExtension,
1395 IN ULONG DeviceNumber,
1396 IN ULONG lChannel, // logical channel,
1397 IN PSCSI_REQUEST_BLOCK Srb,
1398 IN PUCHAR data,
1399 IN ULONG count
1400 );
1401
1402 extern BOOLEAN
1403 NTAPI
1404 AtapiDmaPioSync(
1405 PVOID HwDeviceExtension,
1406 PSCSI_REQUEST_BLOCK Srb,
1407 PUCHAR data,
1408 ULONG count
1409 );
1410
1411 extern BOOLEAN
1412 NTAPI
1413 AtapiDmaDBSync(
1414 PHW_CHANNEL chan,
1415 PSCSI_REQUEST_BLOCK Srb
1416 );
1417
1418 extern VOID
1419 NTAPI
1420 AtapiDmaStart(
1421 IN PVOID HwDeviceExtension,
1422 IN ULONG DeviceNumber,
1423 IN ULONG lChannel, // logical channel,
1424 IN PSCSI_REQUEST_BLOCK Srb
1425 );
1426
1427 extern UCHAR
1428 NTAPI
1429 AtapiDmaDone(
1430 IN PVOID HwDeviceExtension,
1431 IN ULONG DeviceNumber,
1432 IN ULONG lChannel, // logical channel,
1433 IN PSCSI_REQUEST_BLOCK Srb
1434 );
1435
1436 extern VOID
1437 NTAPI
1438 AtapiDmaReinit(
1439 IN PHW_DEVICE_EXTENSION deviceExtension,
1440 IN PHW_LU_EXTENSION LunExt,
1441 IN PATA_REQ AtaReq
1442 );
1443
1444 extern VOID
1445 NTAPI
1446 AtapiDmaInit__(
1447 IN PHW_DEVICE_EXTENSION deviceExtension,
1448 IN PHW_LU_EXTENSION LunExt
1449 );
1450
1451 extern VOID
1452 NTAPI
1453 AtapiDmaInit(
1454 IN PVOID HwDeviceExtension,
1455 IN ULONG DeviceNumber,
1456 IN ULONG lChannel, // logical channel,
1457 // is always 0 except simplex-only and multi-channel controllers
1458 IN SCHAR apiomode,
1459 IN SCHAR wdmamode,
1460 IN SCHAR udmamode
1461 );
1462
1463 extern BOOLEAN NTAPI
1464 AtapiInterrupt2(
1465 IN PKINTERRUPT Interrupt,
1466 IN PVOID HwDeviceExtension
1467 );
1468
1469 extern PDRIVER_OBJECT SavedDriverObject;
1470
1471 extern BOOLEAN
1472 NTAPI
1473 UniataChipDetectChannels(
1474 IN PVOID HwDeviceExtension,
1475 IN PPCI_COMMON_CONFIG pciData, // optional
1476 IN ULONG DeviceNumber,
1477 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo
1478 );
1479
1480 extern NTSTATUS
1481 NTAPI
1482 UniataChipDetect(
1483 IN PVOID HwDeviceExtension,
1484 IN PPCI_COMMON_CONFIG pciData, // optional
1485 IN ULONG DeviceNumber,
1486 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1487 IN BOOLEAN* simplexOnly
1488 );
1489
1490 extern BOOLEAN
1491 NTAPI
1492 AtapiChipInit(
1493 IN PVOID HwDeviceExtension,
1494 IN ULONG DeviceNumber,
1495 IN ULONG c
1496 );
1497
1498 extern ULONG
1499 NTAPI
1500 AtapiGetIoRange(
1501 IN PVOID HwDeviceExtension,
1502 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1503 IN PPCI_COMMON_CONFIG pciData,
1504 IN ULONG SystemIoBusNumber,
1505 IN ULONG rid,
1506 IN ULONG offset,
1507 IN ULONG length //range id
1508 );
1509
1510 /****************** 1 *****************/
1511 #define GetPciConfig1(offs, op) { \
1512 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1513 PCIConfiguration, \
1514 SystemIoBusNumber, \
1515 slotNumber, \
1516 &op, \
1517 offs, \
1518 1); \
1519 }
1520
1521 #define SetPciConfig1(offs, op) { \
1522 UCHAR _a = op; \
1523 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1524 PCIConfiguration, \
1525 SystemIoBusNumber, \
1526 slotNumber, \
1527 &_a, \
1528 offs, \
1529 1); \
1530 }
1531
1532 #define ChangePciConfig1(offs, _op) { \
1533 UCHAR a = 0; \
1534 GetPciConfig1(offs, a); \
1535 a = (UCHAR)(_op); \
1536 SetPciConfig1(offs, a); \
1537 }
1538
1539 /****************** 2 *****************/
1540 #define GetPciConfig2(offs, op) { \
1541 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1542 PCIConfiguration, \
1543 SystemIoBusNumber, \
1544 slotNumber, \
1545 &op, \
1546 offs, \
1547 2); \
1548 }
1549
1550 #define SetPciConfig2(offs, op) { \
1551 USHORT _a = op; \
1552 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1553 PCIConfiguration, \
1554 SystemIoBusNumber, \
1555 slotNumber, \
1556 &_a, \
1557 offs, \
1558 2); \
1559 }
1560
1561 #define ChangePciConfig2(offs, _op) { \
1562 USHORT a = 0; \
1563 GetPciConfig2(offs, a); \
1564 a = (USHORT)(_op); \
1565 SetPciConfig2(offs, a); \
1566 }
1567
1568 /****************** 4 *****************/
1569 #define GetPciConfig4(offs, op) { \
1570 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1571 PCIConfiguration, \
1572 SystemIoBusNumber, \
1573 slotNumber, \
1574 &op, \
1575 offs, \
1576 4); \
1577 }
1578
1579 #define SetPciConfig4(offs, op) { \
1580 ULONG _a = op; \
1581 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1582 PCIConfiguration, \
1583 SystemIoBusNumber, \
1584 slotNumber, \
1585 &_a, \
1586 offs, \
1587 4); \
1588 }
1589
1590 #define ChangePciConfig4(offs, _op) { \
1591 ULONG a = 0; \
1592 GetPciConfig4(offs, a); \
1593 a = _op; \
1594 SetPciConfig4(offs, a); \
1595 }
1596
1597 #define DMA_MODE_NONE 0x00
1598 #define DMA_MODE_BM 0x01
1599 #define DMA_MODE_AHCI 0x02
1600
1601 #ifndef GetDmaStatus
1602 #define GetDmaStatus(de, c) \
1603 (((de)->BusMaster == DMA_MODE_BM) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)
1604 #endif //GetDmaStatus
1605
1606 #ifdef USE_OWN_DMA
1607 #define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1608 AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);
1609 #else
1610 #define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1611 (ScsiPortConvertPhysicalAddressToUlong/*(ULONG)ScsiPortGetVirtualAddress*/(/*hwde,*/ \
1612 ScsiPortGetPhysicalAddress(hwde, srb, phaddr, plen)))
1613 #endif //USE_OWN_DMA
1614
1615 VOID
1616 DDKFASTAPI
1617 AtapiWritePort4(
1618 IN PHW_CHANNEL chan,
1619 IN ULONGIO_PTR port,
1620 IN ULONG data
1621 );
1622
1623 VOID
1624 DDKFASTAPI
1625 AtapiWritePort2(
1626 IN PHW_CHANNEL chan,
1627 IN ULONGIO_PTR port,
1628 IN USHORT data
1629 );
1630
1631 VOID
1632 DDKFASTAPI
1633 AtapiWritePort1(
1634 IN PHW_CHANNEL chan,
1635 IN ULONGIO_PTR port,
1636 IN UCHAR data
1637 );
1638
1639 VOID
1640 DDKFASTAPI
1641 AtapiWritePortEx4(
1642 IN PHW_CHANNEL chan,
1643 IN ULONGIO_PTR port,
1644 IN ULONG offs,
1645 IN ULONG data
1646 );
1647
1648 VOID
1649 DDKFASTAPI
1650 AtapiWritePortEx1(
1651 IN PHW_CHANNEL chan,
1652 IN ULONGIO_PTR port,
1653 IN ULONG offs,
1654 IN UCHAR data
1655 );
1656
1657 ULONG
1658 DDKFASTAPI
1659 AtapiReadPort4(
1660 IN PHW_CHANNEL chan,
1661 IN ULONGIO_PTR port
1662 );
1663
1664 USHORT
1665 DDKFASTAPI
1666 AtapiReadPort2(
1667 IN PHW_CHANNEL chan,
1668 IN ULONGIO_PTR port
1669 );
1670
1671 UCHAR
1672 DDKFASTAPI
1673 AtapiReadPort1(
1674 IN PHW_CHANNEL chan,
1675 IN ULONGIO_PTR port
1676 );
1677
1678 ULONG
1679 DDKFASTAPI
1680 AtapiReadPortEx4(
1681 IN PHW_CHANNEL chan,
1682 IN ULONGIO_PTR port,
1683 IN ULONG offs
1684 );
1685
1686 UCHAR
1687 DDKFASTAPI
1688 AtapiReadPortEx1(
1689 IN PHW_CHANNEL chan,
1690 IN ULONGIO_PTR port,
1691 IN ULONG offs
1692 );
1693
1694 VOID
1695 DDKFASTAPI
1696 AtapiWriteBuffer4(
1697 IN PHW_CHANNEL chan,
1698 IN ULONGIO_PTR _port,
1699 IN PVOID Buffer,
1700 IN ULONG Count,
1701 IN ULONG Timing
1702 );
1703
1704 VOID
1705 DDKFASTAPI
1706 AtapiWriteBuffer2(
1707 IN PHW_CHANNEL chan,
1708 IN ULONGIO_PTR _port,
1709 IN PVOID Buffer,
1710 IN ULONG Count,
1711 IN ULONG Timing
1712 );
1713
1714 VOID
1715 DDKFASTAPI
1716 AtapiReadBuffer4(
1717 IN PHW_CHANNEL chan,
1718 IN ULONGIO_PTR _port,
1719 IN PVOID Buffer,
1720 IN ULONG Count,
1721 IN ULONG Timing
1722 );
1723
1724 VOID
1725 DDKFASTAPI
1726 AtapiReadBuffer2(
1727 IN PHW_CHANNEL chan,
1728 IN ULONGIO_PTR _port,
1729 IN PVOID Buffer,
1730 IN ULONG Count,
1731 IN ULONG Timing
1732 );
1733
1734 /*#define GET_CHANNEL(Srb) (Srb->TargetId >> 1)
1735 #define GET_LDEV(Srb) (Srb->TargetId)
1736 #define GET_LDEV2(P, T, L) (T)*/
1737
1738 #define GET_CHANNEL(Srb) (Srb->PathId)
1739 //#define GET_LDEV(Srb) (Srb->TargetId | (Srb->PathId << 1))
1740 //#define GET_LDEV2(P, T, L) (T | ((P)<<1))
1741 #define GET_CDEV(Srb) (Srb->TargetId)
1742
1743 VOID
1744 NTAPI
1745 AtapiSetupLunPtrs(
1746 IN PHW_CHANNEL chan,
1747 IN PHW_DEVICE_EXTENSION deviceExtension,
1748 IN ULONG c
1749 );
1750 /*
1751 #define AtapiSetupLunPtrs(chan, deviceExtension, c) \
1752 { \
1753 chan->DeviceExtension = deviceExtension; \
1754 chan->lChannel = c; \
1755 chan->lun[0] = &(deviceExtension->lun[c*2+0]); \
1756 chan->lun[1] = &(deviceExtension->lun[c*2+1]); \
1757 chan->AltRegMap = deviceExtension->AltRegMap; \
1758 chan->NextDpcChan = -1; \
1759 chan->lun[0]->DeviceExtension = deviceExtension; \
1760 chan->lun[1]->DeviceExtension = deviceExtension; \
1761 }
1762 */
1763 BOOLEAN
1764 NTAPI
1765 AtapiReadChipConfig(
1766 IN PVOID HwDeviceExtension,
1767 IN ULONG DeviceNumber,
1768 IN ULONG channel // physical channel
1769 );
1770
1771 VOID
1772 NTAPI
1773 UniataForgetDevice(
1774 PHW_LU_EXTENSION LunExt
1775 );
1776
1777 extern ULONG SkipRaids;
1778 extern ULONG ForceSimplex;
1779 extern BOOLEAN g_opt_AtapiDmaRawRead;
1780 extern BOOLEAN hasPCI;
1781
1782 extern BOOLEAN InDriverEntry;
1783
1784 extern BOOLEAN g_opt_Verbose;
1785 extern ULONG g_opt_VirtualMachine;
1786
1787 #define VM_AUTO 0x00
1788 #define VM_NONE 0x01
1789 #define VM_VBOX 0x02
1790 #define VM_VMWARE 0x03
1791 #define VM_QEMU 0x04
1792
1793 #define VM_MAX_KNOWN VM_QEMU
1794
1795 extern BOOLEAN WinVer_WDM_Model;
1796
1797 #endif //__IDE_BUSMASTER_H__
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