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[reactos.git] / reactos / drivers / storage / ide / uniata / bsmaster.h
1 /*++
2
3 Copyright (c) 2002-2012 Alexandr A. Telyatnikov (Alter)
4
5 Module Name:
6 bsmaster.h
7
8 Abstract:
9 This file contains DMA/UltraDMA and IDE BusMastering related definitions,
10 internal structures and useful macros
11
12 Author:
13 Alexander A. Telyatnikov (Alter)
14
15 Environment:
16 kernel mode only
17
18 Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31 Revision History:
32
33 Code was created by
34 Alter, Copyright (c) 2002-2008
35
36 Some definitions were taken from FreeBSD 4.3-4.6 ATA driver by
37 Søren Schmidt, Copyright (c) 1998,1999,2000,2001
38
39 --*/
40
41 #ifndef __IDE_BUSMASTER_H__
42 #define __IDE_BUSMASTER_H__
43
44 #include "config.h"
45
46 #include "tools.h"
47
48 //
49 //
50 //
51 #define ATA_IDLE 0x0
52 #define ATA_IMMEDIATE 0x1
53 #define ATA_WAIT_INTR 0x2
54 #define ATA_WAIT_READY 0x3
55 #define ATA_ACTIVE 0x4
56 #define ATA_ACTIVE_ATA 0x5
57 #define ATA_ACTIVE_ATAPI 0x6
58 #define ATA_REINITING 0x7
59 #define ATA_WAIT_BASE_READY 0x8
60 #define ATA_WAIT_IDLE 0x9
61
62
63 #include "bm_devs.h"
64
65 #include "uata_ctl.h"
66
67 #define MAX_RETRIES 6
68 #define RETRY_UDMA2 1
69 #define RETRY_WDMA 2
70 #define RETRY_PIO 3
71
72
73 #define IO_WD1 0x1F0 /* Primary Fixed Disk Controller */
74 #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */
75 #define IP_PC98_BANK 0x432
76
77 #define PCI_ADDRESS_IOMASK 0xfffffff0
78
79 #define ATA_BM_OFFSET1 0x08
80 #define ATA_IOSIZE 0x08
81 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */
82 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
83 #define ATA_ALTIOSIZE 0x01 /* alternate registers size */
84 #define ATA_BMIOSIZE 0x20
85 #define ATA_PC98_BANKIOSIZE 0x01
86 //#define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
87 // Hitachi 1 Tb HDD didn't allow LBA28 with BCount > 1 beyond this LBA
88 #define ATA_MAX_IOLBA28 DEF_U64(0x0fffff80)
89 #define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
90
91 #define ATA_DMA_ENTRIES 256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
92 #define ATA_DMA_EOT 0x80000000
93
94 #define DEV_BSIZE 512
95
96 #define ATAPI_MAGIC_LSB 0x14
97 #define ATAPI_MAGIC_MSB 0xeb
98
99 #define AHCI_MAX_PORT 32
100
101 #define SATA_MAX_PM_UNITS 16
102
103 typedef struct _BUSMASTER_CTX {
104 PBUSMASTER_CONTROLLER_INFORMATION* BMListPtr;
105 ULONG* BMListLen;
106 } BUSMASTER_CTX, *PBUSMASTER_CTX;
107
108 #define PCI_DEV_CLASS_STORAGE 0x01
109
110 #define PCI_DEV_SUBCLASS_IDE 0x01
111 #define PCI_DEV_SUBCLASS_RAID 0x04
112 #define PCI_DEV_SUBCLASS_ATA 0x05
113 #define PCI_DEV_SUBCLASS_SATA 0x06
114
115 #define PCI_DEV_PROGIF_AHCI_1_0 0x01
116
117 /* structure for holding DMA address data */
118 typedef struct BM_DMA_ENTRY {
119 ULONG base;
120 ULONG count;
121 } BM_DMA_ENTRY, *PBM_DMA_ENTRY;
122
123 typedef struct _IDE_BUSMASTER_REGISTERS {
124 UCHAR Command;
125 UCHAR DeviceSpecific0;
126 UCHAR Status;
127 UCHAR DeviceSpecific1;
128 ULONG PRD_Table;
129 } IDE_BUSMASTER_REGISTERS, *PIDE_BUSMASTER_REGISTERS;
130
131 #define BM_STATUS_ACTIVE 0x01
132 #define BM_STATUS_ERR 0x02
133 #define BM_STATUS_INTR 0x04
134 #define BM_STATUS_MASK 0x07
135 #define BM_STATUS_DRIVE_0_DMA 0x20
136 #define BM_STATUS_DRIVE_1_DMA 0x40
137 #define BM_STATUS_SIMPLEX_ONLY 0x80
138
139 #define BM_COMMAND_START_STOP 0x01
140 /*#define BM_COMMAND_WRITE 0x08
141 #define BM_COMMAND_READ 0x00*/
142 #define BM_COMMAND_WRITE 0x00
143 #define BM_COMMAND_READ 0x08
144
145 #define BM_DS0_SII_DMA_ENABLE (1 << 0) /* DMA run switch */
146 #define BM_DS0_SII_IRQ (1 << 3) /* ??? */
147 #define BM_DS0_SII_DMA_SATA_IRQ (1 << 4) /* OR of all SATA IRQs */
148 #define BM_DS0_SII_DMA_ERROR (1 << 17) /* PCI bus error */
149 #define BM_DS0_SII_DMA_COMPLETE (1 << 18) /* cmd complete / IRQ pending */
150
151
152 #define IDX_BM_IO (IDX_IO2_o+IDX_IO2_o_SZ)
153 //#define IDX_BM_IO_SZ sizeof(IDE_BUSMASTER_REGISTERS)
154 #define IDX_BM_IO_SZ 5
155
156 #define IDX_BM_Command (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)
157 #define IDX_BM_DeviceSpecific0 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)
158 #define IDX_BM_Status (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)
159 #define IDX_BM_DeviceSpecific1 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)
160 #define IDX_BM_PRD_Table (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)
161
162 typedef struct _IDE_AHCI_REGISTERS {
163 // HBA Capabilities
164 struct {
165 ULONG NOP:5; // number of ports
166 ULONG SXS:1; // Supports External SATA
167 ULONG EMS:1; // Enclosure Management Supported
168 ULONG CCCS:1; // Command Completion Coalescing Supported
169 ULONG NCS:5; // number of command slots
170 ULONG PSC:1; // partial state capable
171 ULONG SSC:1; // slumber state capable
172 ULONG PMD:1; // PIO multiple DRQ block
173 ULONG FBSS:1; // FIS-based Switching Supported
174
175 ULONG SPM:1; // port multiplier
176 ULONG SAM:1; // AHCI mode only
177 ULONG SNZO:1; // non-zero DMA offset
178 ULONG ISS:4; // interface speed
179 ULONG SCLO:1; // command list override
180 ULONG SAL:1; // activity LED
181 ULONG SALP:1; // aggressive link power management
182 ULONG SSS:1; // staggered spin-up
183 ULONG SIS:1; // interlock switch
184 ULONG SSNTF:1; // Supports SNotification Register
185 ULONG SNCQ:1; // native command queue
186 ULONG S64A:1; // 64bit addr
187 } CAP;
188
189 #define AHCI_CAP_NOP_MASK 0x0000001f
190 #define AHCI_CAP_CCC 0x00000080
191 #define AHCI_CAP_NCS_MASK 0x00001f00
192 #define AHCI_CAP_PMD 0x00008000
193 #define AHCI_CAP_SPM 0x00020000
194 #define AHCI_CAP_SAM 0x00040000
195 #define AHCI_CAP_ISS_MASK 0x00f00000
196 #define AHCI_CAP_SCLO 0x01000000
197 #define AHCI_CAP_SNTF 0x20000000
198 #define AHCI_CAP_NCQ 0x40000000
199 #define AHCI_CAP_S64A 0x80000000
200
201 // Global HBA Control
202 struct {
203 ULONG HR:1; // HBA Reset
204 ULONG IE:1; // interrupt enable
205 ULONG Reserved2_30:1;
206 ULONG AE:1; // AHCI enable
207 } GHC;
208
209 #define AHCI_GHC 0x04
210 #define AHCI_GHC_HR 0x00000001
211 #define AHCI_GHC_IE 0x00000002
212 #define AHCI_GHC_AE 0x80000000
213
214 // Interrupt status (bit mask)
215 ULONG IS; // 0x08
216 // Ports implemented (bit mask)
217 ULONG PI; // 0x0c
218 // AHCI Version
219 ULONG VS; // 0x10
220
221 ULONG CCC_CTL; // 0x14
222 ULONG CCC_PORTS; // 0x18
223 ULONG EM_LOC; // 0x1c
224 ULONG EM_CTL; // 0x20
225
226 // Extended HBA Capabilities
227 struct { // 0x24
228 ULONG BOH:1; // BIOS/OS Handoff
229 ULONG NVMP:1; // NVMHCI Present
230 ULONG APST:1; // Automatic Partial to Slumber Transitions
231 ULONG Reserved:29;
232 } CAP2;
233
234 #define AHCI_CAP2_BOH 0x00000001
235 #define AHCI_CAP2_NVMP 0x00000002
236 #define AHCI_CAP2_APST 0x00000004
237
238 // BIOS/OS Handoff Control and Status
239 struct { // 0x28
240 ULONG BB:1; // BIOS Busy
241 ULONG OOC:1; // OS Ownership Change
242 ULONG SOOE:1; // SMI on OS Ownership Change Enable
243 ULONG OOS:1; // OS Owned Semaphore
244 ULONG BOS:1; // BIOS Owned Semaphore
245 ULONG Reserved:27;
246 } BOHC;
247
248 UCHAR Reserved2[0x74];
249
250 UCHAR VendorSpec[0x60];
251 } IDE_AHCI_REGISTERS, *PIDE_AHCI_REGISTERS;
252
253 #define IDX_AHCI_CAP (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))
254 #define IDX_AHCI_GHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))
255 #define IDX_AHCI_IS (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))
256 #define IDX_AHCI_VS (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))
257 #define IDX_AHCI_PI (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))
258 #define IDX_AHCI_CAP2 (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP2))
259 #define IDX_AHCI_BOHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, BOHC))
260
261
262 typedef union _SATA_SSTATUS_REG {
263
264 struct {
265 ULONG DET:4; // Device Detection
266
267 #define SStatus_DET_NoDev 0x00
268 #define SStatus_DET_Dev_NoPhy 0x01
269 #define SStatus_DET_Dev_Ok 0x03
270 #define SStatus_DET_Offline 0x04
271
272 ULONG SPD:4; // Current Interface Speed
273
274 #define SStatus_SPD_NoDev 0x00
275 #define SStatus_SPD_Gen1 0x01
276 #define SStatus_SPD_Gen2 0x02
277 #define SStatus_SPD_Gen3 0x03
278
279 ULONG IPM:4; // Interface Power Management
280
281 #define SStatus_IPM_NoDev 0x00
282 #define SStatus_IPM_Active 0x01
283 #define SStatus_IPM_Partial 0x02
284 #define SStatus_IPM_Slumber 0x06
285
286 ULONG Reserved:20;
287 };
288 ULONG Reg;
289
290 } SATA_SSTATUS_REG, *PSATA_SSTATUS_REG;
291
292
293 typedef union _SATA_SCONTROL_REG {
294
295 struct {
296 ULONG DET:4; // Device Detection Init
297
298 #define SControl_DET_DoNothing 0x00
299 #define SControl_DET_Idle 0x00
300 #define SControl_DET_Init 0x01
301 #define SControl_DET_Disable 0x04
302
303 ULONG SPD:4; // Speed Allowed
304
305 #define SControl_SPD_NoRestrict 0x00
306 #define SControl_SPD_LimGen1 0x01
307 #define SControl_SPD_LimGen2 0x02
308 #define SControl_SPD_LimGen3 0x03
309
310 ULONG IPM:4; // Interface Power Management Transitions Allowed
311
312 #define SControl_IPM_NoRestrict 0x00
313 #define SControl_IPM_NoPartial 0x01
314 #define SControl_IPM_NoSlumber 0x02
315 #define SControl_IPM_NoPartialSlumber 0x03
316
317 ULONG SPM:4; // Select Power Management, unused by AHCI
318 ULONG PMP:4; // Port Multiplier Port, unused by AHCI
319 ULONG Reserved:12;
320 };
321 ULONG Reg;
322
323 } SATA_SCONTROL_REG, *PSATA_SCONTROL_REG;
324
325
326 typedef union _SATA_SERROR_REG {
327
328 struct {
329 struct {
330 UCHAR I:1; // Recovered Data Integrity Error
331 UCHAR M:1; // Recovered Communications Error
332 UCHAR Reserved_2_7:6;
333
334 UCHAR T:1; // Transient Data Integrity Error
335 UCHAR C:1; // Persistent Communication or Data Integrity Error
336 UCHAR P:1; // Protocol Error
337 UCHAR E:1; // Internal Error
338 UCHAR Reserved_12_15:4;
339 } ERR;
340
341 struct {
342 UCHAR N:1; // PhyRdy Change, PIS.PRCS
343 UCHAR I:1; // Phy Internal Error
344 UCHAR W:1; // Comm Wake
345 UCHAR B:1; // 10B to 8B Decode Error
346 UCHAR D:1; // Disparity Error, not used by AHCI
347 UCHAR C:1; // CRC Error
348 UCHAR H:1; // Handshake Error
349 UCHAR S:1; // Link Sequence Error
350
351 UCHAR T:1; // Transport state transition error
352 UCHAR F:1; // Unknown FIS Type
353 UCHAR X:1; // Exchanged
354 UCHAR Reserved_27_31:5;
355 } DIAG;
356 };
357 ULONG Reg;
358
359 } SATA_SERROR_REG, *PSATA_SERROR_REG;
360
361
362 typedef struct _IDE_SATA_REGISTERS {
363 union {
364 SATA_SSTATUS_REG SStatus;
365 ULONG SStatus_Reg;
366 };
367 union {
368 SATA_SERROR_REG SError;
369 ULONG SError_Reg;
370 };
371 union {
372 SATA_SCONTROL_REG SControl;
373 ULONG SControl_Reg;
374 };
375
376 // SATA 1.2
377
378 ULONG SActive;
379 union {
380 ULONG Reg;
381 struct {
382 USHORT PMN; // PM Notify, bitmask
383 USHORT Reserved;
384 };
385 } SNTF;
386 ULONG SReserved[11];
387 } IDE_SATA_REGISTERS, *PIDE_SATA_REGISTERS;
388
389 #define IDX_SATA_IO (IDX_BM_IO+IDX_BM_IO_SZ)
390 //#define IDX_SATA_IO_SZ sizeof(IDE_SATA_REGISTERS)
391 #define IDX_SATA_IO_SZ 5
392
393 #define IDX_SATA_SStatus (0+IDX_SATA_IO)
394 #define IDX_SATA_SError (1+IDX_SATA_IO)
395 #define IDX_SATA_SControl (2+IDX_SATA_IO)
396 #define IDX_SATA_SActive (3+IDX_SATA_IO)
397 #define IDX_SATA_SNTF_PMN (4+IDX_SATA_IO)
398
399 #define IDX_INDEXED_IO (IDX_SATA_IO+IDX_SATA_IO_SZ)
400 #define IDX_INDEXED_IO_SZ 2
401
402 #define IDX_INDEXED_ADDR (0+IDX_INDEXED_IO)
403 #define IDX_INDEXED_DATA (1+IDX_INDEXED_IO)
404
405 #define IDX_MAX_REG (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)
406
407
408 typedef union _AHCI_IS_REG {
409 struct {
410 ULONG DHRS:1;// Device to Host Register FIS Interrupt
411 ULONG PSS:1; // PIO Setup FIS Interrupt
412 ULONG DSS:1; // DMA Setup FIS Interrupt
413 ULONG SDBS:1;// Set Device Bits Interrupt
414 ULONG UFS:1; // Unknown FIS Interrupt
415 ULONG DPS:1; // Descriptor Processed
416 ULONG PCS:1; // Port Connect Change Status
417 ULONG DMPS:1;// Device Mechanical Presence Status
418
419 ULONG Reserved_8_21:14;
420 ULONG PRCS:1;// PhyRdy Change Status
421 ULONG IPMS:1;// Incorrect Port Multiplier Status
422
423 ULONG OFS:1; // Overflow Status
424 ULONG Reserved_25:1;
425 ULONG INFS:1;// Interface Non-fatal Error Status
426 ULONG IFS:1; // Interface Fatal Error Status
427 ULONG HBDS:1;// Host Bus Data Error Status
428 ULONG HBFS:1;// Host Bus Fatal Error Status
429 ULONG TFES:1;// Task File Error Status
430 ULONG CPDS:1;// Cold Port Detect Status
431 };
432 ULONG Reg;
433 } AHCI_IS_REG, *PAHCI_IS_REG;
434
435 #define ATA_AHCI_P_IX_DHR 0x00000001
436 #define ATA_AHCI_P_IX_PS 0x00000002
437 #define ATA_AHCI_P_IX_DS 0x00000004
438 #define ATA_AHCI_P_IX_SDB 0x00000008
439 #define ATA_AHCI_P_IX_UF 0x00000010
440 #define ATA_AHCI_P_IX_DP 0x00000020
441 #define ATA_AHCI_P_IX_PC 0x00000040
442 #define ATA_AHCI_P_IX_DI 0x00000080
443
444 #define ATA_AHCI_P_IX_PRC 0x00400000
445 #define ATA_AHCI_P_IX_IPM 0x00800000
446 #define ATA_AHCI_P_IX_OF 0x01000000
447 #define ATA_AHCI_P_IX_INF 0x04000000
448 #define ATA_AHCI_P_IX_IF 0x08000000
449 #define ATA_AHCI_P_IX_HBD 0x10000000
450 #define ATA_AHCI_P_IX_HBF 0x20000000
451 #define ATA_AHCI_P_IX_TFE 0x40000000
452 #define ATA_AHCI_P_IX_CPD 0x80000000
453
454 #define AHCI_CLB_ALIGNEMENT_MASK ((ULONGLONG)(1024-1))
455 #define AHCI_FIS_ALIGNEMENT_MASK ((ULONGLONG)(256-1))
456 #define AHCI_CMD_ALIGNEMENT_MASK ((ULONGLONG)(128-1))
457
458 typedef struct _IDE_AHCI_PORT_REGISTERS {
459 union {
460 struct {
461 ULONG CLB; // command list base address, 1K-aligned
462 ULONG CLBU; // command list base address (upper 32bits)
463 };
464 ULONGLONG CLB64;
465 }; // 0x100 + 0x80*c + 0x0000
466
467 union {
468 struct {
469 ULONG FB; // FIS base address
470 ULONG FBU; // FIS base address (upper 32bits)
471 };
472 ULONGLONG FB64;
473 }; // 0x100 + 0x80*c + 0x0008
474
475 union {
476 ULONG IS_Reg; // interrupt status
477 AHCI_IS_REG IS;
478 }; // 0x100 + 0x80*c + 0x0010
479
480 union {
481 ULONG Reg; // interrupt enable
482 struct {
483 ULONG DHRE:1;// Device to Host Register FIS Interrupt Enable
484 ULONG PSE:1; // PIO Setup FIS Interrupt Enable
485 ULONG DSE:1; // DMA Setup FIS Interrupt Enable
486 ULONG SDBE:1;// Set Device Bits FIS Interrupt Enable
487 ULONG UFE:1; // Unknown FIS Interrupt Enable
488 ULONG DPE:1; // Descriptor Processed Interrupt Enable
489 ULONG PCE:1; // Port Change Interrupt Enable
490 ULONG DPME:1;// Device Mechanical Presence Enable
491
492 ULONG Reserved_8_21:14;
493 ULONG PRCE:1;// PhyRdy Change Interrupt Enable
494 ULONG IPME:1;// Incorrect Port Multiplier Enable
495 ULONG OFE:1; // Overflow Enable
496 ULONG Reserved_25:1;
497 ULONG INFE:1;// Interface Non-fatal Error Enable
498 ULONG IFE:1; // Interface Fatal Error Enable
499 ULONG HBDE:1;// Host Bus Data Error Enable
500 ULONG HBFE:1;// Host Bus Fatal Error Enable
501 ULONG TFEE:1;// Task File Error Enable
502 ULONG CPDE:1;// Cold Port Detect Enable
503 };
504 } IE; // 0x100 + 0x80*c + 0x0014
505
506 union {
507 ULONG Reg; // command register
508 struct {
509
510 ULONG ST:1; // Start
511 ULONG SUD:1; // Spin-Up Device
512 ULONG POD:1; // Power On Device
513 ULONG CLO:1; // Command List Override
514 ULONG FRE:1; // FIS Receive Enable
515 ULONG Reserved_5_7:3;
516
517 ULONG CCS:5; // Current Command Slot
518 ULONG MPSS:1;// Mechanical Presence Switch State
519 ULONG FR:1; // FIS Receive Running
520 ULONG CR:1; // Command List Running
521
522 ULONG CPS:1; // Cold Presence State
523 ULONG PMA:1; // Port Multiplier Attached
524 ULONG HPCP:1;// Hot Plug Capable Port
525 ULONG MPSP:1;// Mechanical Presence Switch Attached to Port
526 ULONG CPD:1; // Cold Presence Detection
527 ULONG ESP:1; // External SATA Port
528 ULONG Reserved_22_23:2;
529
530 ULONG ATAPI:1; // Device is ATAPI
531 ULONG DLAE:1;// Drive LED on ATAPI Enable
532 ULONG ALPE:1;// Aggressive Link Power Management Enable
533 ULONG ASP:1; // Aggressive Slumber / Partial
534 ULONG ICC:4; // Interface Communication Control
535
536 #define SATA_CMD_ICC_Idle 0x00
537 #define SATA_CMD_ICC_NoOp 0x00
538 #define SATA_CMD_ICC_Active 0x01
539 #define SATA_CMD_ICC_Partial 0x02
540 #define SATA_CMD_ICC_Slumber 0x06
541 };
542 } CMD; // 0x100 + 0x80*c + 0x0018
543
544 ULONG Reserved;
545
546 union {
547 ULONG Reg; // Task File Data
548 struct {
549 struct {
550 UCHAR ERR:1;
551 UCHAR cs1:2;// command-specific
552 UCHAR DRQ:1;
553 UCHAR cs2:3;// command-specific
554 UCHAR BSY:1;
555 } STS;
556 UCHAR ERR; // Contains the latest copy of the task file error register.
557 UCHAR Reserved[2];
558 };
559 } TFD; // 0x100 + 0x80*c + 0x0020
560
561 union {
562 ULONG Reg; // signature
563 struct {
564 UCHAR SectorCount;
565 UCHAR LbaLow; // IDX_IO1_i_BlockNumber
566 UCHAR LbaMid; // IDX_IO1_i_CylinderLow
567 UCHAR LbaHigh; // IDX_IO1_i_CylinderHigh
568 };
569 } SIG; // 0x100 + 0x80*c + 0x0024
570 union {
571 ULONG SStatus; // SCR0
572 SATA_SSTATUS_REG SSTS;
573 }; // 0x100 + 0x80*c + 0x0028
574 union {
575 ULONG SControl; // SCR2
576 SATA_SCONTROL_REG SCTL;
577 }; // 0x100 + 0x80*c + 0x002c
578 union {
579 ULONG SError; // SCR1
580 SATA_SERROR_REG SERR;
581 }; // 0x100 + 0x80*c + 0x0030
582 union {
583 ULONG SACT; // SCR3
584 ULONG SActive; // bitmask
585 }; // 0x100 + 0x80*c + 0x0034
586
587 ULONG CI; // Command issue, bitmask, 0x100 + 0x80*c + 0x0038
588
589 // AHCI 1.1
590 union {
591 ULONG Reg;
592 struct {
593 USHORT PMN; // PM Notify, bitmask
594 USHORT Reserved;
595 };
596 } SNTF; // 0x100 + 0x80*c + 0x003c
597
598 // AHCI 1.2
599 union {
600 ULONG Reg;
601 struct {
602 ULONG EN:1; // Enable
603 ULONG DEC:1; // Device Error Clear
604 ULONG SDE:1; // Single Device Error
605 ULONG Reserved_3_7:5; // Reserved
606 ULONG DEV:4; // Device To Issue
607 ULONG ADO:4; // Active Device Optimization (recommended parallelism)
608 ULONG DWE:4; // Device With Error
609 ULONG Reserved_20_31:12; // Reserved
610 };
611 } FBS; // 0x100 + 0x80*c + 0x0040
612
613 ULONG Reserved_44_7f[11];
614 UCHAR VendorSpec[16];
615
616 } IDE_AHCI_PORT_REGISTERS, *PIDE_AHCI_PORT_REGISTERS;
617
618 #define IDX_AHCI_P_CLB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))
619 #define IDX_AHCI_P_FB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))
620 #define IDX_AHCI_P_IS (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
621 #define IDX_AHCI_P_IE (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))
622 #define IDX_AHCI_P_CI (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
623 #define IDX_AHCI_P_TFD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
624 #define IDX_AHCI_P_SIG (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
625 #define IDX_AHCI_P_CMD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
626 #define IDX_AHCI_P_SStatus (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))
627 #define IDX_AHCI_P_SControl (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))
628 #define IDX_AHCI_P_SError (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))
629 #define IDX_AHCI_P_ACT (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
630
631 #define IDX_AHCI_P_SNTF (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
632
633 // AHCI commands ( -> IDX_AHCI_P_CMD)
634 #define ATA_AHCI_P_CMD_ST 0x00000001
635 #define ATA_AHCI_P_CMD_SUD 0x00000002
636 #define ATA_AHCI_P_CMD_POD 0x00000004
637 #define ATA_AHCI_P_CMD_CLO 0x00000008
638 #define ATA_AHCI_P_CMD_FRE 0x00000010
639 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
640 #define ATA_AHCI_P_CMD_ISS 0x00002000
641 #define ATA_AHCI_P_CMD_FR 0x00004000
642 #define ATA_AHCI_P_CMD_CR 0x00008000
643 #define ATA_AHCI_P_CMD_CPS 0x00010000
644 #define ATA_AHCI_P_CMD_PMA 0x00020000
645 #define ATA_AHCI_P_CMD_HPCP 0x00040000
646 #define ATA_AHCI_P_CMD_ISP 0x00080000
647 #define ATA_AHCI_P_CMD_CPD 0x00100000
648 #define ATA_AHCI_P_CMD_ATAPI 0x01000000
649 #define ATA_AHCI_P_CMD_DLAE 0x02000000
650 #define ATA_AHCI_P_CMD_ALPE 0x04000000
651 #define ATA_AHCI_P_CMD_ASP 0x08000000
652 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
653 #define ATA_AHCI_P_CMD_NOOP 0x00000000
654 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000
655 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000
656 #define ATA_AHCI_P_CMD_SLUMBER 0x60000000
657
658
659 typedef struct _IDE_AHCI_PRD_ENTRY {
660 union {
661 ULONG base;
662 ULONGLONG base64;
663 struct {
664 ULONG DBA;
665 union {
666 ULONG DBAU;
667 ULONG baseu;
668 };
669 };
670 };
671 ULONG Reserved1;
672
673 union {
674 struct {
675 ULONG DBC:22;
676 ULONG Reserved2:9;
677 ULONG I:1;
678 };
679 ULONG DBC_ULONG;
680 };
681
682 } IDE_AHCI_PRD_ENTRY, *PIDE_AHCI_PRD_ENTRY;
683
684 #define ATA_AHCI_DMA_ENTRIES (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */
685 #define ATA_AHCI_MAX_TAGS 32
686
687 #define AHCI_FIS_TYPE_ATA_H2D 0x27
688 #define AHCI_FIS_TYPE_ATA_D2H 0x34
689 #define AHCI_FIS_TYPE_DMA_D2H 0x39
690 #define AHCI_FIS_TYPE_DMA_BiDi 0x41
691 #define AHCI_FIS_TYPE_DATA_BiDi 0x46
692 #define AHCI_FIS_TYPE_BIST_BiDi 0x58
693 #define AHCI_FIS_TYPE_PIO_D2H 0x5f
694 #define AHCI_FIS_TYPE_DEV_BITS_D2H 0xA1
695
696 typedef struct _AHCI_ATA_H2D_FIS {
697 UCHAR FIS_Type; // = 0x27
698 UCHAR Reserved1:7;
699 UCHAR Cmd:1; // update Command register
700 UCHAR Command; // [2]
701 UCHAR Feature; // [3]
702
703 UCHAR BlockNumber; // [4]
704 UCHAR CylinderLow; // [5]
705 UCHAR CylinderHigh; // [6]
706 UCHAR DriveSelect; // [7]
707
708 UCHAR BlockNumberExp; // [8]
709 UCHAR CylinderLowExp; // [9]
710 UCHAR CylinderHighExp; // [10]
711 UCHAR FeatureExp; // [11]
712
713 UCHAR BlockCount; // [12]
714 UCHAR BlockCountExp; // [13]
715 UCHAR Reserved14; // [14]
716 UCHAR Control; // [15]
717
718 } AHCI_ATA_H2D_FIS, *PAHCI_ATA_H2D_FIS;
719
720 #define IDX_AHCI_o_Command (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Command))
721 #define IDX_AHCI_o_Feature (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Feature))
722 #define IDX_AHCI_o_BlockNumber (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumber ))
723 #define IDX_AHCI_o_CylinderLow (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLow ))
724 #define IDX_AHCI_o_CylinderHigh (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHigh))
725 #define IDX_AHCI_o_DriveSelect (FIELD_OFFSET(AHCI_ATA_H2D_FIS, DriveSelect ))
726 #define IDX_AHCI_o_BlockCount (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCount))
727 #define IDX_AHCI_o_Control (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Control))
728 #define IDX_AHCI_o_FeatureExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, FeatureExp))
729 #define IDX_AHCI_o_BlockNumberExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumberExp ))
730 #define IDX_AHCI_o_CylinderLowExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLowExp ))
731 #define IDX_AHCI_o_CylinderHighExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHighExp))
732 #define IDX_AHCI_o_BlockCountExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCountExp))
733
734 #define AHCI_FIS_COMM_PM (0x80 | AHCI_DEV_SEL_PM)
735
736 #define AHCI_DEV_SEL_1 0x00
737 #define AHCI_DEV_SEL_2 0x01
738 #define AHCI_DEV_SEL_PM 0x0f
739
740 /* 128-byte aligned */
741 typedef struct _IDE_AHCI_CMD {
742 UCHAR cfis[64];
743 UCHAR acmd[16];
744 UCHAR Reserved[48];
745 IDE_AHCI_PRD_ENTRY prd_tab[ATA_AHCI_DMA_ENTRIES]; // also 128-byte aligned
746 } IDE_AHCI_CMD, *PIDE_AHCI_CMD;
747
748
749 /* cmd_flags */
750 #define ATA_AHCI_CMD_ATAPI 0x0020
751 #define ATA_AHCI_CMD_WRITE 0x0040
752 #define ATA_AHCI_CMD_PREFETCH 0x0080
753 #define ATA_AHCI_CMD_RESET 0x0100
754 #define ATA_AHCI_CMD_BIST 0x0200
755 #define ATA_AHCI_CMD_CLR_BUSY 0x0400
756
757 /* 128-byte aligned */
758 typedef struct _IDE_AHCI_CMD_LIST {
759 USHORT cmd_flags;
760 USHORT prd_length; /* PRD entries */
761 ULONG bytecount;
762 ULONGLONG cmd_table_phys; /* points to IDE_AHCI_CMD */
763 ULONG Reserved[4];
764 } IDE_AHCI_CMD_LIST, *PIDE_AHCI_CMD_LIST;
765
766 /* 256-byte aligned */
767 typedef struct _IDE_AHCI_RCV_FIS {
768 UCHAR dsfis[28];
769 UCHAR Reserved1[4];
770 UCHAR psfis[20];
771 UCHAR Reserved2[12];
772 UCHAR rfis[20];
773 UCHAR Reserved3[4];
774 UCHAR SDBFIS[8];
775 UCHAR ufis[64];
776 UCHAR Reserved4[96];
777 } IDE_AHCI_RCV_FIS, *PIDE_AHCI_RCV_FIS;
778
779 /* 1K-byte aligned */
780 typedef struct _IDE_AHCI_CHANNEL_CTL_BLOCK {
781 IDE_AHCI_CMD_LIST cmd_list[ATA_AHCI_MAX_TAGS]; // 1K-size (32*32)
782 IDE_AHCI_RCV_FIS rcv_fis;
783 IDE_AHCI_CMD cmd; // for single internal commands w/o associated AtaReq
784 } IDE_AHCI_CHANNEL_CTL_BLOCK, *PIDE_AHCI_CHANNEL_CTL_BLOCK;
785
786
787 #define IsBusMaster(pciData) \
788 ( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/)) == \
789 (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/))
790
791 #define PCI_IDE_PROGIF_NATIVE_1 0x01
792 #define PCI_IDE_PROGIF_NATIVE_2 0x04
793 #define PCI_IDE_PROGIF_NATIVE_ALL 0x05
794
795 #define IsMasterDev(pciData) \
796 ( ((pciData)->ProgIf & 0x80) && \
797 ((pciData)->ProgIf & PCI_IDE_PROGIF_NATIVE_ALL) != PCI_IDE_PROGIF_NATIVE_ALL )
798
799 //#define INT_Q_SIZE 32
800 #define MIN_REQ_TTL 4
801
802 union _ATA_REQ;
803
804 typedef union _ATA_REQ {
805 // ULONG reqId; // serial
806 struct {
807
808 //union {
809
810 struct {
811 union _ATA_REQ* next_req;
812 union _ATA_REQ* prev_req;
813
814 PSCSI_REQUEST_BLOCK Srb; // Current request on controller.
815
816 PUSHORT DataBuffer; // Data buffer pointer.
817 ULONG WordsLeft; // Data words left.
818 ULONG TransferLength; // Originally requested transfer length
819 LONGLONG lba;
820 ULONG WordsTransfered;// Data words already transfered.
821 ULONG bcount;
822
823 UCHAR retry;
824 UCHAR ttl;
825 // UCHAR tag;
826 UCHAR Flags;
827 UCHAR ReqState;
828
829 PSCSI_REQUEST_BLOCK OriginalSrb; // Mechanism Status Srb Data
830
831 ULONG dma_entries;
832 union {
833 // for ATA
834 struct {
835 ULONG dma_base;
836 ULONG dma_baseu;
837 } ata;
838 // for AHCI
839 struct {
840 ULONGLONG ahci_base64;
841 ULONGLONG in_lba;
842 PIDE_AHCI_CMD ahci_cmd_ptr;
843 ULONG in_bcount;
844 ULONG in_status;
845 USHORT io_cmd_flags; // out
846 UCHAR in_error;
847 } ahci;
848 };
849 };
850 //UCHAR padding_128b[128]; // Note: we assume, NT allocates block > 4k as PAGE-aligned
851 //};
852 struct {
853 union {
854 BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
855 IDE_AHCI_CMD ahci_cmd0; // for AHCI, 128-byte aligned
856 };
857 };
858 };
859
860 UCHAR padding_4kb[PAGE_SIZE];
861
862 } ATA_REQ, *PATA_REQ;
863
864 #define REQ_FLAG_FORCE_DOWNRATE 0x01
865 #define REQ_FLAG_DMA_OPERATION 0x02
866 #define REQ_FLAG_REORDERABLE_CMD 0x04
867 #define REQ_FLAG_RW_MASK 0x08
868 #define REQ_FLAG_READ 0x08
869 #define REQ_FLAG_WRITE 0x00
870 #define REQ_FLAG_FORCE_DOWNRATE_LBA48 0x10
871 #define REQ_FLAG_DMA_DBUF 0x20
872 #define REQ_FLAG_DMA_DBUF_PRD 0x40
873 #define REQ_FLAG_LBA48 0x80
874
875 // Request states
876 #define REQ_STATE_NONE 0x00
877 #define REQ_STATE_QUEUED 0x10
878
879 #define REQ_STATE_PREPARE_TO_TRANSFER 0x20
880 #define REQ_STATE_PREPARE_TO_NEXT 0x21
881 #define REQ_STATE_READY_TO_TRANSFER 0x30
882
883 #define REQ_STATE_EXPECTING_INTR 0x40
884 #define REQ_STATE_ATAPI_EXPECTING_CMD_INTR 0x41
885 #define REQ_STATE_ATAPI_EXPECTING_DATA_INTR 0x42
886 #define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2 0x43
887 #define REQ_STATE_ATAPI_DO_NOTHING_INTR 0x44
888
889 #define REQ_STATE_EARLY_INTR 0x48
890
891 #define REQ_STATE_PROCESSING_INTR 0x50
892
893 #define REQ_STATE_DPC_INTR_REQ 0x51
894 #define REQ_STATE_DPC_RESET_REQ 0x52
895 #define REQ_STATE_DPC_COMPLETE_REQ 0x53
896
897 #define REQ_STATE_DPC_WAIT_BUSY0 0x57
898 #define REQ_STATE_DPC_WAIT_BUSY1 0x58
899 #define REQ_STATE_DPC_WAIT_BUSY 0x59
900 #define REQ_STATE_DPC_WAIT_DRQ 0x5a
901 #define REQ_STATE_DPC_WAIT_DRQ0 0x5b
902 #define REQ_STATE_DPC_WAIT_DRQ_ERR 0x5c
903
904 #define REQ_STATE_TRANSFER_COMPLETE 0x7f
905
906 // Command actions:
907 #define CMD_ACTION_PREPARE 0x01
908 #define CMD_ACTION_EXEC 0x02
909 #define CMD_ACTION_ALL (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)
910
911 // predefined Reorder costs
912 #define REORDER_COST_MAX ((DEF_I64(0x1) << 60) - 1)
913 #define REORDER_COST_TTL (REORDER_COST_MAX - 1)
914 #define REORDER_COST_INTERSECT (REORDER_COST_MAX - 2)
915 #define REORDER_COST_DENIED (REORDER_COST_MAX - 3)
916 #define REORDER_COST_RESELECT (REORDER_COST_MAX/4)
917
918 #define REORDER_COST_SWITCH_RW_CD (REORDER_COST_MAX/8)
919 #define REORDER_MCOST_SWITCH_RW_CD (0)
920 #define REORDER_MCOST_SEEK_BACK_CD (16)
921
922 #define REORDER_COST_SWITCH_RW_HDD (0)
923 #define REORDER_MCOST_SWITCH_RW_HDD (4)
924 #define REORDER_MCOST_SEEK_BACK_HDD (2)
925
926 /*typedef struct _ATA_QUEUE {
927 struct _ATA_REQ* head_req; // index
928 struct _ATA_REQ* tail_req; // index
929 ULONG req_count;
930 ULONG dma_base;
931 BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
932 } ATA_QUEUE, *PATA_QUEUE;*/
933
934 struct _HW_DEVICE_EXTENSION;
935 struct _HW_LU_EXTENSION;
936
937 typedef struct _IORES {
938 union {
939 ULONG Addr; /* Base address*/
940 PVOID pAddr; /* Base address in pointer form */
941 };
942 ULONG MemIo:1; /* Memory mapping (1) vs IO ports (0) */
943 ULONG Proc:1; /* Need special processing via IO_Proc */
944 ULONG Reserved:30;
945 } IORES, *PIORES;
946
947 // Channel extension
948 typedef struct _HW_CHANNEL {
949
950 PATA_REQ cur_req;
951 ULONG cur_cdev;
952 /* PATA_REQ first_req;
953 PATA_REQ last_req;*/
954 ULONG queue_depth;
955 ULONG ChannelSelectWaitCount;
956
957 UCHAR DpcState;
958
959 BOOLEAN ExpectingInterrupt; // Indicates expecting an interrupt
960 BOOLEAN RDP; // Indicate last tape command was DSC Restrictive.
961 // Indicates whether '0x1f0' is the base address. Used
962 // in SMART Ioctl calls.
963 BOOLEAN PrimaryAddress;
964 // Placeholder for the sub-command value of the last
965 // SMART command.
966 UCHAR SmartCommand;
967 // Reorder anabled
968 BOOLEAN UseReorder;
969 // Placeholder for status register after a GET_MEDIA_STATUS command
970 UCHAR ReturningMediaStatus;
971
972 BOOLEAN CopyDmaBuffer;
973 //BOOLEAN MemIo;
974 BOOLEAN AltRegMap;
975
976 UCHAR Reserved[3];
977
978 MECHANICAL_STATUS_INFORMATION_HEADER MechStatusData;
979 SENSE_DATA MechStatusSense;
980 ULONG MechStatusRetryCount;
981 SCSI_REQUEST_BLOCK InternalSrb;
982
983 ULONG MaxTransferMode; // may differ from Controller's value due to 40-pin cable
984
985 ULONG ChannelCtrlFlags;
986 ULONG ResetInProgress; // flag
987 LONG DisableIntr;
988 LONG CheckIntr;
989
990 ULONG lChannel;
991
992 #define CHECK_INTR_ACTIVE 0x03
993 #define CHECK_INTR_DETECTED 0x02
994 #define CHECK_INTR_CHECK 0x01
995 #define CHECK_INTR_IDLE 0x00
996
997 ULONG NextDpcChan;
998 PHW_TIMER HwScsiTimer;
999 LONGLONG DpcTime;
1000 #if 0
1001 PHW_TIMER HwScsiTimer1;
1002 PHW_TIMER HwScsiTimer2;
1003 LONGLONG DpcTime1;
1004 // PHW_TIMER CurDpc;
1005 // LARGE_INTEGER ActivationTime;
1006
1007 // KDPC Dpc;
1008 // KTIMER Timer;
1009 // PHW_TIMER HwScsiTimer;
1010 // KSPIN_LOCK QueueSpinLock;
1011 // KIRQL QueueOldIrql;
1012 #endif
1013 struct _HW_DEVICE_EXTENSION* DeviceExtension;
1014 struct _HW_LU_EXTENSION* lun[IDE_MAX_LUN_PER_CHAN];
1015
1016 ULONG NumberLuns;
1017 ULONG PmLunMap;
1018
1019 // Double-buffering support
1020 PVOID DB_PRD;
1021 ULONG DB_PRD_PhAddr;
1022 PVOID DB_IO;
1023 ULONG DB_IO_PhAddr;
1024
1025 PUCHAR DmaBuffer;
1026
1027 //
1028 PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock0; // unaligned
1029 PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock; // 128-byte aligned
1030 ULONGLONG AHCI_CTL_PhAddr;
1031 IORES BaseIoAHCI_Port;
1032 ULONG AhciPrevCI;
1033 ULONG AhciCompleteCI;
1034 ULONG AhciLastIS;
1035 //PVOID AHCI_FIS; // is not actually used by UniATA now, but is required by AHCI controller
1036 //ULONGLONG AHCI_FIS_PhAddr;
1037 // Note: in contrast to FBSD, we keep PRD and CMD item in AtaReq structure
1038 PATA_REQ AhciInternalAtaReq;
1039 PSCSI_REQUEST_BLOCK AhciInternalSrb;
1040
1041 #ifdef QUEUE_STATISTICS
1042 LONGLONG QueueStat[MAX_QUEUE_STAT];
1043 LONGLONG ReorderCount;
1044 LONGLONG IntersectCount;
1045 LONGLONG TryReorderCount;
1046 LONGLONG TryReorderHeadCount;
1047 LONGLONG TryReorderTailCount; /* in-order requests */
1048 #endif //QUEUE_STATISTICS
1049
1050 //ULONG BaseMemAddress;
1051 //ULONG BaseMemAddressOffset;
1052 IORES RegTranslation[IDX_MAX_REG];
1053
1054 } HW_CHANNEL, *PHW_CHANNEL;
1055
1056 #define CTRFLAGS_DMA_ACTIVE 0x0001
1057 #define CTRFLAGS_DMA_RO 0x0002
1058 #define CTRFLAGS_DMA_OPERATION 0x0004
1059 #define CTRFLAGS_INTR_DISABLED 0x0008
1060 #define CTRFLAGS_DPC_REQ 0x0010
1061 #define CTRFLAGS_ENABLE_INTR_REQ 0x0020
1062 #define CTRFLAGS_LBA48 0x0040
1063 #define CTRFLAGS_DSC_BSY 0x0080
1064 #define CTRFLAGS_NO_SLAVE 0x0100
1065 //#define CTRFLAGS_PATA 0x0200
1066 //#define CTRFLAGS_NOT_PRESENT 0x0200
1067 #define CTRFLAGS_AHCI_PM 0x0400
1068 #define CTRFLAGS_AHCI_PM2 0x0800
1069
1070 #define CTRFLAGS_PERMANENT (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)
1071
1072 #define GEOM_AUTO 0xffffffff
1073 #define GEOM_STD 0x0000
1074 #define GEOM_UNIATA 0x0001
1075 #define GEOM_ORIG 0x0002
1076 #define GEOM_MANUAL 0x0003
1077
1078 #define DPC_STATE_NONE 0x00
1079 #define DPC_STATE_ISR 0x10
1080 #define DPC_STATE_DPC 0x20
1081 #define DPC_STATE_TIMER 0x30
1082 #define DPC_STATE_COMPLETE 0x40
1083
1084 // Logical unit extension
1085 typedef struct _HW_LU_EXTENSION {
1086 IDENTIFY_DATA2 IdentifyData;
1087 ULONGLONG NumOfSectors;
1088 ULONG DeviceFlags; // Flags word for each possible device. DFLAGS_XXX
1089 ULONG DiscsPresent; // Indicates number of platters on changer-ish devices.
1090 BOOLEAN DWordIO; // Indicates use of 32-bit PIO
1091 UCHAR ReturningMediaStatus;
1092 UCHAR MaximumBlockXfer;
1093 UCHAR PowerState;
1094
1095 UCHAR TransferMode; // current transfer mode
1096 UCHAR LimitedTransferMode; // user-defined or IDE cable limitation
1097 UCHAR OrigTransferMode; // transfer mode, returned by device IDENTIFY (can be changed via IOCTL)
1098 UCHAR PhyTransferMode; // phy transfer mode (actual bus transfer mode for PATA DMA and SATA)
1099
1100 ULONG ErrorCount; // Count of errors. Used to turn off features.
1101 // ATA_QUEUE cmd_queue;
1102 LONGLONG ReadCmdCost;
1103 LONGLONG WriteCmdCost;
1104 LONGLONG OtherCmdCost;
1105 LONGLONG RwSwitchCost;
1106 LONGLONG RwSwitchMCost;
1107 LONGLONG SeekBackMCost;
1108 //
1109 PATA_REQ first_req;
1110 PATA_REQ last_req;
1111 ULONG queue_depth;
1112 ULONG last_write;
1113
1114 ULONG LunSelectWaitCount;
1115 ULONG AtapiReadyWaitDelay;
1116
1117 // tuning options
1118 ULONG opt_GeomType;
1119 ULONG opt_MaxTransferMode;
1120 ULONG opt_PreferedTransferMode;
1121 BOOLEAN opt_ReadCacheEnable;
1122 BOOLEAN opt_WriteCacheEnable;
1123 UCHAR opt_ReadOnly;
1124 UCHAR opt_AdvPowerMode;
1125 UCHAR opt_AcousticMode;
1126 UCHAR opt_StandbyTimer;
1127 UCHAR opt_Padding[2]; // padding
1128
1129 struct _SBadBlockListItem* bbListDescr;
1130 struct _SBadBlockRange* arrBadBlocks;
1131 ULONG nBadBlocks;
1132
1133 // Controller-specific LUN options
1134 union {
1135 /* for tricky controllers, those can change Logical-to-Physical LUN mapping.
1136 mainly for mapping SATA ports to compatible PATA registers
1137 Treated as PHYSICAL port number, regardless of logical mapping.
1138 */
1139 ULONG SATA_lun_map;
1140 };
1141
1142 struct _HW_DEVICE_EXTENSION* DeviceExtension;
1143 struct _HW_CHANNEL* chan;
1144 ULONG Lun;
1145
1146 #ifdef IO_STATISTICS
1147
1148 LONGLONG ModeErrorCount[MAX_RETRIES];
1149 LONGLONG RecoverCount[MAX_RETRIES];
1150 LONGLONG IoCount;
1151 LONGLONG BlockIoCount;
1152
1153 #endif//IO_STATISTICS
1154 } HW_LU_EXTENSION, *PHW_LU_EXTENSION;
1155
1156 // Device extension
1157 typedef struct _HW_DEVICE_EXTENSION {
1158 CHAR Signature[32];
1159 //PIDE_REGISTERS_1 BaseIoAddress1[IDE_MAX_CHAN]; // Base register locations
1160 //PIDE_REGISTERS_2 BaseIoAddress2[IDE_MAX_CHAN];
1161 ULONG BusInterruptLevel; // Interrupt level
1162 ULONG InterruptMode; // Interrupt Mode (Level or Edge)
1163 ULONG BusInterruptVector;
1164 // Number of channels being supported by one instantiation
1165 // of the device extension. Normally (and correctly) one, but
1166 // with so many broken PCI IDE controllers being sold, we have
1167 // to support them.
1168 ULONG NumberChannels;
1169 ULONG NumberLuns;
1170 ULONG FirstChannelToCheck;
1171 #if 0
1172 HW_LU_EXTENSION lun[IDE_MAX_LUN];
1173 HW_CHANNEL chan[AHCI_MAX_PORT/*IDE_MAX_CHAN*/];
1174 #else
1175 PHW_LU_EXTENSION lun; // lun array
1176 PHW_CHANNEL chan; // channel array
1177 #endif
1178 UCHAR LastInterruptedChannel;
1179 // Indicates the number of blocks transferred per int. according to the
1180 // identify data.
1181 BOOLEAN DriverMustPoll; // Driver is being used by the crash dump utility or ntldr.
1182 BOOLEAN BusMaster;
1183 BOOLEAN UseDpc; // Indicates use of DPC on long waits
1184 IDENTIFY_DATA FullIdentifyData; // Identify data for device
1185 // BusMaster specific data
1186 // PBM_DMA_ENTRY dma_tab_0;
1187 //KSPIN_LOCK DpcSpinLock;
1188
1189 ULONG ActiveDpcChan;
1190 ULONG FirstDpcChan;
1191 ULONG ExpectingInterrupt; // Indicates entire controller expecting an interrupt
1192 /*
1193 PHW_TIMER HwScsiTimer1;
1194 PHW_TIMER HwScsiTimer2;
1195 LONGLONG DpcTime1;
1196 LONGLONG DpcTime2;
1197 */
1198 ULONG queue_depth;
1199
1200 PDEVICE_OBJECT Isr2DevObj;
1201
1202 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0;
1203 IORES BaseIoAddressBM_0;
1204 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM[IDE_MAX_CHAN];
1205
1206 // Device identification
1207 ULONG DevID;
1208 ULONG RevID;
1209 ULONG slotNumber;
1210 ULONG SystemIoBusNumber;
1211 ULONG DevIndex;
1212
1213 ULONG InitMethod; // vendor specific
1214
1215 ULONG Channel;
1216
1217 ULONG HbaCtrlFlags;
1218 BOOLEAN simplexOnly;
1219 //BOOLEAN MemIo;
1220 BOOLEAN AltRegMap;
1221 BOOLEAN UnknownDev;
1222 BOOLEAN MasterDev;
1223 BOOLEAN Host64;
1224 BOOLEAN DWordIO; // Indicates use of 32-bit PIO
1225 /* // Indicates, that HW Initialized is already called for this controller
1226 // 0 bit for Primary, 1 - for Secondary. Is used to manage AltInit under w2k+
1227 UCHAR Initialized; */
1228 UCHAR Reserved1[2];
1229
1230 LONG ReCheckIntr;
1231
1232 ULONG MaxTransferMode; // max transfer mode supported by controller
1233 ULONG HwFlags;
1234 INTERFACE_TYPE OrigAdapterInterfaceType;
1235 INTERFACE_TYPE AdapterInterfaceType;
1236 ULONG MaximumDmaTransferLength;
1237 ULONG AlignmentMask;
1238 ULONG DmaSegmentLength;
1239 ULONG DmaSegmentAlignmentMask; // must be PAGE-aligned
1240
1241 //ULONG BaseMemAddress;
1242
1243 //PIDE_SATA_REGISTERS BaseIoAddressSATA_0;
1244 IORES BaseIoAddressSATA_0;
1245 //PIDE_SATA_REGISTERS BaseIoAddressSATA[IDE_MAX_CHAN];
1246
1247 IORES BaseIoAHCI_0;
1248 //PIDE_AHCI_PORT_REGISTERS BaseIoAHCIPort[AHCI_MAX_PORT];
1249 ULONG AHCI_CAP;
1250 ULONG AHCI_PI;
1251 PATA_REQ AhciInternalAtaReq0;
1252 PSCSI_REQUEST_BLOCK AhciInternalSrb0;
1253
1254 BOOLEAN opt_AtapiDmaZeroTransfer; // default FALSE
1255 BOOLEAN opt_AtapiDmaControlCmd; // default FALSE
1256 BOOLEAN opt_AtapiDmaRawRead; // default TRUE
1257 BOOLEAN opt_AtapiDmaReadWrite; // default TRUE
1258
1259 PCCH FullDevName;
1260
1261 // Controller specific state/options
1262 union {
1263 ULONG HwCfg;
1264 };
1265
1266 } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
1267
1268 typedef struct _ISR2_DEVICE_EXTENSION {
1269 PHW_DEVICE_EXTENSION HwDeviceExtension;
1270 ULONG DevIndex;
1271 } ISR2_DEVICE_EXTENSION, *PISR2_DEVICE_EXTENSION;
1272
1273 typedef ISR2_DEVICE_EXTENSION PCIIDE_DEVICE_EXTENSION;
1274 typedef PISR2_DEVICE_EXTENSION PPCIIDE_DEVICE_EXTENSION;
1275
1276 #define HBAFLAGS_DMA_DISABLED 0x01
1277 #define HBAFLAGS_DMA_DISABLED_LBA48 0x02
1278
1279 extern UCHAR pciBuffer[256];
1280 extern PBUSMASTER_CONTROLLER_INFORMATION BMList;
1281 extern ULONG BMListLen;
1282 extern ULONG IsaCount;
1283 extern ULONG MCACount;
1284 extern UNICODE_STRING SavedRegPath;
1285
1286 //extern const CHAR retry_Wdma[MAX_RETRIES+1];
1287 //extern const CHAR retry_Udma[MAX_RETRIES+1];
1288
1289 extern VOID
1290 NTAPI
1291 UniataEnumBusMasterController(
1292 IN PVOID DriverObject,
1293 PVOID Argument2
1294 );
1295
1296 extern ULONG NTAPI
1297 UniataFindCompatBusMasterController1(
1298 IN PVOID HwDeviceExtension,
1299 IN PVOID Context,
1300 IN PVOID BusInformation,
1301 IN PCHAR ArgumentString,
1302 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1303 OUT PBOOLEAN Again
1304 );
1305
1306 extern ULONG NTAPI
1307 UniataFindCompatBusMasterController2(
1308 IN PVOID HwDeviceExtension,
1309 IN PVOID Context,
1310 IN PVOID BusInformation,
1311 IN PCHAR ArgumentString,
1312 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1313 OUT PBOOLEAN Again
1314 );
1315
1316 #define UNIATA_ALLOCATE_NEW_LUNS 0x00
1317
1318 extern BOOLEAN NTAPI
1319 UniataAllocateLunExt(
1320 PHW_DEVICE_EXTENSION deviceExtension,
1321 ULONG NewNumberChannels
1322 );
1323
1324 extern VOID NTAPI
1325 UniataFreeLunExt(
1326 PHW_DEVICE_EXTENSION deviceExtension
1327 );
1328
1329 extern ULONG NTAPI
1330 UniataFindBusMasterController(
1331 IN PVOID HwDeviceExtension,
1332 IN PVOID Context,
1333 IN PVOID BusInformation,
1334 IN PCHAR ArgumentString,
1335 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1336 OUT PBOOLEAN Again
1337 );
1338
1339 extern NTSTATUS
1340 NTAPI
1341 UniataClaimLegacyPCIIDE(
1342 ULONG i
1343 );
1344
1345 extern NTSTATUS
1346 NTAPI
1347 UniataConnectIntr2(
1348 IN PVOID HwDeviceExtension
1349 );
1350
1351 extern NTSTATUS
1352 NTAPI
1353 UniataDisconnectIntr2(
1354 IN PVOID HwDeviceExtension
1355 );
1356
1357 extern ULONG
1358 NTAPI
1359 ScsiPortGetBusDataByOffset(
1360 IN PVOID HwDeviceExtension,
1361 IN BUS_DATA_TYPE BusDataType,
1362 IN ULONG BusNumber,
1363 IN ULONG SlotNumber,
1364 IN PVOID Buffer,
1365 IN ULONG Offset,
1366 IN ULONG Length
1367 );
1368
1369 #define PCIBUSNUM_NOT_SPECIFIED (0xffffffffL)
1370 #define PCISLOTNUM_NOT_SPECIFIED (0xffffffffL)
1371
1372 extern ULONG
1373 NTAPI
1374 AtapiFindListedDev(
1375 PBUSMASTER_CONTROLLER_INFORMATION BusMasterAdapters,
1376 ULONG lim,
1377 IN PVOID HwDeviceExtension,
1378 IN ULONG BusNumber,
1379 IN ULONG SlotNumber,
1380 OUT PCI_SLOT_NUMBER* _slotData // optional
1381 );
1382
1383 extern ULONG
1384 NTAPI
1385 AtapiFindDev(
1386 IN PVOID HwDeviceExtension,
1387 IN BUS_DATA_TYPE BusDataType,
1388 IN ULONG BusNumber,
1389 IN ULONG SlotNumber,
1390 IN ULONG dev_id,
1391 IN ULONG RevID
1392 );
1393
1394 extern VOID
1395 NTAPI
1396 AtapiDmaAlloc(
1397 IN PVOID HwDeviceExtension,
1398 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1399 IN ULONG lChannel // logical channel,
1400 );
1401
1402 extern BOOLEAN
1403 NTAPI
1404 AtapiDmaSetup(
1405 IN PVOID HwDeviceExtension,
1406 IN ULONG DeviceNumber,
1407 IN ULONG lChannel, // logical channel,
1408 IN PSCSI_REQUEST_BLOCK Srb,
1409 IN PUCHAR data,
1410 IN ULONG count
1411 );
1412
1413 extern BOOLEAN
1414 NTAPI
1415 AtapiDmaPioSync(
1416 PVOID HwDeviceExtension,
1417 PSCSI_REQUEST_BLOCK Srb,
1418 PUCHAR data,
1419 ULONG count
1420 );
1421
1422 extern BOOLEAN
1423 NTAPI
1424 AtapiDmaDBSync(
1425 PHW_CHANNEL chan,
1426 PSCSI_REQUEST_BLOCK Srb
1427 );
1428
1429 extern VOID
1430 NTAPI
1431 AtapiDmaStart(
1432 IN PVOID HwDeviceExtension,
1433 IN ULONG DeviceNumber,
1434 IN ULONG lChannel, // logical channel,
1435 IN PSCSI_REQUEST_BLOCK Srb
1436 );
1437
1438 extern UCHAR
1439 NTAPI
1440 AtapiDmaDone(
1441 IN PVOID HwDeviceExtension,
1442 IN ULONG DeviceNumber,
1443 IN ULONG lChannel, // logical channel,
1444 IN PSCSI_REQUEST_BLOCK Srb
1445 );
1446
1447 extern VOID
1448 NTAPI
1449 AtapiDmaReinit(
1450 IN PHW_DEVICE_EXTENSION deviceExtension,
1451 IN PHW_LU_EXTENSION LunExt,
1452 IN PATA_REQ AtaReq
1453 );
1454
1455 extern VOID
1456 NTAPI
1457 AtapiDmaInit__(
1458 IN PHW_DEVICE_EXTENSION deviceExtension,
1459 IN PHW_LU_EXTENSION LunExt
1460 );
1461
1462 extern VOID
1463 NTAPI
1464 AtapiDmaInit(
1465 IN PVOID HwDeviceExtension,
1466 IN ULONG DeviceNumber,
1467 IN ULONG lChannel, // logical channel,
1468 // is always 0 except simplex-only and multi-channel controllers
1469 IN SCHAR apiomode,
1470 IN SCHAR wdmamode,
1471 IN SCHAR udmamode
1472 );
1473
1474 extern BOOLEAN NTAPI
1475 AtapiInterrupt2(
1476 IN PKINTERRUPT Interrupt,
1477 IN PVOID HwDeviceExtension
1478 );
1479
1480 extern PDRIVER_OBJECT SavedDriverObject;
1481
1482 extern BOOLEAN
1483 NTAPI
1484 UniataChipDetectChannels(
1485 IN PVOID HwDeviceExtension,
1486 IN PPCI_COMMON_CONFIG pciData, // optional
1487 IN ULONG DeviceNumber,
1488 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo
1489 );
1490
1491 extern NTSTATUS
1492 NTAPI
1493 UniataChipDetect(
1494 IN PVOID HwDeviceExtension,
1495 IN PPCI_COMMON_CONFIG pciData, // optional
1496 IN ULONG DeviceNumber,
1497 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1498 IN BOOLEAN* simplexOnly
1499 );
1500
1501 extern BOOLEAN
1502 NTAPI
1503 AtapiChipInit(
1504 IN PVOID HwDeviceExtension,
1505 IN ULONG DeviceNumber,
1506 IN ULONG c
1507 );
1508
1509 extern ULONG
1510 NTAPI
1511 AtapiGetIoRange(
1512 IN PVOID HwDeviceExtension,
1513 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1514 IN PPCI_COMMON_CONFIG pciData,
1515 IN ULONG SystemIoBusNumber,
1516 IN ULONG rid,
1517 IN ULONG offset,
1518 IN ULONG length //range id
1519 );
1520
1521 extern USHORT
1522 NTAPI
1523 UniataEnableIoPCI(
1524 IN ULONG busNumber,
1525 IN ULONG slotNumber,
1526 IN OUT PPCI_COMMON_CONFIG pciData
1527 );
1528
1529 /****************** 1 *****************/
1530 #define GetPciConfig1(offs, op) { \
1531 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1532 PCIConfiguration, \
1533 SystemIoBusNumber, \
1534 slotNumber, \
1535 &op, \
1536 offs, \
1537 1); \
1538 }
1539
1540 #define SetPciConfig1(offs, op) { \
1541 UCHAR _a = op; \
1542 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1543 PCIConfiguration, \
1544 SystemIoBusNumber, \
1545 slotNumber, \
1546 &_a, \
1547 offs, \
1548 1); \
1549 }
1550
1551 #define ChangePciConfig1(offs, _op) { \
1552 UCHAR a = 0; \
1553 GetPciConfig1(offs, a); \
1554 a = (UCHAR)(_op); \
1555 SetPciConfig1(offs, a); \
1556 }
1557
1558 /****************** 2 *****************/
1559 #define GetPciConfig2(offs, op) { \
1560 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1561 PCIConfiguration, \
1562 SystemIoBusNumber, \
1563 slotNumber, \
1564 &op, \
1565 offs, \
1566 2); \
1567 }
1568
1569 #define SetPciConfig2(offs, op) { \
1570 USHORT _a = op; \
1571 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1572 PCIConfiguration, \
1573 SystemIoBusNumber, \
1574 slotNumber, \
1575 &_a, \
1576 offs, \
1577 2); \
1578 }
1579
1580 #define ChangePciConfig2(offs, _op) { \
1581 USHORT a = 0; \
1582 GetPciConfig2(offs, a); \
1583 a = (USHORT)(_op); \
1584 SetPciConfig2(offs, a); \
1585 }
1586
1587 /****************** 4 *****************/
1588 #define GetPciConfig4(offs, op) { \
1589 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1590 PCIConfiguration, \
1591 SystemIoBusNumber, \
1592 slotNumber, \
1593 &op, \
1594 offs, \
1595 4); \
1596 }
1597
1598 #define SetPciConfig4(offs, op) { \
1599 ULONG _a = op; \
1600 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1601 PCIConfiguration, \
1602 SystemIoBusNumber, \
1603 slotNumber, \
1604 &_a, \
1605 offs, \
1606 4); \
1607 }
1608
1609 #define ChangePciConfig4(offs, _op) { \
1610 ULONG a = 0; \
1611 GetPciConfig4(offs, a); \
1612 a = _op; \
1613 SetPciConfig4(offs, a); \
1614 }
1615
1616 #define DMA_MODE_NONE 0x00
1617 #define DMA_MODE_BM 0x01
1618 #define DMA_MODE_AHCI 0x02
1619
1620 #ifndef GetDmaStatus
1621 #define GetDmaStatus(de, c) \
1622 (((de)->BusMaster == DMA_MODE_BM) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)
1623 #endif //GetDmaStatus
1624
1625 #ifdef USE_OWN_DMA
1626 #define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1627 AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);
1628 #else
1629 #define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1630 (ScsiPortConvertPhysicalAddressToUlong/*(ULONG)ScsiPortGetVirtualAddress*/(/*hwde,*/ \
1631 ScsiPortGetPhysicalAddress(hwde, srb, phaddr, plen)))
1632 #endif //USE_OWN_DMA
1633
1634 VOID
1635 DDKFASTAPI
1636 AtapiWritePort4(
1637 IN PHW_CHANNEL chan,
1638 IN ULONGIO_PTR port,
1639 IN ULONG data
1640 );
1641
1642 VOID
1643 DDKFASTAPI
1644 AtapiWritePort2(
1645 IN PHW_CHANNEL chan,
1646 IN ULONGIO_PTR port,
1647 IN USHORT data
1648 );
1649
1650 VOID
1651 DDKFASTAPI
1652 AtapiWritePort1(
1653 IN PHW_CHANNEL chan,
1654 IN ULONGIO_PTR port,
1655 IN UCHAR data
1656 );
1657
1658 VOID
1659 DDKFASTAPI
1660 AtapiWritePortEx4(
1661 IN PHW_CHANNEL chan,
1662 IN ULONGIO_PTR port,
1663 IN ULONG offs,
1664 IN ULONG data
1665 );
1666
1667 VOID
1668 DDKFASTAPI
1669 AtapiWritePortEx1(
1670 IN PHW_CHANNEL chan,
1671 IN ULONGIO_PTR port,
1672 IN ULONG offs,
1673 IN UCHAR data
1674 );
1675
1676 ULONG
1677 DDKFASTAPI
1678 AtapiReadPort4(
1679 IN PHW_CHANNEL chan,
1680 IN ULONGIO_PTR port
1681 );
1682
1683 USHORT
1684 DDKFASTAPI
1685 AtapiReadPort2(
1686 IN PHW_CHANNEL chan,
1687 IN ULONGIO_PTR port
1688 );
1689
1690 UCHAR
1691 DDKFASTAPI
1692 AtapiReadPort1(
1693 IN PHW_CHANNEL chan,
1694 IN ULONGIO_PTR port
1695 );
1696
1697 ULONG
1698 DDKFASTAPI
1699 AtapiReadPortEx4(
1700 IN PHW_CHANNEL chan,
1701 IN ULONGIO_PTR port,
1702 IN ULONG offs
1703 );
1704
1705 UCHAR
1706 DDKFASTAPI
1707 AtapiReadPortEx1(
1708 IN PHW_CHANNEL chan,
1709 IN ULONGIO_PTR port,
1710 IN ULONG offs
1711 );
1712
1713 VOID
1714 DDKFASTAPI
1715 AtapiWriteBuffer4(
1716 IN PHW_CHANNEL chan,
1717 IN ULONGIO_PTR _port,
1718 IN PVOID Buffer,
1719 IN ULONG Count,
1720 IN ULONG Timing
1721 );
1722
1723 VOID
1724 DDKFASTAPI
1725 AtapiWriteBuffer2(
1726 IN PHW_CHANNEL chan,
1727 IN ULONGIO_PTR _port,
1728 IN PVOID Buffer,
1729 IN ULONG Count,
1730 IN ULONG Timing
1731 );
1732
1733 VOID
1734 DDKFASTAPI
1735 AtapiReadBuffer4(
1736 IN PHW_CHANNEL chan,
1737 IN ULONGIO_PTR _port,
1738 IN PVOID Buffer,
1739 IN ULONG Count,
1740 IN ULONG Timing
1741 );
1742
1743 VOID
1744 DDKFASTAPI
1745 AtapiReadBuffer2(
1746 IN PHW_CHANNEL chan,
1747 IN ULONGIO_PTR _port,
1748 IN PVOID Buffer,
1749 IN ULONG Count,
1750 IN ULONG Timing
1751 );
1752
1753 /*#define GET_CHANNEL(Srb) (Srb->TargetId >> 1)
1754 #define GET_LDEV(Srb) (Srb->TargetId)
1755 #define GET_LDEV2(P, T, L) (T)*/
1756
1757 #define GET_CHANNEL(Srb) (Srb->PathId)
1758 //#define GET_LDEV(Srb) (Srb->TargetId | (Srb->PathId << 1))
1759 //#define GET_LDEV2(P, T, L) (T | ((P)<<1))
1760 #define GET_CDEV(Srb) (Srb->TargetId)
1761
1762 VOID
1763 NTAPI
1764 AtapiSetupLunPtrs(
1765 IN PHW_CHANNEL chan,
1766 IN PHW_DEVICE_EXTENSION deviceExtension,
1767 IN ULONG c
1768 );
1769 /*
1770 #define AtapiSetupLunPtrs(chan, deviceExtension, c) \
1771 { \
1772 chan->DeviceExtension = deviceExtension; \
1773 chan->lChannel = c; \
1774 chan->lun[0] = &(deviceExtension->lun[c*2+0]); \
1775 chan->lun[1] = &(deviceExtension->lun[c*2+1]); \
1776 chan->AltRegMap = deviceExtension->AltRegMap; \
1777 chan->NextDpcChan = -1; \
1778 chan->lun[0]->DeviceExtension = deviceExtension; \
1779 chan->lun[1]->DeviceExtension = deviceExtension; \
1780 }
1781 */
1782 BOOLEAN
1783 NTAPI
1784 AtapiReadChipConfig(
1785 IN PVOID HwDeviceExtension,
1786 IN ULONG DeviceNumber,
1787 IN ULONG channel // physical channel
1788 );
1789
1790 VOID
1791 NTAPI
1792 UniataForgetDevice(
1793 PHW_LU_EXTENSION LunExt
1794 );
1795
1796 extern ULONG SkipRaids;
1797 extern ULONG ForceSimplex;
1798 extern BOOLEAN g_opt_AtapiDmaRawRead;
1799 extern BOOLEAN hasPCI;
1800
1801 extern BOOLEAN InDriverEntry;
1802
1803 extern BOOLEAN g_opt_Verbose;
1804 extern ULONG g_opt_VirtualMachine;
1805
1806 #define VM_AUTO 0x00
1807 #define VM_NONE 0x01
1808 #define VM_VBOX 0x02
1809 #define VM_VMWARE 0x03
1810 #define VM_QEMU 0x04
1811
1812 #define VM_MAX_KNOWN VM_QEMU
1813
1814 extern BOOLEAN WinVer_WDM_Model;
1815
1816 #endif //__IDE_BUSMASTER_H__
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