3 Copyright (c) 2002-2012 Alexander A. Telyatnikov (Alter)
9 This is the miniport driver for ATAPI IDE controllers
10 With Busmaster DMA support
13 Alexander A. Telyatnikov (Alter)
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 This module is a port from FreeBSD 4.3-6.1 ATA driver (ata-dma.c, ata-chipset.c) by
34 Søren Schmidt, Copyright (c) 1998-2008
36 Changed defaulting-to-generic-PIO/DMA policy
37 Added PIO settings for VIA
38 Optimized VIA/AMD/nVidia init part
39 Optimized Promise TX2 init part
40 Optimized Intel init part
41 by Alex A. Telyatnikov (Alter) (c) 2002-2007
48 static const ULONG valid_udma
[7] = {0,0,2,0,4,5,6};
50 static const CHAR retry_Wdma
[MAX_RETRIES
+1] = {2, 2, 2,-1,-1,-1};
51 static const CHAR retry_Udma
[MAX_RETRIES
+1] = {6, 2,-1,-1,-1,-1};
53 PHYSICAL_ADDRESS ph4gb
= {{0xFFFFFFFF, 0}};
58 IN PHW_DEVICE_EXTENSION deviceExtension
,
59 IN ULONG dev
, // physical device number (0-3)
66 IN PHW_DEVICE_EXTENSION deviceExtension
,
67 IN ULONG dev
, // physical device number (0-3)
74 IN PHW_DEVICE_EXTENSION deviceExtension
,
75 IN ULONG dev
, // physical device number (0-3)
82 IN PHW_DEVICE_EXTENSION deviceExtension
,
83 IN ULONG dev
, // physical device number (0-3)
90 IN PHW_DEVICE_EXTENSION deviceExtension
,
91 IN ULONG channel
// physical channel number (0-1)
97 IN PVOID HwDeviceExtension
,
98 IN PSCSI_REQUEST_BLOCK Srb
,
100 OUT PULONG count
, /* bytes */
104 PHYSICAL_ADDRESS ph_addr
;
107 ph_addr
= MmGetPhysicalAddress(data
);
108 if(!ph_addru
&& ph_addr
.HighPart
) {
109 // do so until we add 64bit address support
110 // or some workaround
115 (*ph_addru
) = ph_addr
.HighPart
;
116 //addr = ScsiPortConvertPhysicalAddressToUlong(ph_addr);
117 addr
= ph_addr
.LowPart
;
118 if(!addr
&& !ph_addr
.HighPart
) {
123 *count
= sizeof(BM_DMA_ENTRY
)*ATA_DMA_ENTRIES
;
125 *count
= PAGE_SIZE
- (addr
& (PAGE_SIZE
-1));
128 } // end AtapiVirtToPhysAddr_()
133 IN PVOID HwDeviceExtension
,
134 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo
,
135 IN ULONG lChannel
// logical channel,
139 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
140 PHW_CHANNEL chan
= &(deviceExtension
->chan
[lChannel
]);
145 deviceExtension
->chan
[c
].CopyDmaBuffer
= FALSE
;
147 if(!deviceExtension
->Host64
&& (WinVer_Id() > WinVer_NT
)) {
148 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: allocate tmp buffers below 4Gb\n"));
149 chan
->DB_PRD
= MmAllocateContiguousMemory(sizeof(((PATA_REQ
)NULL
)->dma_tab
), ph4gb
);
151 chan
->DB_PRD_PhAddr
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)(chan
->DB_PRD
), &i
, &ph_addru
);
152 if(!chan
->DB_PRD_PhAddr
|| !i
|| ((LONG
)(chan
->DB_PRD_PhAddr
) == -1)) {
153 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No DB PRD BASE\n" ));
155 chan
->DB_PRD_PhAddr
= 0;
159 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No DB PRD below 4Gb\n" ));
163 chan
->DB_IO
= MmAllocateContiguousMemory(deviceExtension
->MaximumDmaTransferLength
, ph4gb
);
165 chan
->DB_IO_PhAddr
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)(chan
->DB_IO
), &i
, &ph_addru
);
166 if(!chan
->DB_IO_PhAddr
|| !i
|| ((LONG
)(chan
->DB_IO_PhAddr
) == -1)) {
167 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No DB IO BASE\n" ));
169 MmFreeContiguousMemory(chan
->DB_PRD
);
171 chan
->DB_PRD_PhAddr
= 0;
173 chan
->DB_IO_PhAddr
= 0;
177 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No DB IO below 4Gb\n" ));
178 MmFreeContiguousMemory(chan
->DB_IO
);
185 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
186 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: AHCI\n" ));
187 if(chan
->AhciCtlBlock
) {
188 KdPrint2((PRINT_PREFIX
" already initialized %x\n", chan
->AhciCtlBlock
));
191 // Need 1K-byte alignment
192 chan
->AhciCtlBlock0
= (PIDE_AHCI_CHANNEL_CTL_BLOCK
)MmAllocateContiguousMemory(
193 sizeof(IDE_AHCI_CHANNEL_CTL_BLOCK
)+AHCI_CLB_ALIGNEMENT_MASK
,
195 if(chan
->AhciCtlBlock0
) {
198 ULONGLONG AhciCtlBlock64
;
201 AhciCtlBlock
= (PUCHAR
)chan
->AhciCtlBlock0
;
203 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: CLP BASE %I64x\n", AhciCtlBlock64
));
205 AhciCtlBlock64
+= AHCI_CLB_ALIGNEMENT_MASK
;
206 AhciCtlBlock64
&= ~AHCI_CLB_ALIGNEMENT_MASK
;
208 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: CLP BASE 1k-aligned %I64x\n", AhciCtlBlock64
));
210 chan
->AhciCtlBlock
= (PIDE_AHCI_CHANNEL_CTL_BLOCK
)AhciCtlBlock
;
212 chan
->AHCI_CTL_PhAddr
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)(chan
->AhciCtlBlock
), &i
, &ph_addru
);
213 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: CLP Phys BASE %I64x\n", chan
->AHCI_CTL_PhAddr
));
214 if(!chan
->AHCI_CTL_PhAddr
|| !i
|| ((LONG
)(chan
->AHCI_CTL_PhAddr
) == -1)) {
215 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No AHCI CLP BASE\n" ));
216 chan
->AhciCtlBlock
= NULL
;
217 chan
->AHCI_CTL_PhAddr
= 0;
221 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No AHCI CLP below 4Gb\n" ));
222 MmFreeContiguousMemory(chan
->AhciCtlBlock0
);
223 chan
->AhciCtlBlock
= NULL
;
224 chan
->AHCI_CTL_PhAddr
= 0;
228 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: Can't alloc AHCI CLP\n"));
233 } // end AtapiDmaAlloc()
238 IN PVOID HwDeviceExtension
,
239 IN ULONG DeviceNumber
,
240 IN ULONG lChannel
, // logical channel,
241 IN PSCSI_REQUEST_BLOCK Srb
,
243 IN ULONG count
/* bytes */
246 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
247 ULONG dma_count
, dma_base
, dma_baseu
;
248 ULONG dma_count0
, dma_base0
;
250 PHW_CHANNEL chan
= &(deviceExtension
->chan
[lChannel
]);
251 PATA_REQ AtaReq
= (PATA_REQ
)(Srb
->SrbExtension
);
252 BOOLEAN use_DB_IO
= FALSE
;
253 BOOLEAN use_AHCI
= (deviceExtension
->HwFlags
& UNIATA_AHCI
) ? TRUE
: FALSE
;
254 ULONG orig_count
= count
;
255 ULONG max_entries
= use_AHCI
? ATA_AHCI_DMA_ENTRIES
: ATA_DMA_ENTRIES
;
256 //ULONG max_frag = use_AHCI ? (0x3fffff+1) : (4096); // DEBUG, replace 4096 for procer chipset-specific value
257 ULONG max_frag
= deviceExtension
->DmaSegmentLength
;
258 ULONG seg_align
= deviceExtension
->DmaSegmentAlignmentMask
;
260 if(AtaReq
->dma_entries
) {
261 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: already setup, %d entries\n", AtaReq
->dma_entries
));
264 AtaReq
->ata
.dma_base
= 0;
265 AtaReq
->Flags
&= ~REQ_FLAG_DMA_OPERATION
;
267 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: mode %#x, data %x, count %x, lCh %x, dev %x\n",
268 chan
->lun
[DeviceNumber
]->TransferMode
,
269 data
, count
, lChannel
, DeviceNumber
));
270 if(chan
->lun
[DeviceNumber
]->TransferMode
< ATA_DMA
) {
271 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: Not DMA mode, assume this is just preparation\n" ));
274 //KdPrint2((PRINT_PREFIX " checkpoint 1\n" ));
276 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: count=0\n" ));
279 //KdPrint2((PRINT_PREFIX " checkpoint 2\n" ));
280 if(count
> deviceExtension
->MaximumDmaTransferLength
) {
281 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: deviceExtension->MaximumDmaTransferLength > count\n" ));
284 //KdPrint2((PRINT_PREFIX " checkpoint 3\n" ));
285 if((ULONG
)data
& deviceExtension
->AlignmentMask
) {
286 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: unaligned data: %#x (%#x)\n", data
, deviceExtension
->AlignmentMask
));
290 //KdPrint2((PRINT_PREFIX " checkpoint 4\n" ));
292 KdPrint2((PRINT_PREFIX
" get Phys(AHCI_CMD=%x)\n", AtaReq
->ahci
.ahci_cmd_ptr
));
293 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)(AtaReq
->ahci
.ahci_cmd_ptr
), &i
, &dma_baseu
);
294 AtaReq
->ahci
.ahci_base64
= 0; // clear before setup
296 KdPrint2((PRINT_PREFIX
" get Phys(PRD=%x)\n", &(AtaReq
->dma_tab
) ));
297 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)&(AtaReq
->dma_tab
) /*chan->dma_tab*/, &i
, &dma_baseu
);
300 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: SRB built-in PRD above 4Gb: %8.8x%8.8x\n", dma_baseu
, dma_base
));
301 if(!deviceExtension
->Host64
) {
302 dma_base
= chan
->DB_PRD_PhAddr
;
303 AtaReq
->Flags
|= REQ_FLAG_DMA_DBUF_PRD
;
307 if(!dma_base
|| !i
|| ((LONG
)(dma_base
) == -1)) {
308 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: No BASE\n" ));
311 AtaReq
->ata
.dma_base
= dma_base
; // aliased to AtaReq->ahci.ahci_base64
313 KdPrint2((PRINT_PREFIX
" get Phys(data[0]=%x)\n", data
));
314 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, Srb
, data
, &dma_count
, &dma_baseu
);
316 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: 1st block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu
, dma_base
));
317 if(!deviceExtension
->Host64
) {
320 dma_base
= chan
->DB_IO_PhAddr
;
321 data
= (PUCHAR
)(chan
->DB_IO
);
323 AtaReq
->ahci
.ahci_base64
= (ULONGLONG
)dma_base
| ((ULONGLONG
)dma_baseu
<< 32);
326 if(!dma_count
|| ((LONG
)(dma_base
) == -1)) {
327 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: No 1st block\n" ));
328 //AtaReq->dma_base = NULL;
329 AtaReq
->ahci
.ahci_base64
= NULL
;
333 dma_count
= min(count
, (PAGE_SIZE
- ((ULONG
)data
& PAGE_MASK
)));
338 dma_count0
= dma_count
;
339 dma_base0
= dma_base
;
342 /* KdPrint2((PRINT_PREFIX " segments %#x+%#x == %#x && %#x+%#x <= %#x\n",
343 dma_base0, dma_count0, dma_base,
344 dma_count0, dma_count, max_frag));*/
345 if(dma_base0
+dma_count0
== dma_base
&&
346 dma_count0
+dma_count
<= max_frag
) {
347 // 'i' should be always > 0 here
348 // for BM we cannot cross 64k boundary
349 if(dma_base
& seg_align
) {
350 //KdPrint2((PRINT_PREFIX " merge segments\n" ));
354 dma_base
= dma_base0
;
355 dma_count
+= dma_count0
;
359 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].base
= dma_base
;
360 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].baseu
= dma_baseu
;
361 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].Reserved1
= 0;
362 *((PULONG
)&(AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].DBC_ULONG
)) = ((dma_count
-1) & 0x3fffff);
363 /* AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved2 = 0;
364 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].I = 0;*/
365 KdPrint2((PRINT_PREFIX
" ph data[%d]=%x:%x (%x)\n", i
, dma_baseu
, dma_base
, AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].DBC
));
367 AtaReq
->dma_tab
[i
].base
= dma_base
;
368 AtaReq
->dma_tab
[i
].count
= (dma_count
& 0xffff);
370 dma_count0
= dma_count
;
371 dma_base0
= dma_base
;
373 if (i
>= max_entries
) {
374 KdPrint2((PRINT_PREFIX
"too many segments in DMA table\n" ));
375 //AtaReq->dma_base = NULL;
376 AtaReq
->ahci
.ahci_base64
= NULL
;
379 KdPrint2((PRINT_PREFIX
" get Phys(data[n=%d]=%x)\n", i
, data
));
380 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, Srb
, data
, &dma_count
, &dma_baseu
);
382 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu
, dma_base
));
383 if(!deviceExtension
->Host64
) {
385 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: *ERROR* special buffer above 4Gb: %8.8x%8.8x\n", dma_baseu
, dma_base
));
392 if(!dma_count
|| !dma_base
|| ((LONG
)(dma_base
) == -1)) {
393 //AtaReq->dma_base = NULL;
394 AtaReq
->ahci
.ahci_base64
= 0;
395 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: No NEXT block\n" ));
399 dma_count
= min(count
, PAGE_SIZE
);
400 data
+= min(count
, PAGE_SIZE
);
401 count
-= min(count
, PAGE_SIZE
);
403 KdPrint2((PRINT_PREFIX
" set TERM\n" ));
404 /* KdPrint2((PRINT_PREFIX " segments %#x+%#x == %#x && #x+%#x <= %#x\n",
405 dma_base0, dma_count0, dma_base,
406 dma_count0, dma_count, max_frag));*/
407 if(dma_base0
+dma_count0
== dma_base
&&
408 dma_count0
+dma_count
<= max_frag
) {
409 // 'i' should be always > 0 here
410 if(dma_base
& seg_align
) {
411 //KdPrint2((PRINT_PREFIX " merge segments\n" ));
415 dma_base
= dma_base0
;
416 dma_count
+= dma_count0
;
420 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].base
= dma_base
;
421 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].baseu
= dma_baseu
;
422 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].Reserved1
= 0;
423 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC = ((dma_count-1) & 0x3fffff);
424 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved2 = 0;
425 *((PULONG
)&(AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].DBC_ULONG
)) = ((dma_count
-1) & 0x3fffff);
426 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].I = 1; // interrupt when ready
427 KdPrint2((PRINT_PREFIX
" ph data[%d]=%x:%x (%x)\n", i
, dma_baseu
, dma_base
, AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].DBC
));
428 if(((ULONG
)&(AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
) & ~PAGE_MASK
) != ((ULONG
)&(AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
]) & ~PAGE_MASK
)) {
429 KdPrint2((PRINT_PREFIX
"PRD table crosses page boundary! %x vs %x\n",
430 &AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
, &(AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
]) ));
431 //AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
434 AtaReq
->dma_tab
[i
].base
= dma_base
;
435 AtaReq
->dma_tab
[i
].count
= (dma_count
& 0xffff) | ATA_DMA_EOT
;
436 if(((ULONG
)&(AtaReq
->dma_tab
) & ~PAGE_MASK
) != ((ULONG
)&(AtaReq
->dma_tab
[i
]) & ~PAGE_MASK
)) {
437 KdPrint2((PRINT_PREFIX
"DMA table crosses page boundary! %x vs %x\n",
438 &AtaReq
->dma_tab
, &(AtaReq
->dma_tab
[i
]) ));
439 //AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
442 AtaReq
->dma_entries
= i
+1;
445 AtaReq
->Flags
|= REQ_FLAG_DMA_DBUF
;
447 AtaReq
->Flags
|= REQ_FLAG_DMA_OPERATION
;
449 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: OK\n" ));
452 } // end AtapiDmaSetup()
457 PVOID HwDeviceExtension
,
458 PSCSI_REQUEST_BLOCK Srb
,
464 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
471 // This must never be called after DMA operation !!!
472 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: data %#x, len %#x\n", data
, count
));
475 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: !Srb\n" ));
479 AtaReq
= (PATA_REQ
)(Srb
->SrbExtension
);
481 // do nothing on PCI (This can be changed. We cannot guarantee,
482 // that CommonBuffer will always point to User's buffer,
483 // however, this usually happens on PCI-32)
484 if(deviceExtension
->OrigAdapterInterfaceType
== PCIBus
) {
487 // do nothing for DMA
488 if(AtaReq
->Flags
& REQ_FLAG_DMA_OPERATION
) {
493 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: !data\n" ));
498 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, Srb
, data
, &dma_count
);
500 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: !dma_base for data %#x\n", data
));
503 DmaBuffer
= (PUCHAR
)ScsiPortGetVirtualAddress(HwDeviceExtension
,
504 ScsiPortConvertUlongToPhysicalAddress(dma_base
));
506 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: !DmaBuffer for dma_base %#x\n", dma_base
));
509 len
= min(dma_count
, count
);
510 memcpy(DmaBuffer
, data
, len
);
517 } // end AtapiDmaPioSync()
523 PSCSI_REQUEST_BLOCK Srb
528 AtaReq
= (PATA_REQ
)(Srb
->SrbExtension
);
529 if((Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) &&
530 (AtaReq
->Flags
& REQ_FLAG_DMA_DBUF
)) {
531 KdPrint2((PRINT_PREFIX
" AtapiDmaDBSync is issued.\n"));
533 KdPrint2((PRINT_PREFIX
" DBUF (Read)\n"));
534 RtlCopyMemory(AtaReq
->DataBuffer
, chan
->DB_IO
,
535 Srb
->DataTransferLength
);
538 } // end AtapiDmaDBSync()
543 IN PVOID HwDeviceExtension
,
544 IN ULONG DeviceNumber
,
545 IN ULONG lChannel
, // logical channel,
546 IN PSCSI_REQUEST_BLOCK Srb
549 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
550 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
551 PATA_REQ AtaReq
= (PATA_REQ
)(Srb
->SrbExtension
);
552 PHW_CHANNEL chan
= &deviceExtension
->chan
[lChannel
];
554 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
555 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
557 KdPrint2((PRINT_PREFIX
"AtapiDmaStart: %s on %#x:%#x\n",
558 (Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) ? "read" : "write",
559 lChannel
, DeviceNumber
));
561 if(!AtaReq
->ata
.dma_base
) {
562 KdPrint2((PRINT_PREFIX
"AtapiDmaStart: *** !AtaReq->ata.dma_base\n"));
565 if(AtaReq
->Flags
& REQ_FLAG_DMA_DBUF_PRD
) {
566 KdPrint2((PRINT_PREFIX
" DBUF_PRD\n"));
568 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
569 RtlCopyMemory(chan
->DB_PRD
, AtaReq
->ahci
.ahci_cmd_ptr
, sizeof(AtaReq
->ahci_cmd0
));
571 RtlCopyMemory(chan
->DB_PRD
, &(AtaReq
->dma_tab
), sizeof(AtaReq
->dma_tab
));
574 if(!(Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) &&
575 (AtaReq
->Flags
& REQ_FLAG_DMA_DBUF
)) {
576 KdPrint2((PRINT_PREFIX
" DBUF (Write)\n"));
578 RtlCopyMemory(chan
->DB_IO
, AtaReq
->DataBuffer
,
579 Srb
->DataTransferLength
);
583 chan
->ChannelCtrlFlags
|= CTRFLAGS_DMA_ACTIVE
;
587 if(ChipType
== PRNEW
) {
588 ULONG Channel
= deviceExtension
->Channel
+ lChannel
;
589 if(chan
->ChannelCtrlFlags
& CTRFLAGS_LBA48
) {
590 AtapiWritePortEx1(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11,
591 AtapiReadPortEx1(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11) |
592 (Channel
? 0x08 : 0x02));
593 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),(Channel
? 0x24 : 0x20),
594 ((Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) ? 0x05000000 : 0x06000000) | (Srb
->DataTransferLength
>> 1)
599 if(deviceExtension->MemIo) {
601 AtapiWritePort4(chan,
603 (AtapiReadPort4(chan,
604 IDX_BM_Command) & ~0x000000c0) |
605 ((Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x00000080 : 0x000000c0) );
612 // set pointer to Pointer Table
613 AtapiWritePort4(chan
, IDX_BM_PRD_Table
,
616 // set transfer direction
617 AtapiWritePort1(chan
, IDX_BM_Command
,
618 (Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) ? BM_COMMAND_READ
: BM_COMMAND_WRITE
);
619 // clear Error & Intr bits (writeing 1 clears bits)
620 // set DMA capability bit
621 AtapiWritePort1(chan
, IDX_BM_Status
,
622 AtapiReadPort1(chan
, IDX_BM_Status
) |
623 (BM_STATUS_INTR
| BM_STATUS_ERR
) /*|
624 (DeviceNumber ? BM_STATUS_DRIVE_1_DMA : BM_STATUS_DRIVE_0_DMA)*/);
626 AtapiWritePort1(chan
, IDX_BM_Command
,
627 AtapiReadPort1(chan
, IDX_BM_Command
) |
628 BM_COMMAND_START_STOP
);
631 } // end AtapiDmaStart()
636 IN PVOID HwDeviceExtension
,
637 IN ULONG DeviceNumber
,
638 IN ULONG lChannel
, // logical channel,
639 IN PSCSI_REQUEST_BLOCK Srb
642 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
643 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
644 PHW_CHANNEL chan
= &deviceExtension
->chan
[lChannel
];
647 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
648 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
650 KdPrint2((PRINT_PREFIX
"AtapiDmaDone: dev %d\n", DeviceNumber
));
652 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
653 KdPrint2((PRINT_PREFIX
" ACHTUNG! should not be called for AHCI!\n"));
654 return IDE_STATUS_WRONG
;
659 if(ChipType
== PRNEW
) {
660 ULONG Channel
= deviceExtension
->Channel
+ lChannel
;
661 if(chan
->ChannelCtrlFlags
& CTRFLAGS_LBA48
) {
662 AtapiWritePortEx1(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11,
663 AtapiReadPortEx1(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11) &
664 ~(Channel
? 0x08 : 0x02));
665 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),(Channel
? 0x24 : 0x20),
671 if(deviceExtension->MemIo) {
673 AtapiWritePort4(chan,
675 (AtapiReadPort4(chan,
676 IDX_BM_Command) & ~0x00000080) );
678 chan->ChannelCtrlFlags &= ~CTRFLAGS_DMA_ACTIVE;
686 dma_status
= AtapiReadPort1(chan
, IDX_BM_Status
) & BM_STATUS_MASK
;
688 AtapiWritePort1(chan
, IDX_BM_Command
,
689 AtapiReadPort1(chan
, IDX_BM_Command
) &
690 ~BM_COMMAND_START_STOP
);
691 // clear interrupt and error status
692 AtapiWritePort1(chan
, IDX_BM_Status
, BM_STATUS_ERR
| BM_STATUS_INTR
);
694 chan
->ChannelCtrlFlags
&= ~CTRFLAGS_DMA_ACTIVE
;
698 } // end AtapiDmaDone()
703 IN PHW_DEVICE_EXTENSION deviceExtension
,
704 IN PHW_LU_EXTENSION LunExt
,
710 if((deviceExtension
->HwFlags
& UNIATA_AHCI
) &&
711 !(LunExt
->DeviceFlags
& DFLAGS_ATAPI_DEVICE
)) {
712 // skip unnecessary checks
713 KdPrint2((PRINT_PREFIX
"AtapiDmaReinit: ahci, nothing to do for HDD\n"));
717 apiomode
= (CHAR
)AtaPioMode(&(LunExt
->IdentifyData
));
719 if(!(AtaReq
->Flags
& REQ_FLAG_DMA_OPERATION
)) {
720 KdPrint2((PRINT_PREFIX
721 "AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device %d\n", LunExt
->Lun
));
724 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
725 if(!AtaReq
->ahci
.ahci_base64
) {
726 KdPrint2((PRINT_PREFIX
727 "AtapiDmaReinit: no AHCI PRD, fatal on Device %d\n", LunExt
->Lun
));
731 if(!AtaReq
->ata
.dma_base
) {
732 KdPrint2((PRINT_PREFIX
733 "AtapiDmaReinit: no PRD, fall to PIO on Device %d\n", LunExt
->Lun
));
737 if((deviceExtension
->HbaCtrlFlags
& HBAFLAGS_DMA_DISABLED_LBA48
) &&
738 (AtaReq
->lba
>= (LONGLONG
)ATA_MAX_LBA28
) &&
739 (LunExt
->TransferMode
> ATA_PIO5
) ) {
740 KdPrint2((PRINT_PREFIX
741 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d for LBA48\n", LunExt
->Lun
));
746 if(AtaReq
->Flags
& REQ_FLAG_FORCE_DOWNRATE
) {
747 KdPrint2((PRINT_PREFIX
748 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d\n", LunExt
->Lun
));
749 if(AtaReq
->lba
>= (LONGLONG
)ATA_MAX_LBA28
) {
751 LunExt
->DeviceFlags
|= REQ_FLAG_FORCE_DOWNRATE_LBA48
;
753 // do not make extra work if we already use PIO
754 if(/*LunExt->TransferMode >= ATA_DMA*/
755 (LunExt
->TransferMode
> ATA_PIO5
) && (LunExt
->TransferMode
!= ATA_PIO0
+apiomode
)
757 KdPrint2((PRINT_PREFIX
758 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x)\n", LunExt
->Lun
, LunExt
->TransferMode
, ATA_PIO0
+apiomode
));
759 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
764 if(LunExt
->LimitedTransferMode
< LunExt
->TransferMode
) {
765 KdPrint2((PRINT_PREFIX
766 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x) (2)\n", LunExt
->Lun
, LunExt
->TransferMode
, LunExt
->LimitedTransferMode
));
767 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
768 LunExt
->LimitedTransferMode
-ATA_PIO0
,
774 KdPrint2((PRINT_PREFIX
775 "AtapiDmaReinit: set MAX mode on Device %d\n", LunExt
->Lun
));
776 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
778 min( retry_Wdma
[AtaReq
->retry
],
779 (CHAR
)AtaWmode(&(LunExt
->IdentifyData
)) ),
780 min( retry_Udma
[AtaReq
->retry
],
781 (CHAR
)AtaUmode(&(LunExt
->IdentifyData
)) ) );
783 // LunExt->DeviceFlags &= ~DFLAGS_FORCE_DOWNRATE;
785 if(/*!(LunExt->DeviceFlags & DFLAGS_FORCE_DOWNRATE) &&*/
786 (LunExt
->LimitedTransferMode
>
787 LunExt
->TransferMode
) ||
788 (LunExt
->DeviceFlags
& DFLAGS_REINIT_DMA
)) {
790 KdPrint2((PRINT_PREFIX
791 "AtapiDmaReinit: restore IO mode on Device %d\n", LunExt
->Lun
));
792 AtapiDmaInit__(deviceExtension
, LunExt
);
797 } // end AtapiDmaReinit()
802 IN PHW_DEVICE_EXTENSION deviceExtension
,
803 IN PHW_LU_EXTENSION LunExt
806 if(LunExt
->IdentifyData
.SupportDma
||
807 (LunExt
->IdentifyData
.AtapiDMA
.DMASupport
&& (LunExt
->DeviceFlags
& DFLAGS_ATAPI_DEVICE
))) {
808 KdPrint2((PRINT_PREFIX
809 "AtapiDmaInit__: Set (U)DMA on Device %d\n", LunExt
->Lun
));
810 /* for(i=AtaUmode(&(LunExt->IdentifyData)); i>=0; i--) {
811 AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
812 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
813 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
814 UDMA_MODE0+(CHAR)i );
816 for(i=AtaWmode(&(LunExt->IdentifyData)); i>=0; i--) {
817 AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
818 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
819 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
820 UDMA_MODE0+(CHAR)i );
822 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
823 (CHAR
)AtaPioMode(&(LunExt
->IdentifyData
)),
824 (CHAR
)AtaWmode(&(LunExt
->IdentifyData
)),
825 (CHAR
)AtaUmode(&(LunExt
->IdentifyData
)) );
827 KdPrint2((PRINT_PREFIX
828 "AtapiDmaInit__: Set PIO on Device %d\n", LunExt
->Lun
));
829 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
830 (CHAR
)AtaPioMode(&(LunExt
->IdentifyData
)), -1, -1);
832 } // end AtapiDmaInit__()
837 IN PHW_DEVICE_EXTENSION deviceExtension
,
838 IN ULONG DeviceNumber
,
839 IN ULONG lChannel
, // logical channel,
840 IN PHW_LU_EXTENSION LunExt
,
844 KdPrint3((PRINT_PREFIX
845 "AtaSetTransferMode: Set %#x on Device %d/%d\n", mode
, lChannel
, DeviceNumber
));
849 if(LunExt
->DeviceFlags
& DFLAGS_MANUAL_CHS
) {
850 statusByte
= mode
<= ATA_PIO2
? IDE_STATUS_IDLE
: IDE_STATUS_ERROR
;
852 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
853 AtapiDisableInterrupts(deviceExtension
, lChannel
);
855 statusByte
= AtaCommand(deviceExtension
, DeviceNumber
, lChannel
,
856 IDE_COMMAND_SET_FEATURES
, 0, 0, 0,
857 (UCHAR
)((mode
> ATA_UDMA6
) ? ATA_UDMA6
: mode
), ATA_C_F_SETXFER
, ATA_WAIT_BASE_READY
);
858 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
859 AtapiEnableInterrupts(deviceExtension
, lChannel
);
862 if(statusByte
& IDE_STATUS_ERROR
) {
863 KdPrint3((PRINT_PREFIX
" wait ready after error\n"));
864 if(LunExt
->DeviceFlags
& DFLAGS_ATAPI_DEVICE
) {
865 AtapiStallExecution(10);
867 AtapiStallExecution(100);
869 apiomode
= (CHAR
)AtaPioMode(&(LunExt
->IdentifyData
));
870 if( (apiomode
> 0) &&
871 ((CHAR
)AtaWmode(&(LunExt
->IdentifyData
)) > 0) &&
872 ((CHAR
)AtaUmode(&(LunExt
->IdentifyData
)) > 0)
876 if(mode
> ATA_PIO2
) {
879 KdPrint3((PRINT_PREFIX
" assume that drive doesn't support mode swithing using PIO%d\n", apiomode
));
880 mode
= ATA_PIO0
+ apiomode
;
882 // SATA sets actual transfer rate in LunExt on init.
883 // There is no run-time SATA rate adjustment yet.
884 // On the other hand, we may turn SATA device in PIO mode
885 LunExt
->TransferMode
= (UCHAR
)mode
;
886 if(deviceExtension
->HwFlags
& UNIATA_SATA
) {
887 if(mode
< ATA_SA150
) {
888 LunExt
->PhyTransferMode
= max(LunExt
->PhyTransferMode
, LunExt
->TransferMode
);
890 LunExt
->PhyTransferMode
= LunExt
->TransferMode
;
893 if(LunExt
->DeviceFlags
& DFLAGS_ATAPI_DEVICE
) {
894 LunExt
->PhyTransferMode
= max(LunExt
->LimitedTransferMode
, LunExt
->TransferMode
);
896 LunExt
->PhyTransferMode
= LunExt
->TransferMode
;
900 } // end AtaSetTransferMode()
905 IN PVOID HwDeviceExtension
,
906 IN ULONG DeviceNumber
,
907 IN ULONG lChannel
, // logical channel,
908 // is always 0 except simplex-only controllers
914 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
915 ULONG Channel
= deviceExtension
->Channel
+ lChannel
;
916 PHW_CHANNEL chan
= &deviceExtension
->chan
[lChannel
];
917 //LONG statusByte = 0;
918 ULONG dev
= Channel
*2 + DeviceNumber
; // for non-SATA/AHCI only!
919 //ULONG ldev = lChannel*2 + DeviceNumber; // for non-SATA/AHCI only!
920 BOOLEAN isAtapi
= ATAPI_DEVICE(chan
, DeviceNumber
);
921 ULONG slotNumber
= deviceExtension
->slotNumber
;
922 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
924 PHW_LU_EXTENSION LunExt
= chan
->lun
[DeviceNumber
];
927 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
928 //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
929 //ULONG RevID = deviceExtension->RevID;
930 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
931 ULONG ChipFlags
= deviceExtension
->HwFlags
& CHIPFLAG_MASK
;
935 //UCHAR *reg_val = NULL;
937 LunExt
->DeviceFlags
&= ~DFLAGS_REINIT_DMA
;
938 /* set our most pessimistic default mode */
939 LunExt
->TransferMode
= ATA_PIO
;
940 // if(!deviceExtension->BaseIoAddressBM[lChannel]) {
941 if(!deviceExtension
->BusMaster
) {
942 KdPrint2((PRINT_PREFIX
" !deviceExtension->BusMaster: NO DMA\n"));
943 wdmamode
= udmamode
= -1;
946 // Limit transfer mode (controller limitation)
947 if((LONG
)chan
->MaxTransferMode
>= ATA_UDMA
) {
948 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA\n"));
949 udmamode
= min( udmamode
, (CHAR
)(chan
->MaxTransferMode
- ATA_UDMA
));
951 if((LONG
)chan
->MaxTransferMode
>= ATA_WDMA
) {
952 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: chan->MaxTransferMode >= ATA_WDMA\n"));
954 wdmamode
= min( wdmamode
, (CHAR
)(chan
->MaxTransferMode
- ATA_WDMA
));
956 if((LONG
)chan
->MaxTransferMode
>= ATA_PIO0
) {
957 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: NO DMA\n"));
958 wdmamode
= udmamode
= -1;
959 apiomode
= min( apiomode
, (CHAR
)(chan
->MaxTransferMode
- ATA_PIO0
));
961 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: PIO0\n"));
962 wdmamode
= udmamode
= -1;
965 // Limit transfer mode (device limitation)
966 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: LunExt->LimitedTransferMode %#x\n", LunExt
->LimitedTransferMode
));
967 if((LONG
)LunExt
->LimitedTransferMode
>= ATA_UDMA
) {
968 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => %#x\n",
969 min( udmamode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_UDMA
))
971 udmamode
= min( udmamode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_UDMA
));
973 if((LONG
)LunExt
->LimitedTransferMode
>= ATA_WDMA
) {
974 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: LunExt->MaxTransferMode >= ATA_WDMA => %#x\n",
975 min( wdmamode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_WDMA
))
978 wdmamode
= min( wdmamode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_WDMA
));
980 if((LONG
)LunExt
->LimitedTransferMode
>= ATA_PIO0
) {
981 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: lun NO DMA\n"));
982 wdmamode
= udmamode
= -1;
983 apiomode
= min( apiomode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_PIO0
));
985 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: lun PIO0\n"));
986 wdmamode
= udmamode
= -1;
990 //if(!(ChipFlags & UNIATA_AHCI)) {
992 // this is necessary for future PM support
993 SelectDrive(chan
, DeviceNumber
);
994 GetStatus(chan
, statusByte
);
995 // we can see here IDE_STATUS_ERROR status after previous operation
996 if(statusByte
& IDE_STATUS_ERROR
) {
997 KdPrint2((PRINT_PREFIX
"IDE_STATUS_ERROR detected on entry, statusByte = %#x\n", statusByte
));
998 //GetBaseStatus(chan, statusByte);
1000 if(statusByte
&& UniataIsIdle(deviceExtension
, statusByte
& ~IDE_STATUS_ERROR
) != IDE_STATUS_IDLE
) {
1001 KdPrint2((PRINT_PREFIX
"Can't setup transfer mode: statusByte = %#x\n", statusByte
));
1006 if(UniataIsSATARangeAvailable(deviceExtension
, lChannel
) ||
1007 (ChipFlags
& UNIATA_AHCI
) || (chan
->MaxTransferMode
>= ATA_SA150
)
1009 //if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI)) {
1014 KdPrint2((PRINT_PREFIX
"SATA Generic\n"));
1015 if((udmamode
>= 5) || (ChipFlags
& UNIATA_AHCI
) || ((udmamode
>= 0) && (chan
->MaxTransferMode
>= ATA_SA150
))) {
1016 /* some drives report UDMA6, some UDMA5 */
1017 /* ATAPI may not have SataCapabilities set in IDENTIFY DATA */
1018 if(ata_is_sata(&(LunExt
->IdentifyData
))) {
1019 //udmamode = min(udmamode, 6);
1020 KdPrint2((PRINT_PREFIX
"LunExt->LimitedTransferMode %x, LunExt->OrigTransferMode %x\n",
1021 LunExt
->LimitedTransferMode
, LunExt
->OrigTransferMode
));
1022 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, min(LunExt
->LimitedTransferMode
, LunExt
->OrigTransferMode
))) {
1025 udmamode
= min(udmamode
, 6);
1028 KdPrint2((PRINT_PREFIX
"SATA -> PATA adapter ?\n"));
1029 if (udmamode
> 2 && (!LunExt
->IdentifyData
.HwResCableId
&& (LunExt
->IdentifyData
.HwResValid
== IDENTIFY_CABLE_ID_VALID
) )) {
1030 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
1032 apiomode
= min( apiomode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_PIO0
));
1034 udmamode
= min(udmamode
, 6);
1039 ModeByte
= ATA_UDMA0
+ udmamode
;
1042 ModeByte
= ATA_WDMA0
+ wdmamode
;
1045 ModeByte
= ATA_PIO0
+ apiomode
;
1050 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ModeByte
);
1054 if(deviceExtension
->UnknownDev
) {
1055 KdPrint2((PRINT_PREFIX
"Unknown chip, omit Vendor/Dev checks\n"));
1056 goto try_generic_dma
;
1059 if(udmamode
> 2 && (!LunExt
->IdentifyData
.HwResCableId
&& (LunExt
->IdentifyData
.HwResValid
== IDENTIFY_CABLE_ID_VALID
)) ) {
1060 if(ata_is_sata(&(LunExt
->IdentifyData
))) {
1061 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: SATA beyond adapter or Controller compat mode\n"));
1063 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
1065 apiomode
= min( apiomode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_PIO
));
1069 KdPrint2((PRINT_PREFIX
"Setup chip a:w:u=%d:%d:%d\n",
1075 case ATA_ACARD_ID
: {
1079 static const USHORT reg4a
= 0xa6;
1080 UCHAR reg
= 0x40 + (UCHAR
)dev
;
1082 if(ChipType
== ATPOLD
) {
1084 static const USHORT reg4x
= 0x0301;
1086 for(i
=udmamode
; i
>=0; i
--) {
1087 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA
+ i
)) {
1089 ChangePciConfig1(0x54, a
| (0x01 << dev
) | ((i
+1) << (dev
*2)));
1090 SetPciConfig1(0x4a, reg4a
);
1091 SetPciConfig2(reg
, reg4x
);
1096 if (wdmamode
>= 2 && apiomode
>= 4) {
1097 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1103 static const UCHAR reg4x
= 0x31;
1105 for(i
=udmamode
; i
>=0; i
--) {
1106 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA
+ i
)) {
1108 ChangePciConfig2(0x44, (a
& ~(0x000f << (dev
* 4))) | ((i
+1) << (dev
*4)));
1109 SetPciConfig1(0x4a, reg4a
);
1110 SetPciConfig1(reg
, reg4x
);
1115 if (wdmamode
>= 2 && apiomode
>= 4) {
1116 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1121 /* Use GENERIC PIO */
1123 case ATA_ACER_LABS_ID
: {
1124 /************************/
1125 /* Acer Labs Inc. (ALI) */
1126 /************************/
1127 static const UCHAR ali_udma
[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
1128 static const ULONG ali_pio
[] =
1129 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1130 0x00310001, 0x00440001};
1131 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
1132 if ((ChipFlags
& ALIOLD
) &&
1133 (udmamode
>= 0 || wdmamode
>= 0)) {
1134 if(ATAPI_DEVICE(chan
, 0) &&
1135 ATAPI_DEVICE(chan
, 1)) {
1136 // 2 devices on this channel - NO DMA
1137 chan
->MaxTransferMode
=
1138 min(chan
->MaxTransferMode
, ATA_PIO4
);
1139 udmamode
= wdmamode
= -1;
1143 for(i
=udmamode
; i
>=0; i
--) {
1144 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1147 GetPciConfig4(0x54, word54
);
1148 word54
&= ~(0x000f000f << (dev
* 4));
1149 word54
|= (((ali_udma
[i
]<<16) | 5) << (dev
* 4));
1150 SetPciConfig4(0x54, word54
);
1151 ChangePciConfig1(0x53, a
| 0x03);
1152 SetPciConfig4(0x58 + (Channel
<<2), 0x00310001);
1156 /* make sure eventual UDMA mode from the BIOS is disabled */
1157 ChangePciConfig2(0x56, a
& ~(0x0008 << (dev
* 4)) );
1158 if (wdmamode
>= 2 && apiomode
>= 4) {
1159 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1160 ChangePciConfig1(0x53, a
| 0x03);
1161 chan
->ChannelCtrlFlags
|= CTRFLAGS_DMA_RO
;
1165 ChangePciConfig1(0x53, (a
& ~0x01) | 0x02);
1167 for(i
=apiomode
; i
>=0; i
--) {
1168 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ i
)) {
1169 ChangePciConfig4(0x54, a
& ~(0x0008000f << (dev
* 4)));
1170 SetPciConfig4(0x58 + (Channel
<<2), ali_pio
[i
]);
1179 /********************/
1180 /* AMD, nVidia, VIA */
1181 /********************/
1182 if((VendorID
== ATA_VIA_ID
) &&
1183 (ChipFlags
& VIASATA
) &&
1185 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_SA150
);
1189 static const UCHAR via_modes
[5][7] = {
1190 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 and New Chips */
1191 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* ATA66 */
1192 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* ATA100 */
1193 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
1194 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
1195 static const UCHAR via_pio
[] =
1196 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
1197 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1198 const UCHAR
*reg_val
= NULL
;
1199 UCHAR reg
= 0x53-(UCHAR
)dev
;
1201 reg_val
= &via_modes
[ChipType
][0];
1203 if(VendorID
== ATA_NVIDIA_ID
)
1206 for(i
= udmamode
; i
>=0; i
--) {
1207 SetPciConfig1(reg
-0x08, via_pio
[8+i
]);
1208 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1209 SetPciConfig1(reg
, (UCHAR
)reg_val
[i
]);
1213 if(!(ChipFlags
& VIABAR
)) {
1214 /* This chip can't do WDMA. */
1215 for(i
= wdmamode
; i
>=0; i
--) {
1216 SetPciConfig1(reg
-0x08, via_pio
[5+i
]);
1217 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1218 SetPciConfig1(reg
, 0x8b);
1223 /* set PIO mode timings */
1224 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1225 if((apiomode
>= 0) && (ChipType
!= VIA133
)) {
1226 SetPciConfig1(reg
-0x08, via_pio
[apiomode
]);
1228 via82c_timing(deviceExtension
, dev
, ATA_PIO0
+ apiomode
);
1229 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1233 case ATA_CYRIX_ID
: {
1237 ULONG cyr_piotiming
[] =
1238 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1239 ULONG cyr_wdmatiming
[] = { 0x00077771, 0x00012121, 0x00002020 };
1240 ULONG cyr_udmatiming
[] = { 0x00921250, 0x00911140, 0x00911030 };
1241 ULONG mode_reg
= 0x24+(dev
<< 3);
1245 for(i
=udmamode
; i
>=0; i
--) {
1246 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1247 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
), mode_reg
, cyr_udmatiming
[udmamode
]);
1251 for(i
=wdmamode
; i
>=0; i
--) {
1252 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1253 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
), mode_reg
, cyr_wdmatiming
[wdmamode
]);
1257 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
)) {
1258 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
), mode_reg
, cyr_piotiming
[apiomode
]);
1264 case ATA_NATIONAL_ID
: {
1268 ULONG nat_piotiming
[] =
1269 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1270 0x00803020, 0x20102010, 0x00100010,
1271 0x00100010, 0x00100010, 0x00100010 };
1272 ULONG nat_dmatiming
[] = { 0x80077771, 0x80012121, 0x80002020 };
1273 ULONG nat_udmatiming
[] = { 0x80921250, 0x80911140, 0x80911030 };
1277 for(i
=udmamode
; i
>=0; i
--) {
1278 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1279 SetPciConfig4(0x44 + (dev
* 8), nat_udmatiming
[i
]);
1280 SetPciConfig4(0x40 + (dev
* 8), nat_piotiming
[i
+8]);
1284 for(i
=wdmamode
; i
>=0; i
--) {
1285 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1286 SetPciConfig4(0x44 + (dev
* 8), nat_dmatiming
[i
]);
1287 SetPciConfig4(0x40 + (dev
* 8), nat_piotiming
[i
+5]);
1291 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
)) {
1292 ChangePciConfig4(0x44 + (dev
* 8), a
| 0x80000000);
1293 SetPciConfig4(0x40 + (dev
* 8), nat_piotiming
[apiomode
]);
1296 /* Use GENERIC PIO */
1298 case ATA_CYPRESS_ID
:
1302 if (wdmamode
>= 2 && apiomode
>= 4) {
1303 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1304 SetPciConfig2(Channel
? 0x4e:0x4c, 0x2020);
1308 /* Use GENERIC PIO */
1310 case ATA_MARVELL_ID
:
1314 for(i
=udmamode
; i
>=0; i
--) {
1315 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1319 for(i
=wdmamode
; i
>=0; i
--) {
1320 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1324 /* try generic DMA, use hpt_timing() */
1325 if (wdmamode
>= 0 && apiomode
>= 4) {
1326 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
)) {
1330 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1333 case ATA_NETCELL_ID
:
1337 if (wdmamode
>= 2 && apiomode
>= 4) {
1338 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1342 /* Use GENERIC PIO */
1344 case ATA_HIGHPOINT_ID
: {
1345 /********************/
1346 /* High Point (HPT) */
1347 /********************/
1348 for(i
=udmamode
; i
>=0; i
--) {
1349 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1350 hpt_timing(deviceExtension
, dev
, (UCHAR
)(ATA_UDMA
+ i
)); // ???
1355 for(i
=wdmamode
; i
>=0; i
--) {
1356 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1357 hpt_timing(deviceExtension
, dev
, (UCHAR
)(ATA_WDMA0
+i
));
1361 /* try generic DMA, use hpt_timing() */
1362 if (wdmamode
>= 0 && apiomode
>= 4) {
1363 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
)) {
1367 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1368 hpt_timing(deviceExtension
, dev
, ATA_PIO0
+ apiomode
);
1371 case ATA_INTEL_ID
: {
1376 BOOLEAN udma_ok
= FALSE
;
1387 UCHAR intel_timings
[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1388 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1389 UCHAR intel_utimings
[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
1391 if(deviceExtension
->DevID
== ATA_I82371FB
) {
1392 if (wdmamode
>= 2 && apiomode
>= 4) {
1395 GetPciConfig4(0x40, word40
);
1396 word40
>>= Channel
* 16;
1398 /* Check for timing config usable for DMA on controller */
1399 if (!((word40
& 0x3300) == 0x2300 &&
1400 ((word40
>> ((!(DeviceNumber
& 1)) ? 0 : 4)) & 1) == 1)) {
1401 udmamode
= wdmamode
= -1;
1405 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1412 if(deviceExtension
->DevID
== ATA_ISCH
) {
1414 GetPciConfig4(0x80 + dev
*4, tim
);
1416 for(i
=udmamode
; i
>=0; i
--) {
1417 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1419 tim
&= ~(0x7 << 16);
1424 apiomode
= ATA_PIO4
;
1429 for(i
=wdmamode
; i
>=0; i
--) {
1430 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1431 tim
&= ~(0x1 << 31);
1437 apiomode
= (i
== 0) ? ATA_PIO0
:
1438 (i
== 1) ? ATA_PIO3
: ATA_PIO4
;
1444 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1448 tim
|= (apiomode
& 0x7);
1449 SetPciConfig4(0x80 + dev
*4, tim
);
1454 GetPciConfig2(0x48, reg48
);
1455 if(!(ChipFlags
& ICH4_FIX
)) {
1456 GetPciConfig2(0x4a, reg4a
);
1458 GetPciConfig2(0x54, reg54
);
1459 // if(udmamode >= 0) {
1460 // enable the write buffer to be used in a split (ping/pong) manner.
1466 // reg40 &= ~0x00ff00ff;
1467 // reg40 |= 0x40774077;
1469 for(i
=udmamode
; i
>=0; i
--) {
1470 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1472 /* Set UDMA reference clock (33 MHz or more). */
1473 SetPciConfig1(0x48, reg48
| (0x0001 << dev
));
1474 if(!(ChipFlags
& ICH4_FIX
)) {
1475 if(deviceExtension
->MaxTransferMode
== ATA_UDMA3
) {
1476 // Special case (undocumented overclock !) for PIIX4e
1477 SetPciConfig2(0x4a, (reg4a
| (0x03 << (dev
<<2)) ) );
1479 SetPciConfig2(0x4a, (reg4a
& ~(0x03 << (dev
<<2))) |
1480 (((USHORT
)(intel_utimings
[i
])) << (dev
<<2) ) );
1483 /* Set UDMA reference clock (66 MHz or more). */
1485 reg54
|= (0x1 << dev
);
1487 reg54
&= ~(0x1 << dev
);
1489 /* Set UDMA reference clock (133 MHz). */
1491 reg54
|= (0x1000 << dev
);
1493 reg54
&= ~(0x1000 << dev
);
1495 SetPciConfig2(0x54, reg54
);
1499 if(ChipFlags
& ICH4_FIX
) {
1507 SetPciConfig1(0x48, reg48
& ~(0x0001 << dev
));
1508 if(!(ChipFlags
& ICH4_FIX
)) {
1509 SetPciConfig2(0x4a, (reg4a
& ~(0x3 << (dev
<< 2))) );
1511 SetPciConfig2(0x54, reg54
& ~(0x1001 << dev
));
1512 for(i
=wdmamode
; i
>=0; i
--) {
1513 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1516 if(ChipFlags
& ICH4_FIX
) {
1525 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1529 GetPciConfig4(0x40, reg40
);
1530 GetPciConfig1(0x44, reg44
);
1532 /* Allow PIO/WDMA timing controls. */
1533 mask40
= 0x000000ff;
1534 /* Set PIO/WDMA timings. */
1535 if(!(DeviceNumber
& 1)) {
1536 mask40
|= 0x00003300;
1537 new40
= ((USHORT
)(intel_timings
[idx
]) << 8);
1540 new44
= ((intel_timings
[idx
] & 0x30) >> 2) |
1541 (intel_timings
[idx
] & 0x03);
1543 new40
|= 0x00004077;
1552 SetPciConfig4(0x40, (reg40
& ~mask40
) | new40
);
1553 SetPciConfig1(0x44, (reg44
& ~mask44
) | new44
);
1557 case ATA_PROMISE_ID
:
1561 if(ChipType
< PRTX
) {
1567 for(i
=udmamode
; i
>=0; i
--) {
1568 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1569 promise_timing(deviceExtension
, dev
, (UCHAR
)(ATA_UDMA
+ i
)); // ???
1574 for(i
=wdmamode
; i
>=0; i
--) {
1575 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1576 promise_timing(deviceExtension
, dev
, (UCHAR
)(ATA_WDMA0
+i
));
1580 /* try generic DMA, use hpt_timing() */
1581 if (wdmamode
>= 0 && apiomode
>= 4) {
1582 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
)) {
1586 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1587 promise_timing(deviceExtension
, dev
, ATA_PIO0
+ apiomode
);
1592 KdPrint2((PRINT_PREFIX
"ATI\n"));
1593 if(ChipType
== SIIMIO
) {
1594 goto l_ATA_SILICON_IMAGE_ID
;
1596 //goto ATA_SERVERWORKS_ID;
1601 case ATA_SERVERWORKS_ID
: {
1605 // static const ULONG udma_modes[] = { 0x70, 0x21, 0x20 };
1606 static const ULONG sw_dma_modes
[] = { 0x70, 0x21, 0x20 };
1607 static const ULONG sw_pio_modes
[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1608 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1612 ULONG offset
= dev
^ 0x01;
1613 ULONG bit_offset
= offset
* 8;
1615 for(i
=udmamode
; i
>=0; i
--) {
1616 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1617 GetPciConfig2(0x56, reg56
);
1618 reg56
&= ~(0xf << (dev
* 4));
1619 reg56
|= ((USHORT
)i
<< (dev
* 4));
1620 SetPciConfig2(0x56, reg56
);
1621 ChangePciConfig1(0x54, a
| (0x01 << dev
));
1623 GetPciConfig4(0x44, reg44
);
1624 reg44
= (reg44
& ~(0xff << bit_offset
)) |
1625 (sw_dma_modes
[2] << bit_offset
);
1626 SetPciConfig4(0x44, reg44
);
1628 GetPciConfig4(0x40, reg40
);
1629 reg40
= (reg40
& ~(0xff << bit_offset
)) |
1630 (sw_pio_modes
[8+i
] << bit_offset
);
1631 SetPciConfig4(0x40, reg40
);
1636 for(i
=wdmamode
; i
>=0; i
--) {
1637 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1639 ChangePciConfig1(0x54, a
& ~(0x01 << dev
));
1641 GetPciConfig4(0x44, reg44
);
1642 reg44
= (reg44
& ~(0xff << bit_offset
)) |
1643 (sw_dma_modes
[wdmamode
] << bit_offset
);
1644 SetPciConfig4(0x44, reg44
);
1646 GetPciConfig4(0x40, reg40
);
1647 reg40
= (reg40
& ~(0xff << bit_offset
)) |
1648 (sw_pio_modes
[5+i
] << bit_offset
);
1649 SetPciConfig4(0x40, reg40
);
1653 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1654 // SetPciConfig4(0x44, sw_pio_modes[apiomode]);
1655 if(VendorID
== ATA_ATI_ID
) {
1656 // special case for ATI
1657 // Seems, that PATA ATI are just re-brended ServerWorks
1660 GetPciConfig2(0x4a, reg4a
);
1661 reg4a
= (reg4a
& ~(0xf << (dev
*4))) |
1662 (apiomode
<< (dev
*4));
1663 SetPciConfig2(0x4a, reg4a
);
1667 GetPciConfig4(0x40, reg40
);
1668 reg40
= (reg40
& ~(0xff << bit_offset
)) |
1669 (sw_pio_modes
[apiomode
] << bit_offset
);
1670 SetPciConfig4(0x40, reg40
);
1673 case ATA_SILICON_IMAGE_ID
: {
1674 l_ATA_SILICON_IMAGE_ID
:
1675 /********************/
1676 /* SiliconImage/CMD */
1677 /********************/
1678 if(ChipType
== SIIMIO
) {
1680 static const UCHAR sil_modes
[7] =
1681 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1682 static const USHORT sil_wdma_modes
[3] =
1683 { 0x2208, 0x10c2, 0x10c1 };
1684 static const USHORT sil_pio_modes
[6] =
1685 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1, 0x10c1 };
1687 UCHAR ureg
= 0xac + ((UCHAR
)DeviceNumber
* 0x02) + ((UCHAR
)Channel
* 0x10);
1689 UCHAR mreg
= Channel
? 0x84 : 0x80;
1690 UCHAR mask
= DeviceNumber
? 0x30 : 0x03;
1693 GetPciConfig1(ureg
, uval
);
1694 GetPciConfig1(mreg
, mode
);
1696 /* enable UDMA mode */
1697 for(i
= udmamode
; i
>=0; i
--) {
1699 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1700 SetPciConfig1(mreg
, mode
| mask
);
1701 SetPciConfig1(ureg
, (uval
& 0x3f) | sil_modes
[i
]);
1705 /* enable WDMA mode */
1706 for(i
= wdmamode
; i
>=0; i
--) {
1708 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1709 SetPciConfig1(mreg
, mode
| (mask
& 0x22));
1710 SetPciConfig2(ureg
- 0x4, sil_wdma_modes
[i
]);
1714 /* restore PIO mode */
1715 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1717 SetPciConfig1(mreg
, mode
| (mask
& 0x11));
1718 SetPciConfig2(ureg
- 0x8, sil_pio_modes
[apiomode
]);
1723 static const UCHAR cmd_modes
[2][6] = {
1724 { 0x31, 0x21, 0x011, 0x25, 0x15, 0x05 },
1725 { 0xc2, 0x82, 0x042, 0x8a, 0x4a, 0x0a } };
1726 static const UCHAR cmd_wdma_modes
[] = { 0x87, 0x32, 0x3f };
1727 static const UCHAR cmd_pio_modes
[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1728 ULONG treg
= 0x54 + ((dev
< 3) ? (dev
<< 1) : 7);
1730 udmamode
= min(udmamode
, 5);
1731 /* enable UDMA mode */
1732 for(i
= udmamode
; i
>=0; i
--) {
1735 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1736 GetPciConfig1(Channel
? 0x7b : 0x73, umode
);
1737 umode
&= ~(!(DeviceNumber
& 1) ? 0x35 : 0xca);
1738 umode
|= ( cmd_modes
[DeviceNumber
& 1][i
]);
1739 SetPciConfig1(Channel
? 0x7b : 0x73, umode
);
1743 /* make sure eventual UDMA mode from the BIOS is disabled */
1744 ChangePciConfig1(Channel
? 0x7b : 0x73, a
& ~(!(DeviceNumber
& 1) ? 0x35 : 0xca));
1746 for(i
= wdmamode
; i
>=0; i
--) {
1748 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1749 SetPciConfig1(treg
, cmd_wdma_modes
[i
]);
1750 ChangePciConfig1(Channel
? 0x7b : 0x73, a
& ~(!(DeviceNumber
& 1) ? 0x35 : 0xca));
1754 /* set PIO mode timings */
1755 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1757 SetPciConfig1(treg
, cmd_pio_modes
[apiomode
]);
1758 ChangePciConfig1(Channel
? 0x7b : 0x73, a
& ~(!(DeviceNumber
& 1) ? 0x35 : 0xca));
1768 PULONG sis_modes
= NULL
;
1769 static const ULONG sis_modes_new133
[] =
1770 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
1771 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
1772 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
1773 static const ULONG sis_modes_old133
[] =
1774 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1775 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
1776 static const ULONG sis_modes_old
[] =
1777 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 0x0301,
1778 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
1779 static const ULONG sis_modes_new100
[] =
1780 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1781 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
1790 sis_modes
= (PULONG
)(&sis_modes_new133
[0]);
1792 GetPciConfig1(0x57, reg57
);
1793 reg
= (reg57
& 0x40 ? 0x70 : 0x40) + (dev
* 4);
1796 sis_modes
= (PULONG
)(&sis_modes_old133
[0]);
1798 reg
= 0x40 + (dev
* 2);
1801 sis_modes
= (PULONG
)(&sis_modes_new100
[0]);
1803 reg
= 0x40 + (dev
* 2);
1808 sis_modes
= (PULONG
)(&sis_modes_old
[0]);
1810 reg
= 0x40 + (dev
* 2);
1815 for(i
=udmamode
; i
>=0; i
--) {
1816 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1818 SetPciConfig4(reg
, sis_modes
[offs
+i
]);
1820 SetPciConfig2(reg
, (USHORT
)sis_modes
[offs
+i
]);
1827 for(i
=wdmamode
; i
>=0; i
--) {
1828 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1830 SetPciConfig4(reg
, sis_modes
[offs
+i
]);
1832 SetPciConfig2(reg
, (USHORT
)sis_modes
[offs
+i
]);
1837 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1839 SetPciConfig4(reg
, sis_modes
[apiomode
]);
1841 SetPciConfig2(reg
, (USHORT
)sis_modes
[apiomode
]);
1846 /* Cenatek Rocket Drive controller */
1847 if (wdmamode
>= 0 &&
1848 (AtapiReadPort1(chan
, IDX_BM_Status
) &
1849 (DeviceNumber
? BM_STATUS_DRIVE_1_DMA
: BM_STATUS_DRIVE_0_DMA
))) {
1850 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ wdmamode
);
1852 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1855 case ATA_ITE_ID
: { /* ITE IDE controller */
1857 if(ChipType
== ITE_33
) {
1858 int a_speed
= 3 << (dev
* 4);
1859 int u_flag
= 1 << dev
;
1863 USHORT drive_enables
;
1866 GetPciConfig1(0x48, reg48
);
1867 GetPciConfig1(0x4a, reg4a
);
1870 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
1871 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
1872 * transfers on some drives, even though both numbers meet the minimum
1873 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
1874 * So the faster times are just commented out here. The good news is
1875 * that the slower cycle time has very little affect on transfer
1879 for(i
=udmamode
; i
>=0; i
--) {
1880 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1881 SetPciConfig1(0x48, reg48
| u_flag
);
1883 SetPciConfig1(0x4a, reg4a
| u_speed
);
1885 goto setup_drive_ite
;
1889 for(i
=wdmamode
; i
>=0; i
--) {
1890 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1891 SetPciConfig1(0x48, reg48
& ~u_flag
);
1892 SetPciConfig1(0x4a, reg4a
& ~a_speed
);
1897 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1898 SetPciConfig1(0x48, reg48
& ~u_flag
);
1899 SetPciConfig1(0x4a, reg4a
& ~a_speed
);
1905 GetPciConfig2(0x40, drive_enables
);
1906 GetPciConfig4(0x44, drive_timing
);
1909 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
1910 * are being left at the default values of 8 PCI clocks (242 nsec
1911 * for a 33 MHz clock). These can be safely shortened at higher
1912 * PIO modes. The DIOR/DIOW pulse width and recovery times only
1913 * apply to PIO modes, not to the DMA modes.
1917 * Enable port 0x44. The IT8172G spec is confused; it calls
1918 * this register the "Slave IDE Timing Register", but in fact,
1919 * it controls timing for both master and slave drives.
1921 drive_enables
|= 0x4000;
1923 drive_enables
&= (0xc000 | (0x06 << (DeviceNumber
*4)));
1925 /* enable prefetch and IORDY sample-point */
1926 drive_enables
|= (0x06 << (DeviceNumber
*4));
1929 SetPciConfig2(0x40, drive_enables
);
1931 if(ChipType
== ITE_133
) {
1932 static const UCHAR udmatiming
[] =
1933 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
1934 static const UCHAR chtiming
[] =
1935 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
1936 ULONG offset
= (Channel
<<2) + DeviceNumber
;
1939 for(i
=udmamode
; i
>=0; i
--) {
1940 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1941 ChangePciConfig1(0x50, a
& ~(1 << (dev
+ 3)) );
1942 SetPciConfig1(0x56 + offset
, udmatiming
[i
]);
1947 for(i
=wdmamode
; i
>=0; i
--) {
1948 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1950 ChangePciConfig1(0x50, a
| (1 << (dev
+ 3)) );
1951 GetPciConfig1(0x54 + offset
, reg54
);
1952 if(reg54
< chtiming
[i
+5]) {
1953 SetPciConfig1(0x54 + offset
, chtiming
[i
+5]);
1958 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1959 ChangePciConfig1(0x50, a
| (1 << (dev
+ 3)) );
1960 GetPciConfig1(0x54 + offset
, reg54
);
1961 if(reg54
< chtiming
[apiomode
]) {
1962 SetPciConfig1(0x54 + offset
, chtiming
[apiomode
]);
1966 if(ChipType
== ITE_133_NEW
) {
1967 //static const USHORT reg54_timings[] = { 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x1001, 0x1001 };
1968 static const UCHAR udmatiming
[] =
1969 { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
1970 static const UCHAR timings
[] =
1971 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1972 0x23, 0x23, 0x23, 0x23, 0x23, 0x02, 0x02 };
1973 BOOLEAN udma_ok
= FALSE
;
1981 USHORT mask40
=0, new40
=0;
1982 UCHAR mask44
=0, new44
=0;
1984 GetPciConfig2(0x40, reg40
);
1985 GetPciConfig1(0x44, reg44
);
1986 GetPciConfig2(0x4a, reg4a
);
1987 GetPciConfig2(0x54, reg54
);
1989 if(!(reg54
& (0x10 << dev
))) {
1991 udmamode
= min(udmamode
, 2);
1994 for(i
=udmamode
; i
>=0; i
--) {
1995 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1996 ChangePciConfig1(0x48, a
| (1 << dev
) );
1997 ChangePciConfig2(0x4a,
1998 (a
& ~(0x3 << (dev
*4))) |
1999 (udmatiming
[i
] << (dev
*4)) );
2002 timing
= timings
[i
+8];
2007 for(i
=wdmamode
; !ok
&& i
>=0; i
--) {
2008 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
2011 timing
= timings
[i
+5];
2017 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
2018 timing
= timings
[apiomode
];
2022 ChangePciConfig1(0x48, a
& ~(1 << dev
) );
2023 ChangePciConfig2(0x4a, a
& ~(0x3 << (dev
<< 2)) );
2025 if (udma_ok
&& udmamode
>= ATA_UDMA2
) {
2026 reg54
|= (0x1 << dev
);
2028 reg54
&= ~(0x1 << dev
);
2030 if (udma_ok
&& udmamode
>= ATA_UDMA5
) {
2031 reg54
|= (0x1000 << dev
);
2033 reg54
&= ~(0x1000 << dev
);
2035 SetPciConfig2(0x54, reg54
);
2040 if(!(DeviceNumber
& 1)) {
2041 reg40
|= (isAtapi
? 0x04 : 0x00);
2043 new40
= timing
<< 8;
2045 reg40
|= (isAtapi
? 0x40 : 0x00);
2047 new44
= ((timing
& 0x30) >> 2) |
2050 SetPciConfig2(0x40, (reg40
& ~mask40
) | new40
);
2051 SetPciConfig1(0x44, (reg44
& ~mask44
) | new44
);
2058 /* HiNT Corp. VXPro II EIDE */
2059 if (wdmamode
>= 0 &&
2060 (AtapiReadPort1(chan
, IDX_BM_Status
) &
2061 (DeviceNumber
? BM_STATUS_DRIVE_1_DMA
: BM_STATUS_DRIVE_0_DMA
))) {
2062 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
);
2064 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
2067 case ATA_JMICRON_ID
: {
2070 GetPciConfig1(0x40, reg40
);
2074 udmamode
= min(udmamode
, 2);
2076 /* Nothing to do to setup mode, the controller snoop SET_FEATURE cmd. */
2079 for(i
=udmamode
; i
>=0; i
--) {
2080 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
2084 for(i
=wdmamode
; i
>=0; i
--) {
2085 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
2089 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
)) {
2098 /* unknown controller chip */
2100 /* better not try generic DMA on ATAPI devices it almost never works */
2102 KdPrint2((PRINT_PREFIX
"ATAPI on unknown controller -> PIO\n"));
2107 /* if controller says its setup for DMA take the easy way out */
2108 /* the downside is we dont know what DMA mode we are in */
2109 if ((udmamode
>= 0 || /*wdmamode > 1*/ wdmamode
>= 0) &&
2110 /*deviceExtension->BaseIoAddressBM[lChannel]*/ (deviceExtension
->BusMaster
==DMA_MODE_BM
) &&
2111 (GetDmaStatus(deviceExtension
, lChannel
) &
2112 (!(DeviceNumber
& 1) ?
2113 BM_STATUS_DRIVE_0_DMA
: BM_STATUS_DRIVE_1_DMA
))) {
2114 // LunExt->TransferMode = ATA_DMA;
2116 KdPrint2((PRINT_PREFIX
"try DMA on unknown controller\n"));
2117 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
)) {
2123 /* well, we have no support for this, but try anyways */
2124 if ((wdmamode
>= 0 && apiomode
>= 4) && deviceExtension
->BaseIoAddressBM
[lChannel
]) {
2125 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
/* + wdmamode*/)) {
2131 KdPrint2((PRINT_PREFIX
"try PIO%d on unknown controller\n", apiomode
));
2132 if(!AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
)) {
2133 KdPrint2((PRINT_PREFIX
"fall to PIO on unknown controller\n"));
2134 LunExt
->TransferMode
= ATA_PIO
;
2137 } // end AtapiDmaInit()
2143 IN PHW_DEVICE_EXTENSION deviceExtension
,
2144 IN ULONG dev
, // physical device number (0-3)
2148 // ASSERT(dev/2 >= deviceExtension->Channel);
2149 // PHW_CHANNEL chan = &(deviceExtension->chan[dev/2-deviceExtension->Channel]);
2150 ULONG reg20
= 0x0000e132;
2151 ULONG reg24
= 0x00017771;
2153 if(mode
== ATA_PIO5
)
2157 case ATA_PIO0
: reg20
= 0x0000e132; break;
2158 case ATA_PIO1
: reg20
= 0x00018121; break;
2159 case ATA_PIO2
: reg20
= 0x00024020; break;
2160 case ATA_PIO3
: reg20
= 0x00032010; break;
2162 case ATA_PIO5
: reg20
= 0x00040010; break;
2163 case ATA_WDMA2
: reg24
= 0x00002020; break;
2164 case ATA_UDMA2
: reg24
= 0x00911030; break;
2166 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),(dev
*8) + 0x20, reg20
);
2167 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),(dev
*8) + 0x24, reg24
);
2173 IN PHW_DEVICE_EXTENSION deviceExtension
,
2174 IN ULONG dev
, // physical device number (0-3)
2178 PVOID HwDeviceExtension
= (PVOID
)deviceExtension
;
2179 ULONG slotNumber
= deviceExtension
->slotNumber
;
2180 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
2182 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
2183 //ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
2187 if(mode
== ATA_PIO5
)
2194 case ATA_PIO0
: timing
= 0x004ff329; break;
2195 case ATA_PIO1
: timing
= 0x004fec25; break;
2196 case ATA_PIO2
: timing
= 0x004fe823; break;
2197 case ATA_PIO3
: timing
= 0x004fe622; break;
2198 case ATA_PIO4
: timing
= 0x004fe421; break;
2199 case ATA_WDMA0
: timing
= 0x004567f3; break;
2200 case ATA_WDMA1
: timing
= 0x004467f3; break;
2201 case ATA_WDMA2
: timing
= 0x004367f3; break;
2202 case ATA_UDMA0
: timing
= 0x004367f3; break;
2203 case ATA_UDMA1
: timing
= 0x004247f3; break;
2204 case ATA_UDMA2
: timing
= 0x004127f3; break;
2211 case ATA_PIO0
: timing
= 0x004fff2f; break;
2212 case ATA_PIO1
: timing
= 0x004ff82a; break;
2213 case ATA_PIO2
: timing
= 0x004ff026; break;
2214 case ATA_PIO3
: timing
= 0x004fec24; break;
2215 case ATA_PIO4
: timing
= 0x004fe822; break;
2216 case ATA_WDMA0
: timing
= 0x004acef6; break;
2217 case ATA_WDMA1
: timing
= 0x0048cef6; break;
2218 case ATA_WDMA2
: timing
= 0x0046cef6; break;
2219 case ATA_UDMA0
: timing
= 0x0046cef6; break;
2220 case ATA_UDMA1
: timing
= 0x00448ef6; break;
2221 case ATA_UDMA2
: timing
= 0x00436ef6; break;
2222 case ATA_UDMA3
: timing
= 0x00424ef6; break;
2223 case ATA_UDMA4
: timing
= 0x004127f3; break;
2224 case ATA_UDMA5
: timing
= 0x004127f3; break;
2230 SetPciConfig4(0x60 + (dev
<<2), timing
);
2231 } // end promise_timing()
2237 IN PHW_DEVICE_EXTENSION deviceExtension
,
2238 IN ULONG dev
, // physical device number (0-3)
2242 PVOID HwDeviceExtension
= (PVOID
)deviceExtension
;
2243 ULONG slotNumber
= deviceExtension
->slotNumber
;
2244 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
2246 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
2247 //ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
2251 if(mode
== ATA_PIO5
)
2257 switch (mode
) { /* HPT374 */
2258 case ATA_PIO0
: timing
= 0x0ac1f48a; break;
2259 case ATA_PIO1
: timing
= 0x0ac1f465; break;
2260 case ATA_PIO2
: timing
= 0x0a81f454; break;
2261 case ATA_PIO3
: timing
= 0x0a81f443; break;
2262 case ATA_PIO4
: timing
= 0x0a81f442; break;
2263 case ATA_WDMA0
: timing
= 0x228082ea; break;
2264 case ATA_WDMA1
: timing
= 0x22808254; break;
2265 case ATA_WDMA2
: timing
= 0x22808242; break;
2266 case ATA_UDMA0
: timing
= 0x121882ea; break;
2267 case ATA_UDMA1
: timing
= 0x12148254; break;
2268 case ATA_UDMA2
: timing
= 0x120c8242; break;
2269 case ATA_UDMA3
: timing
= 0x128c8242; break;
2270 case ATA_UDMA4
: timing
= 0x12ac8242; break;
2271 case ATA_UDMA5
: timing
= 0x12848242; break;
2272 case ATA_UDMA6
: timing
= 0x12808242; break;
2273 default: timing
= 0x0d029d5e;
2279 switch (mode
) { /* HPT372 */
2280 case ATA_PIO0
: timing
= 0x0d029d5e; break;
2281 case ATA_PIO1
: timing
= 0x0d029d26; break;
2282 case ATA_PIO2
: timing
= 0x0c829ca6; break;
2283 case ATA_PIO3
: timing
= 0x0c829c84; break;
2284 case ATA_PIO4
: timing
= 0x0c829c62; break;
2285 case ATA_WDMA0
: timing
= 0x2c82922e; break;
2286 case ATA_WDMA1
: timing
= 0x2c829266; break;
2287 case ATA_WDMA2
: timing
= 0x2c829262; break;
2288 case ATA_UDMA0
: timing
= 0x1c829c62; break;
2289 case ATA_UDMA1
: timing
= 0x1c9a9c62; break;
2290 case ATA_UDMA2
: timing
= 0x1c929c62; break;
2291 case ATA_UDMA3
: timing
= 0x1c8e9c62; break;
2292 case ATA_UDMA4
: timing
= 0x1c8a9c62; break;
2293 case ATA_UDMA5
: timing
= 0x1c8a9c62; break;
2294 case ATA_UDMA6
: timing
= 0x1c869c62; break;
2295 default: timing
= 0x0d029d5e;
2301 switch (mode
) { /* HPT370 */
2302 case ATA_PIO0
: timing
= 0x06914e57; break;
2303 case ATA_PIO1
: timing
= 0x06914e43; break;
2304 case ATA_PIO2
: timing
= 0x06514e33; break;
2305 case ATA_PIO3
: timing
= 0x06514e22; break;
2306 case ATA_PIO4
: timing
= 0x06514e21; break;
2307 case ATA_WDMA0
: timing
= 0x26514e97; break;
2308 case ATA_WDMA1
: timing
= 0x26514e33; break;
2309 case ATA_WDMA2
: timing
= 0x26514e21; break;
2310 case ATA_UDMA0
: timing
= 0x16514e31; break;
2311 case ATA_UDMA1
: timing
= 0x164d4e31; break;
2312 case ATA_UDMA2
: timing
= 0x16494e31; break;
2313 case ATA_UDMA3
: timing
= 0x166d4e31; break;
2314 case ATA_UDMA4
: timing
= 0x16454e31; break;
2315 case ATA_UDMA5
: timing
= 0x16454e31; break;
2316 default: timing
= 0x06514e57;
2322 GetPciConfig1(0x41 + (dev
<< 2), reg41
);
2325 case 0x85: /* 25Mhz */
2327 case ATA_PIO0
: timing
= 0x40d08585; break;
2328 case ATA_PIO1
: timing
= 0x40d08572; break;
2329 case ATA_PIO2
: timing
= 0x40ca8542; break;
2330 case ATA_PIO3
: timing
= 0x40ca8532; break;
2331 case ATA_PIO4
: timing
= 0x40ca8521; break;
2332 case ATA_WDMA2
: timing
= 0x20ca8521; break;
2333 case ATA_UDMA2
: timing
= 0x10cf8521; break;
2334 case ATA_UDMA4
: timing
= 0x10c98521; break;
2335 default: timing
= 0x01208585;
2339 case 0xa7: /* 33MHz */
2341 case ATA_PIO0
: timing
= 0x40d0a7aa; break;
2342 case ATA_PIO1
: timing
= 0x40d0a7a3; break;
2343 case ATA_PIO2
: timing
= 0x40d0a753; break;
2344 case ATA_PIO3
: timing
= 0x40c8a742; break;
2345 case ATA_PIO4
: timing
= 0x40c8a731; break;
2346 case ATA_WDMA0
: timing
= 0x20c8a797; break;
2347 case ATA_WDMA1
: timing
= 0x20c8a732; break;
2348 case ATA_WDMA2
: timing
= 0x20c8a731; break;
2349 case ATA_UDMA0
: timing
= 0x10c8a731; break;
2350 case ATA_UDMA1
: timing
= 0x10cba731; break;
2351 case ATA_UDMA2
: timing
= 0x10caa731; break;
2352 case ATA_UDMA3
: timing
= 0x10cfa731; break;
2353 case ATA_UDMA4
: timing
= 0x10c9a731; break;
2354 default: timing
= 0x0120a7a7;
2357 case 0xd9: /* 40Mhz */
2359 case ATA_PIO0
: timing
= 0x4018d9d9; break;
2360 case ATA_PIO1
: timing
= 0x4010d9c7; break;
2361 case ATA_PIO2
: timing
= 0x4010d997; break;
2362 case ATA_PIO3
: timing
= 0x4010d974; break;
2363 case ATA_PIO4
: timing
= 0x4008d963; break;
2364 case ATA_WDMA2
: timing
= 0x2008d943; break;
2365 case ATA_UDMA2
: timing
= 0x100bd943; break;
2366 case ATA_UDMA4
: timing
= 0x100fd943; break;
2367 default: timing
= 0x0120d9d9;
2373 SetPciConfig4(0x40 + (dev
<<2), timing
);
2374 } // end hpt_timing()
2377 #define FIT(v,min,max) (((v)>(max)?(max):(v))<(min)?(min):(v))
2382 IN PHW_DEVICE_EXTENSION deviceExtension
,
2383 IN ULONG dev
, // physical device number (0-3)
2387 PVOID HwDeviceExtension
= (PVOID
)deviceExtension
;
2388 ULONG slotNumber
= deviceExtension
->slotNumber
;
2389 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
2391 USHORT T
= 1000 / /* PciBusClockMHz()*/ 33;
2402 case ATA_PIO0
: setup
= 70; active
= 165; recover
= 150; cycle
= 600; break;
2403 case ATA_PIO1
: setup
= 50; active
= 125; recover
= 100; cycle
= 383; break;
2404 case ATA_PIO2
: setup
= 30; active
= 100; recover
= 90; cycle
= 240; break;
2405 case ATA_PIO3
: setup
= 30; active
= 80; recover
= 70; cycle
= 180; break;
2406 case ATA_PIO4
: setup
= 25; active
= 70; recover
= 25; cycle
= 120; break;
2407 case ATA_PIO5
: setup
= 20; active
= 50; recover
= 30; cycle
= 100; break;
2410 setup
= (setup
-1)/(T
+1);
2411 active
= (active
-1)/(T
+1);
2412 recover
= (recover
-1)/(T
+1);
2413 cycle
= (cycle
-1)/(T
+1);
2415 if (active
+ recover
< cycle
) {
2416 active
+= (cycle
- (active
+ recover
)) / 2;
2417 recover
= cycle
- active
;
2420 // Newer chips dislike this:
2421 if(/*!(deviceExtension->HwFlags & VIAAST)*/
2422 deviceExtension
->MaxTransferMode
< ATA_UDMA6
) {
2423 /* PIO address setup */
2424 GetPciConfig1(0x4c, t
);
2425 t
= (t
& ~(3 << ((3 - dev
) << 1))) | (FIT(setup
- 1, 0, 3) << ((3 - dev
) << 1));
2426 SetPciConfig1(0x4c, t
);
2429 /* PIO active & recover */
2430 SetPciConfig1(0x4b-dev
, (FIT(active
- 1, 0, 0xf) << 4) | FIT(recover
- 1, 0, 0xf) );
2431 } // end via82c_timing()