reactos/drivers/usb/usbehci/hardware.h

   1 #pragma once
   2
   3 //
   4 // Host Controller Capability Registers
   5 //
   6 #define EHCI_CAPLENGTH                  0x00
   7 #define EHCI_HCIVERSION                 0x02
   8 #define EHCI_HCSPARAMS                  0x04
   9 #define EHCI_HCCPARAMS                  0x08
  10 #define EHCI_HCSP_PORTROUTE             0x0c
  11
  12
  13 //
  14 // Extended Capabilities
  15 //
  16 #define EHCI_ECP_SHIFT                  8
  17 #define EHCI_ECP_MASK                   0xff
  18 #define EHCI_LEGSUP_CAPID_MASK          0xff
  19 #define EHCI_LEGSUP_CAPID               0x01
  20 #define EHCI_LEGSUP_OSOWNED             (1 << 24)
  21 #define EHCI_LEGSUP_BIOSOWNED           (1 << 16)
  22
  23
  24 //
  25 // EHCI Operational Registers
  26 //
  27 #define EHCI_USBCMD                     0x00
  28 #define EHCI_USBSTS                     0x04
  29 #define EHCI_USBINTR                    0x08
  30 #define EHCI_FRINDEX                    0x0C
  31 #define EHCI_CTRLDSSEGMENT              0x10
  32 #define EHCI_PERIODICLISTBASE           0x14
  33 #define EHCI_ASYNCLISTBASE              0x18
  34 #define EHCI_CONFIGFLAG                 0x40
  35 #define EHCI_PORTSC                     0x44
  36
  37 //
  38 // Interrupt Register Flags
  39 //
  40 #define EHCI_USBINTR_INTE               0x01
  41 #define EHCI_USBINTR_ERR                0x02
  42 #define EHCI_USBINTR_PC                 0x04
  43 #define EHCI_USBINTR_FLROVR             0x08
  44 #define EHCI_USBINTR_HSERR              0x10
  45 #define EHCI_USBINTR_ASYNC              0x20
  46 // Bits 6:31 Reserved
  47
  48 //
  49 // Status Register Flags
  50 //
  51 #define EHCI_STS_INT                    0x01
  52 #define EHCI_STS_ERR                    0x02
  53 #define EHCI_STS_PCD                    0x04
  54 #define EHCI_STS_FLR                    0x08
  55 #define EHCI_STS_FATAL                  0x10
  56 #define EHCI_STS_IAA                    0x20
  57 // Bits 11:6 Reserved
  58 #define EHCI_STS_HALT                   0x1000
  59 #define EHCI_STS_RECL                   0x2000
  60 #define EHCI_STS_PSS                    0x4000
  61 #define EHCI_STS_ASS                    0x8000
  62 #define EHCI_ERROR_INT                  (EHCI_STS_FATAL | EHCI_STS_ERR)
  63
  64 //
  65 // Port Register Flags
  66 //
  67 #define EHCI_PRT_CONNECTED              0x01
  68 #define EHCI_PRT_CONNECTSTATUSCHANGE    0x02
  69 #define EHCI_PRT_ENABLED                0x04
  70 #define EHCI_PRT_ENABLEDSTATUSCHANGE    0x08
  71 #define EHCI_PRT_OVERCURRENTACTIVE      0x10
  72 #define EHCI_PRT_OVERCURRENTCHANGE      0x20
  73 #define EHCI_PRT_FORCERESUME            0x40
  74 #define EHCI_PRT_SUSPEND                0x80
  75 #define EHCI_PRT_RESET                  0x100
  76 #define EHCI_PRT_LINESTATUSA            0x400
  77 #define EHCI_PRT_LINESTATUSB            0x800
  78 #define EHCI_PRT_POWER                  0x1000
  79 #define EHCI_PRT_RELEASEOWNERSHIP       0x2000
  80
  81 #define EHCI_PORTSC_DATAMASK    0xffffffd1
  82
  83 #define EHCI_IS_LOW_SPEED(x) (((x) & EHCI_PRT_LINESTATUSA) && !((x) & EHCI_PRT_LINESTATUSB))
  84 //
  85 // Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
  86 //
  87 #define TERMINATE_POINTER       0x01
  88
  89 //
  90 // QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
  91 //
  92
  93 //
  94 // Token Flags
  95 //
  96 #define PID_CODE_OUT_TOKEN      0x00
  97 #define PID_CODE_IN_TOKEN       0x01
  98 #define PID_CODE_SETUP_TOKEN    0x02
  99
 100 #define DO_START_SPLIT          0x00
 101 #define DO_COMPLETE_SPLIT       0x01
 102
 103 #define PING_STATE_DO_OUT       0x00
 104 #define PING_STATE_DO_PING      0x01
 105
 106 typedef struct _PERIODICFRAMELIST
 107 {
 108     PULONG VirtualAddr;
 109     PHYSICAL_ADDRESS PhysicalAddr;
 110     ULONG Size;
 111 } PERIODICFRAMELIST, *PPERIODICFRAMELIST;
 112
 113 //
 114 // QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
 115 //
 116 typedef struct _QETD_TOKEN_BITS
 117 {
 118     ULONG PingState:1;
 119     ULONG SplitTransactionState:1;
 120     ULONG MissedMicroFrame:1;
 121     ULONG TransactionError:1;
 122     ULONG BabbleDetected:1;
 123     ULONG DataBufferError:1;
 124     ULONG Halted:1;
 125     ULONG Active:1;
 126     ULONG PIDCode:2;
 127     ULONG ErrorCounter:2;
 128     ULONG CurrentPage:3;
 129     ULONG InterruptOnComplete:1;
 130     ULONG TotalBytesToTransfer:15;
 131     ULONG DataToggle:1;
 132 } QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
 133
 134 //
 135 // QUEUE ELEMENT TRANSFER DESCRIPTOR
 136 //
 137 typedef struct _QUEUE_TRANSFER_DESCRIPTOR
 138 {
 139     //Hardware
 140     ULONG NextPointer;
 141     ULONG AlternateNextPointer;
 142     union
 143     {
 144         QETD_TOKEN_BITS Bits;
 145         ULONG DWord;
 146     } Token;
 147     ULONG BufferPointer[5];
 148     ULONG ExtendedBufferPointer[5];
 149
 150     //Software
 151     ULONG PhysicalAddr;
 152     LIST_ENTRY DescriptorEntry;
 153     ULONG TotalBytesToTransfer;
 154 } QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
 155
 156 C_ASSERT(FIELD_OFFSET(QUEUE_TRANSFER_DESCRIPTOR, PhysicalAddr) == 0x34);
 157
 158 //
 159 // EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
 160 //
 161 #define QH_ENDPOINT_FULLSPEED       0x00
 162 #define QH_ENDPOINT_LOWSPEED        0x01
 163 #define QH_ENDPOINT_HIGHSPEED       0x02
 164 typedef struct _END_POINT_CHARACTERISTICS
 165 {
 166     ULONG DeviceAddress:7;
 167     ULONG InactiveOnNextTransaction:1;
 168     ULONG EndPointNumber:4;
 169     ULONG EndPointSpeed:2;
 170     ULONG QEDTDataToggleControl:1;
 171     ULONG HeadOfReclamation:1;
 172     ULONG MaximumPacketLength:11;
 173     ULONG ControlEndPointFlag:1;
 174     ULONG NakCountReload:4;
 175 } END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
 176
 177 //
 178 // Capabilities
 179 //
 180 typedef struct _END_POINT_CAPABILITIES
 181 {
 182     ULONG InterruptScheduleMask:8;
 183     ULONG SplitCompletionMask:8;
 184     ULONG HubAddr:7;
 185     ULONG PortNumber:7;
 186     ULONG NumberOfTransactionPerFrame:2;
 187 } END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
 188
 189 //
 190 // QUEUE HEAD Flags and Struct
 191 //
 192 #define QH_TYPE_IDT             0x00
 193 #define QH_TYPE_QH              0x02
 194 #define QH_TYPE_SITD            0x04
 195 #define QH_TYPE_FSTN            0x06
 196
 197 typedef struct _QUEUE_HEAD
 198 {
 199     //Hardware
 200     ULONG HorizontalLinkPointer;
 201     END_POINT_CHARACTERISTICS EndPointCharacteristics;
 202     END_POINT_CAPABILITIES EndPointCapabilities;
 203     // TERMINATE_POINTER not valid for this member
 204     ULONG CurrentLinkPointer;
 205     // TERMINATE_POINTER valid
 206     ULONG NextPointer;
 207     // TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
 208     ULONG AlternateNextPointer;
 209     // Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
 210     union
 211     {
 212         QETD_TOKEN_BITS Bits;
 213         ULONG DWord;
 214     } Token;
 215     ULONG BufferPointer[5];
 216     ULONG ExtendedBufferPointer[5];
 217
 218     //Software
 219     ULONG PhysicalAddr;
 220     LIST_ENTRY LinkedQueueHeads;
 221     LIST_ENTRY TransferDescriptorListHead;
 222     PVOID NextQueueHead;
 223     PVOID Request;
 224 } QUEUE_HEAD, *PQUEUE_HEAD;
 225
 226 C_ASSERT(sizeof(END_POINT_CHARACTERISTICS) == 4);
 227 C_ASSERT(sizeof(END_POINT_CAPABILITIES) == 4);
 228
 229 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, HorizontalLinkPointer) == 0x00);
 230 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, EndPointCharacteristics) == 0x04);
 231 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, EndPointCapabilities) == 0x08);
 232 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, CurrentLinkPointer) == 0xC);
 233 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, NextPointer) == 0x10);
 234 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, AlternateNextPointer) == 0x14);
 235 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, Token) == 0x18);
 236 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, BufferPointer) == 0x1C);
 237 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, PhysicalAddr) == 0x44);
 238
 239
 240 //
 241 // Command register content
 242 //
 243 typedef struct _EHCI_USBCMD_CONTENT
 244 {
 245     ULONG Run : 1;
 246     ULONG HCReset : 1;
 247     ULONG FrameListSize : 2;
 248     ULONG PeriodicEnable : 1;
 249     ULONG AsyncEnable : 1;
 250     ULONG DoorBell : 1;
 251     ULONG LightReset : 1;
 252     ULONG AsyncParkCount : 2;
 253     ULONG Reserved : 1;
 254     ULONG AsyncParkEnable : 1;
 255     ULONG Reserved1 : 4;
 256     ULONG IntThreshold : 8;
 257     ULONG Reserved2 : 8;
 258 } EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
 259
 260 typedef struct _EHCI_HCS_CONTENT
 261 {
 262     ULONG PortCount : 4;
 263     ULONG PortPowerControl: 1;
 264     ULONG Reserved : 2;
 265     ULONG PortRouteRules : 1;
 266     ULONG PortPerCHC : 4;
 267     ULONG CHCCount : 4;
 268     ULONG PortIndicator : 1;
 269     ULONG Reserved2 : 3;
 270     ULONG DbgPortNum : 4;
 271     ULONG Reserved3 : 8;
 272
 273 } EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
 274
 275 typedef struct _EHCI_HCC_CONTENT
 276 {
 277     ULONG CurAddrBits : 1;
 278     ULONG VarFrameList : 1;
 279     ULONG ParkMode : 1;
 280     ULONG Reserved : 1;
 281     ULONG IsoSchedThreshold : 4;
 282     ULONG EECPCapable : 8;
 283     ULONG Reserved2 : 16;
 284
 285 } EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
 286
 287 typedef struct _EHCI_CAPS {
 288     UCHAR Length;
 289     UCHAR Reserved;
 290     USHORT HCIVersion;
 291     union
 292     {
 293         EHCI_HCS_CONTENT HCSParams;
 294         ULONG HCSParamsLong;
 295     };
 296     union
 297     {
 298         EHCI_HCC_CONTENT HCCParams;
 299         ULONG HCCParamsLong;
 300     };
 301     UCHAR PortRoute [15];
 302 } EHCI_CAPS, *PEHCI_CAPS;
 303
 304 typedef struct
 305 {
 306     ULONG PortStatus;
 307     ULONG PortChange;
 308 }EHCI_PORT_STATUS;
 309
 310 #define EHCI_INTERRUPT_ENTRIES_COUNT    (10 + 1)
 311 #define EHCI_VFRAMELIST_ENTRIES_COUNT    128
 312 #define EHCI_FRAMELIST_ENTRIES_COUNT     1024
 313
 314 #define MAX_AVAILABLE_BANDWIDTH 125 // Microseconds
 315
 316 #define EHCI_QH_CAPS_MULT_SHIFT 30                      // Transactions per Micro-Frame
 317 #define EHCI_QH_CAPS_MULT_MASK 0x03
 318 #define EHCI_QH_CAPS_PORT_SHIFT 23                      // Hub Port (Split-Transaction)
 319 #define EHCI_QH_CAPS_PORT_MASK 0x7f
 320 #define EHCI_QH_CAPS_HUB_SHIFT 16                       // Hub Address (Split-Transaction)
 321 #define EHCI_QH_CAPS_HUB_MASK  0x7f
 322 #define EHCI_QH_CAPS_SCM_SHIFT  8                       // Split Completion Mask
 323 #define EHCI_QH_CAPS_SCM_MASK   0xff
 324 #define EHCI_QH_CAPS_ISM_SHIFT  0                       // Interrupt Schedule Mask
 325 #define EHCI_QH_CAPS_ISM_MASK  0xff