reactos/hal/halx86/include/bus.h

   1 #pragma once
   2
   3 #define PCI_ADDRESS_MEMORY_SPACE            0x00000000
   4
   5 //
   6 // Helper Macros
   7 //
   8 #define PASTE2(x,y)                                                     x ## y
   9 #define POINTER_TO_(x)                                                  PASTE2(P,x)
  10 #define READ_FROM(x)                                                    PASTE2(READ_PORT_, x)
  11 #define WRITE_TO(x)                                                     PASTE2(WRITE_PORT_, x)
  12
  13 //
  14 // Declares a PCI Register Read/Write Routine
  15 //
  16 #define TYPE_DEFINE(x, y)                                               \
  17     ULONG                                                               \
  18     NTAPI                                                               \
  19     x(                                                                  \
  20         IN PPCIPBUSDATA BusData,                                        \
  21         IN y PciCfg,                                                    \
  22         IN PUCHAR Buffer,                                               \
  23         IN ULONG Offset                                                 \
  24     )
  25 #define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
  26 #define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
  27
  28 //
  29 // Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
  30 //
  31 #define TYPE1_START(x, y)                                               \
  32     TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS)                                 \
  33 {                                                                       \
  34     ULONG i = Offset % sizeof(ULONG);                                   \
  35     PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG);             \
  36     WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
  37 #define TYPE1_END(y)                                                    \
  38     return sizeof(y); }
  39 #define TYPE2_END       TYPE1_END
  40
  41 //
  42 // PCI Register Read Type 1 Routine
  43 //
  44 #define TYPE1_READ(x, y)                                                \
  45     TYPE1_START(x, y)                                                   \
  46     *((POINTER_TO_(y))Buffer) =                                         \
  47     READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i));     \
  48     TYPE1_END(y)
  49
  50 //
  51 // PCI Register Write Type 1 Routine
  52 //
  53 #define TYPE1_WRITE(x, y)                                               \
  54     TYPE1_START(x, y)                                                   \
  55     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i),       \
  56                 *((POINTER_TO_(y))Buffer));                             \
  57     TYPE1_END(y)
  58
  59 //
  60 // Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
  61 //
  62 #define TYPE2_START(x, y)                                               \
  63     TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS)                             \
  64 {                                                                       \
  65     PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
  66
  67 //
  68 // PCI Register Read Type 2 Routine
  69 //
  70 #define TYPE2_READ(x, y)                                                \
  71     TYPE2_START(x, y)                                                   \
  72     *((POINTER_TO_(y))Buffer) =                                         \
  73         READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT);        \
  74     TYPE2_END(y)
  75
  76 //
  77 // PCI Register Write Type 2 Routine
  78 //
  79 #define TYPE2_WRITE(x, y)                                               \
  80     TYPE2_START(x, y)                                                   \
  81     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT,              \
  82                 *((POINTER_TO_(y))Buffer));                             \
  83     TYPE2_END(y)
  84
  85 typedef NTSTATUS
  86 (NTAPI *PciIrqRange)(
  87     IN PBUS_HANDLER BusHandler,
  88     IN PBUS_HANDLER RootHandler,
  89     IN PCI_SLOT_NUMBER PciSlot,
  90     OUT PSUPPORTED_RANGE *Interrupt
  91 );
  92
  93 typedef struct _PCIPBUSDATA
  94 {
  95     PCIBUSDATA CommonData;
  96     union
  97     {
  98         struct
  99         {
 100             PULONG Address;
 101             ULONG Data;
 102         } Type1;
 103         struct
 104         {
 105             PUCHAR CSE;
 106             PUCHAR Forward;
 107             ULONG Base;
 108         } Type2;
 109     } Config;
 110     ULONG MaxDevice;
 111     PciIrqRange GetIrqRange;
 112     BOOLEAN BridgeConfigRead;
 113     UCHAR ParentBus;
 114     UCHAR Subtractive;
 115     UCHAR reserved[1];
 116     UCHAR SwizzleIn[4];
 117     RTL_BITMAP DeviceConfigured;
 118     ULONG ConfiguredBits[PCI_MAX_DEVICES * PCI_MAX_FUNCTION / 32];
 119 } PCIPBUSDATA, *PPCIPBUSDATA;
 120
 121 typedef ULONG
 122 (NTAPI *FncConfigIO)(
 123     IN PPCIPBUSDATA BusData,
 124     IN PVOID State,
 125     IN PUCHAR Buffer,
 126     IN ULONG Offset
 127 );
 128
 129 typedef VOID
 130 (NTAPI *FncSync)(
 131     IN PBUS_HANDLER BusHandler,
 132     IN PCI_SLOT_NUMBER Slot,
 133     IN PKIRQL Irql,
 134     IN PVOID State
 135 );
 136
 137 typedef VOID
 138 (NTAPI *FncReleaseSync)(
 139     IN PBUS_HANDLER BusHandler,
 140     IN KIRQL Irql
 141 );
 142
 143 typedef struct _PCI_CONFIG_HANDLER
 144 {
 145     FncSync Synchronize;
 146     FncReleaseSync ReleaseSynchronzation;
 147     FncConfigIO ConfigRead[3];
 148     FncConfigIO ConfigWrite[3];
 149 } PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
 150
 151 typedef struct _PCI_REGISTRY_INFO_INTERNAL
 152 {
 153     UCHAR MajorRevision;
 154     UCHAR MinorRevision;
 155     UCHAR NoBuses; // Number Of Buses
 156     UCHAR HardwareMechanism;
 157     ULONG ElementCount;
 158     PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
 159 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
 160
 161 typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
 162 {
 163     union
 164     {
 165         struct
 166         {
 167             ULONG Reserved1:2;
 168             ULONG RegisterNumber:6;
 169             ULONG FunctionNumber:3;
 170             ULONG Reserved2:21;
 171         } bits;
 172         ULONG AsULONG;
 173     } u;
 174 } PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
 175
 176 typedef struct _PCI_TYPE1_CFG_CYCLE_BITS
 177 {
 178     union
 179     {
 180         struct
 181         {
 182             ULONG Reserved1:2;
 183             ULONG RegisterNumber:6;
 184             ULONG FunctionNumber:3;
 185             ULONG DeviceNumber:5;
 186             ULONG BusNumber:8;
 187             ULONG Reserved2:8;
 188         } bits;
 189         ULONG AsULONG;
 190     } u;
 191 } PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
 192
 193 typedef struct _ARRAY
 194 {
 195     ULONG ArraySize;
 196     PVOID Element[ANYSIZE_ARRAY];
 197 } ARRAY, *PARRAY;
 198
 199 typedef struct _HAL_BUS_HANDLER
 200 {
 201     LIST_ENTRY AllHandlers;
 202     ULONG ReferenceCount;
 203     BUS_HANDLER Handler;
 204 } HAL_BUS_HANDLER, *PHAL_BUS_HANDLER;
 205
 206 /* FUNCTIONS *****************************************************************/
 207
 208 /* SHARED (Fake PCI-BUS HANDLER) */
 209
 210 VOID
 211 NTAPI
 212 HalpPCISynchronizeType1(
 213     IN PBUS_HANDLER BusHandler,
 214     IN PCI_SLOT_NUMBER Slot,
 215     IN PKIRQL Irql,
 216     IN PPCI_TYPE1_CFG_BITS PciCfg
 217 );
 218
 219 VOID
 220 NTAPI
 221 HalpPCIReleaseSynchronzationType1(
 222     IN PBUS_HANDLER BusHandler,
 223     IN KIRQL Irql
 224 );
 225
 226 VOID
 227 NTAPI
 228 HalpPCISynchronizeType2(
 229     IN PBUS_HANDLER BusHandler,
 230     IN PCI_SLOT_NUMBER Slot,
 231     IN PKIRQL Irql,
 232     IN PPCI_TYPE2_ADDRESS_BITS PciCfg
 233 );
 234
 235 VOID
 236 NTAPI
 237 HalpPCIReleaseSynchronizationType2(
 238     IN PBUS_HANDLER BusHandler,
 239     IN KIRQL Irql
 240 );
 241
 242 TYPE1_DEFINE(HalpPCIReadUcharType1);
 243 TYPE1_DEFINE(HalpPCIReadUshortType1);
 244 TYPE1_DEFINE(HalpPCIReadUlongType1);
 245 TYPE2_DEFINE(HalpPCIReadUcharType2);
 246 TYPE2_DEFINE(HalpPCIReadUshortType2);
 247 TYPE2_DEFINE(HalpPCIReadUlongType2);
 248 TYPE1_DEFINE(HalpPCIWriteUcharType1);
 249 TYPE1_DEFINE(HalpPCIWriteUshortType1);
 250 TYPE1_DEFINE(HalpPCIWriteUlongType1);
 251 TYPE2_DEFINE(HalpPCIWriteUcharType2);
 252 TYPE2_DEFINE(HalpPCIWriteUshortType2);
 253 TYPE2_DEFINE(HalpPCIWriteUlongType2);
 254
 255 BOOLEAN
 256 NTAPI
 257 HalpValidPCISlot(
 258     IN PBUS_HANDLER BusHandler,
 259     IN PCI_SLOT_NUMBER Slot
 260 );
 261
 262 VOID
 263 NTAPI
 264 HalpReadPCIConfig(
 265     IN PBUS_HANDLER BusHandler,
 266     IN PCI_SLOT_NUMBER Slot,
 267     IN PVOID Buffer,
 268     IN ULONG Offset,
 269     IN ULONG Length
 270 );
 271
 272 VOID
 273 NTAPI
 274 HalpWritePCIConfig(
 275     IN PBUS_HANDLER BusHandler,
 276     IN PCI_SLOT_NUMBER Slot,
 277     IN PVOID Buffer,
 278     IN ULONG Offset,
 279     IN ULONG Length
 280 );
 281
 282 ULONG
 283 NTAPI
 284 HalpGetPCIData(
 285     IN PBUS_HANDLER BusHandler,
 286     IN PBUS_HANDLER RootBusHandler,
 287     IN PCI_SLOT_NUMBER SlotNumber,
 288     IN PVOID Buffer,
 289     IN ULONG Offset,
 290     IN ULONG Length
 291 );
 292
 293 ULONG
 294 NTAPI
 295 HalpSetPCIData(
 296     IN PBUS_HANDLER BusHandler,
 297     IN PBUS_HANDLER RootBusHandler,
 298     IN PCI_SLOT_NUMBER SlotNumber,
 299     IN PVOID Buffer,
 300     IN ULONG Offset,
 301     IN ULONG Length
 302 );
 303
 304 NTSTATUS
 305 NTAPI
 306 HalpAssignPCISlotResources(
 307     IN PBUS_HANDLER BusHandler,
 308     IN PBUS_HANDLER RootHandler,
 309     IN PUNICODE_STRING RegistryPath,
 310     IN PUNICODE_STRING DriverClassName OPTIONAL,
 311     IN PDRIVER_OBJECT DriverObject,
 312     IN PDEVICE_OBJECT DeviceObject OPTIONAL,
 313     IN ULONG Slot,
 314     IN OUT PCM_RESOURCE_LIST *pAllocatedResources
 315 );
 316
 317 /* NON-LEGACY */
 318
 319 ULONG
 320 NTAPI
 321 HalpGetSystemInterruptVector_Acpi(
 322     ULONG BusNumber,
 323     ULONG BusInterruptLevel,
 324     ULONG BusInterruptVector,
 325     PKIRQL Irql,
 326     PKAFFINITY Affinity
 327 );
 328
 329 ULONG
 330 NTAPI
 331 HalpGetCmosData(
 332     IN ULONG BusNumber,
 333     IN ULONG SlotNumber,
 334     IN PVOID Buffer,
 335     IN ULONG Length
 336 );
 337
 338 ULONG
 339 NTAPI
 340 HalpSetCmosData(
 341     IN ULONG BusNumber,
 342     IN ULONG SlotNumber,
 343     IN PVOID Buffer,
 344     IN ULONG Length
 345 );
 346
 347 VOID
 348 NTAPI
 349 HalpInitializePciBus(
 350     VOID
 351 );
 352
 353 VOID
 354 NTAPI
 355 HalpInitializePciStubs(
 356     VOID
 357 );
 358
 359 BOOLEAN
 360 NTAPI
 361 HalpTranslateBusAddress(
 362     IN INTERFACE_TYPE InterfaceType,
 363     IN ULONG BusNumber,
 364     IN PHYSICAL_ADDRESS BusAddress,
 365     IN OUT PULONG AddressSpace,
 366     OUT PPHYSICAL_ADDRESS TranslatedAddress
 367 );
 368
 369 NTSTATUS
 370 NTAPI
 371 HalpAssignSlotResources(
 372     IN PUNICODE_STRING RegistryPath,
 373     IN PUNICODE_STRING DriverClassName,
 374     IN PDRIVER_OBJECT DriverObject,
 375     IN PDEVICE_OBJECT DeviceObject,
 376     IN INTERFACE_TYPE BusType,
 377     IN ULONG BusNumber,
 378     IN ULONG SlotNumber,
 379     IN OUT PCM_RESOURCE_LIST *AllocatedResources
 380 );
 381
 382 BOOLEAN
 383 NTAPI
 384 HalpFindBusAddressTranslation(
 385     IN PHYSICAL_ADDRESS BusAddress,
 386     IN OUT PULONG AddressSpace,
 387     OUT PPHYSICAL_ADDRESS TranslatedAddress,
 388     IN OUT PULONG_PTR Context,
 389     IN BOOLEAN NextBus
 390 );
 391
 392 VOID
 393 NTAPI
 394 HalpRegisterPciDebuggingDeviceInfo(
 395     VOID
 396 );
 397
 398 /* LEGACY */
 399
 400 VOID
 401 NTAPI
 402 HalpInitBusHandler(
 403     VOID
 404 );
 405
 406 ULONG
 407 NTAPI
 408 HalpNoBusData(
 409     IN PBUS_HANDLER BusHandler,
 410     IN PBUS_HANDLER RootHandler,
 411     IN ULONG SlotNumber,
 412     IN PVOID Buffer,
 413     IN ULONG Offset,
 414     IN ULONG Length
 415 );
 416
 417 ULONG
 418 NTAPI
 419 HalpcGetCmosData(
 420     IN PBUS_HANDLER BusHandler,
 421     IN PBUS_HANDLER RootHandler,
 422     IN ULONG SlotNumber,
 423     IN PVOID Buffer,
 424     IN ULONG Offset,
 425     IN ULONG Length
 426 );
 427
 428 ULONG
 429 NTAPI
 430 HalpcSetCmosData(
 431     IN PBUS_HANDLER BusHandler,
 432     IN PBUS_HANDLER RootHandler,
 433     IN ULONG SlotNumber,
 434     IN PVOID Buffer,
 435     IN ULONG Offset,
 436     IN ULONG Length
 437 );
 438
 439 BOOLEAN
 440 NTAPI
 441 HalpTranslateSystemBusAddress(
 442     IN PBUS_HANDLER BusHandler,
 443     IN PBUS_HANDLER RootHandler,
 444     IN PHYSICAL_ADDRESS BusAddress,
 445     IN OUT PULONG AddressSpace,
 446     OUT PPHYSICAL_ADDRESS TranslatedAddress
 447 );
 448
 449 BOOLEAN
 450 NTAPI
 451 HalpTranslateIsaBusAddress(
 452     IN PBUS_HANDLER BusHandler,
 453     IN PBUS_HANDLER RootHandler,
 454     IN PHYSICAL_ADDRESS BusAddress,
 455     IN OUT PULONG AddressSpace,
 456     OUT PPHYSICAL_ADDRESS TranslatedAddress
 457 );
 458
 459 ULONG
 460 NTAPI
 461 HalpGetSystemInterruptVector(
 462     IN PBUS_HANDLER BusHandler,
 463     IN PBUS_HANDLER RootHandler,
 464     IN ULONG BusInterruptLevel,
 465     IN ULONG BusInterruptVector,
 466     OUT PKIRQL Irql,
 467     OUT PKAFFINITY Affinity
 468 );
 469
 470 extern ULONG HalpBusType;
 471 extern BOOLEAN HalpPCIConfigInitialized;
 472 extern BUS_HANDLER HalpFakePciBusHandler;
 473 extern ULONG HalpMinPciBus, HalpMaxPciBus;
 474
 475 /* EOF */