reactos/hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #ifndef __INTERNAL_HAL_HAL_H
   6 #define __INTERNAL_HAL_HAL_H
   7
   8 #define HAL_APC_REQUEST         0
   9 #define HAL_DPC_REQUEST         1
  10
  11 /* CMOS Registers and Ports */
  12 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  13 #define CMOS_DATA_PORT          (PUCHAR)0x71
  14 #define RTC_REGISTER_A          0x0A
  15 #define RTC_REGISTER_B          0x0B
  16 #define RTC_REG_A_UIP           0x80
  17 #define RTC_REGISTER_CENTURY    0x32
  18
  19 /* Usage flags */
  20 #define IDT_REGISTERED          0x01
  21 #define IDT_LATCHED             0x02
  22 #define IDT_INTERNAL            0x11
  23 #define IDT_DEVICE              0x21
  24
  25 /* Conversion functions */
  26 #define BCD_INT(bcd)            \
  27     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  28 #define INT_BCD(int)            \
  29     (UCHAR)(((int / 10) << 4) + (int % 10))
  30
  31 //
  32 // Commonly stated as being 1.19318MHz
  33 //
  34 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
  35 // P. 471
  36 //
  37 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
  38 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
  39 //
  40 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
  41 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
  42 // infinite series) and divides it by three, one obtains 1.19318167.
  43 //
  44 // It may be that the original NT HAL source code introduced a typo and turned
  45 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
  46 // number is quite long.
  47 //
  48 #define PIT_FREQUENCY 1193182
  49
  50 //
  51 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
  52 //
  53 #define TIMER_CHANNEL0_DATA_PORT 0x40
  54 #define TIMER_CHANNEL1_DATA_PORT 0x41
  55 #define TIMER_CHANNEL2_DATA_PORT 0x42
  56 #define TIMER_CONTROL_PORT       0x43
  57
  58 //
  59 // Mode 0 - Interrupt On Terminal Count
  60 // Mode 1 - Hardware Re-triggerable One-Shot
  61 // Mode 2 - Rate Generator
  62 // Mode 3 - Square Wave Generator
  63 // Mode 4 - Software Triggered Strobe
  64 // Mode 5 - Hardware Triggered Strobe
  65 //
  66 typedef enum _TIMER_OPERATING_MODES
  67 {
  68     PitOperatingMode0,
  69     PitOperatingMode1,
  70     PitOperatingMode2,
  71     PitOperatingMode3,
  72     PitOperatingMode4,
  73     PitOperatingMode5,
  74     PitOperatingMode2Reserved,
  75     PitOperatingMode5Reserved
  76 } TIMER_OPERATING_MODES;
  77
  78 typedef enum _TIMER_ACCESS_MODES
  79 {
  80     PitAccessModeCounterLatch,
  81     PitAccessModeLow,
  82     PitAccessModeHigh,
  83     PitAccessModeLowHigh
  84 } TIMER_ACCESS_MODES;
  85
  86 typedef enum _TIMER_CHANNELS
  87 {
  88     PitChannel0,
  89     PitChannel1,
  90     PitChannel2,
  91     PitReadBack
  92 } TIMER_CHANNELS;
  93
  94 typedef union _TIMER_CONTROL_PORT_REGISTER
  95 {
  96     struct
  97     {
  98         UCHAR BcdMode:1;
  99         TIMER_OPERATING_MODES OperatingMode:3;
 100         TIMER_ACCESS_MODES AccessMode:2;
 101         TIMER_CHANNELS Channel:2;
 102     };
 103     UCHAR Bits;
 104 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 105
 106 //
 107 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 108 // P. 400
 109 //
 110 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 111 //
 112 #define SYSTEM_CONTROL_PORT_A   0x92
 113 #define SYSTEM_CONTROL_PORT_B   0x61
 114 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 115 {
 116     struct
 117     {
 118         UCHAR Timer2GateToSpeaker:1;
 119         UCHAR SpeakerDataEnable:1;
 120         UCHAR ParityCheckEnable:1;
 121         UCHAR ChannelCheckEnable:1;
 122         UCHAR RefreshRequest:1;
 123         UCHAR Timer2Output:1;
 124         UCHAR ChannelCheck:1;
 125         UCHAR ParityCheck:1;
 126     };
 127     UCHAR Bits;
 128 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 129
 130 //
 131 // Mm PTE/PDE to Hal PTE/PDE
 132 //
 133 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 134 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 135
 136 typedef struct _IDTUsageFlags
 137 {
 138     UCHAR Flags;
 139 } IDTUsageFlags;
 140
 141 typedef struct
 142 {
 143     KIRQL Irql;
 144     UCHAR BusReleativeVector;
 145 } IDTUsage;
 146
 147 typedef struct _HalAddressUsage
 148 {
 149     struct _HalAddressUsage *Next;
 150     CM_RESOURCE_TYPE Type;
 151     UCHAR Flags;
 152     struct
 153     {
 154         ULONG Start;
 155         ULONG Length;
 156     } Element[];
 157 } ADDRESS_USAGE, *PADDRESS_USAGE;
 158
 159 /* adapter.c */
 160 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 161
 162 /* sysinfo.c */
 163 VOID
 164 NTAPI
 165 HalpRegisterVector(IN UCHAR Flags,
 166                    IN ULONG BusVector,
 167                    IN ULONG SystemVector,
 168                    IN KIRQL Irql);
 169
 170 VOID
 171 NTAPI
 172 HalpEnableInterruptHandler(IN UCHAR Flags,
 173                            IN ULONG BusVector,
 174                            IN ULONG SystemVector,
 175                            IN KIRQL Irql,
 176                            IN PVOID Handler,
 177                            IN KINTERRUPT_MODE Mode);
 178
 179 /* irql.c */
 180 VOID NTAPI HalpInitPICs(VOID);
 181
 182 /* udelay.c */
 183 VOID NTAPI HalpInitializeClock(VOID);
 184
 185 VOID
 186 NTAPI
 187 HalpCalibrateStallExecution(VOID);
 188
 189 /* pci.c */
 190 VOID HalpInitPciBus (VOID);
 191
 192 /* dma.c */
 193 VOID HalpInitDma (VOID);
 194
 195 /* Non-generic initialization */
 196 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 197 VOID HalpInitPhase1(VOID);
 198 VOID NTAPI HalpClockInterrupt(VOID);
 199 VOID NTAPI HalpProfileInterrupt(VOID);
 200
 201 VOID
 202 NTAPI
 203 HalpFlushTLB(VOID);
 204
 205 //
 206 // KD Support
 207 //
 208 VOID
 209 NTAPI
 210 HalpCheckPowerButton(
 211     VOID
 212 );
 213
 214 VOID
 215 NTAPI
 216 HalpRegisterKdSupportFunctions(
 217     VOID
 218 );
 219
 220 NTSTATUS
 221 NTAPI
 222 HalpSetupPciDeviceForDebugging(
 223     IN PVOID LoaderBlock,
 224     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 225 );
 226
 227 NTSTATUS
 228 NTAPI
 229 HalpReleasePciDeviceForDebugging(
 230     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 231 );
 232
 233 //
 234 // Memory routines
 235 //
 236 PVOID
 237 NTAPI
 238 HalpMapPhysicalMemory64(
 239     IN PHYSICAL_ADDRESS PhysicalAddress,
 240     IN ULONG NumberPage
 241 );
 242
 243 VOID
 244 NTAPI
 245 HalpUnmapVirtualAddress(
 246     IN PVOID VirtualAddress,
 247     IN ULONG NumberPages
 248 );
 249
 250 /* sysinfo.c */
 251 NTSTATUS
 252 NTAPI
 253 HaliQuerySystemInformation(
 254     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 255     IN ULONG BufferSize,
 256     IN OUT PVOID Buffer,
 257     OUT PULONG ReturnedLength
 258 );
 259
 260 NTSTATUS
 261 NTAPI
 262 HaliSetSystemInformation(
 263     IN HAL_SET_INFORMATION_CLASS InformationClass,
 264     IN ULONG BufferSize,
 265     IN OUT PVOID Buffer
 266 );
 267
 268 //
 269 // BIOS Routines
 270 //
 271 BOOLEAN
 272 NTAPI
 273 HalpBiosDisplayReset(
 274     VOID
 275 );
 276
 277 VOID
 278 NTAPI
 279 HalpBiosCall(
 280     VOID
 281 );
 282
 283 VOID
 284 NTAPI
 285 HalpTrap0D(
 286     VOID
 287 );
 288
 289 VOID
 290 NTAPI
 291 HalpTrap06(
 292     VOID
 293 );
 294
 295 //
 296 // Processor Halt Routine
 297 //
 298 VOID
 299 NTAPI
 300 HaliHaltSystem(
 301     VOID
 302 );
 303
 304 //
 305 // CMOS initialization
 306 //
 307 VOID
 308 NTAPI
 309 HalpInitializeCmos(
 310     VOID
 311 );
 312
 313 //
 314 // Spinlock for protecting CMOS access
 315 //
 316 VOID
 317 NTAPI
 318 HalpAcquireSystemHardwareSpinLock(
 319     VOID
 320 );
 321
 322 VOID
 323 NTAPI
 324 HalpReleaseCmosSpinLock(
 325     VOID
 326 );
 327
 328 #ifdef _M_AMD64
 329 #define KfLowerIrql KeLowerIrql
 330 #ifndef CONFIG_SMP
 331 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 332 #define KiAcquireSpinLock(SpinLock)
 333 #define KiReleaseSpinLock(SpinLock)
 334 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 335 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 336 #endif // !CONFIG_SMP
 337 #endif // _M_AMD64
 338
 339 extern BOOLEAN HalpNMIInProgress;
 340
 341 extern PVOID HalpRealModeStart;
 342 extern PVOID HalpRealModeEnd;
 343
 344 extern ADDRESS_USAGE HalpDefaultIoSpace;
 345
 346 extern KSPIN_LOCK HalpSystemHardwareLock;
 347
 348 extern PADDRESS_USAGE HalpAddressUsageList;
 349
 350 #endif /* __INTERNAL_HAL_HAL_H */