reactos/include/ntos/haltypes.h

   1 /* $Id: haltypes.h,v 1.5 2003/12/30 18:34:58 fireball Exp $
   2  *
   3  * COPYRIGHT:                See COPYING in the top level directory
   4  * PROJECT:                  ReactOS kernel
   5  * FILE:                     include/ddk/haltypes.h
   6  * PURPOSE:                  HAL provided defintions for device drivers
   7  * PROGRAMMER:               David Welch (welch@mcmail.com)
   8  * REVISION HISTORY:
   9  *              23/06/98:   Taken from linux system.h
  10  */
  11
  12
  13 #ifndef __INCLUDE_NTOS_HALTYPES_H
  14 #define __INCLUDE_NTOS_HALTYPES_H
  15
  16 #ifdef __GNUC__
  17 #define STDCALL_FUNC  STDCALL
  18 #define FASTCALL_FUNC FASTCALL
  19 #else
  20 #define STDCALL_FUNC(a)  (__stdcall a )
  21 #define FASTCALL_FUNC(a) (__fastcall a )
  22 #endif /*__GNUC__*/
  23
  24 #include "types.h"
  25
  26
  27 /* HalReturnToFirmware */
  28 #define FIRMWARE_HALT   1
  29 #define FIRMWARE_REBOOT 3
  30
  31 #ifndef __USE_W32API
  32
  33 enum
  34 {
  35    DEVICE_DESCRIPTION_VERSION,
  36    DEVICE_DESCRIPTION_VERSION1,
  37 };
  38
  39 /*
  40  * DMA speed specifiers
  41  */
  42 typedef enum _DMA_SPEED
  43 {
  44   Compatible,
  45   TypeA,
  46   TypeB,
  47   TypeC,
  48   TypeF,
  49   MaximumDmaSpeed
  50 } DMA_SPEED, *PDMA_SPEED;
  51
  52 /*
  53  * DMA width specifiers
  54  */
  55 typedef enum _DMA_WIDTH
  56 {
  57   Width8Bits,
  58   Width16Bits,
  59   Width32Bits,
  60   MaximumDmaWidth
  61 } DMA_WIDTH, *PDMA_WIDTH;
  62
  63 /*
  64  * PURPOSE: Types for HalGetBusData
  65  */
  66 typedef enum _BUS_DATA_TYPE
  67 {
  68    ConfigurationSpaceUndefined = -1,
  69    Cmos,
  70    EisaConfiguration,
  71    Pos,
  72    CbusConfiguration,
  73    PCIConfiguration,
  74    VMEConfiguration,
  75    NuBusConfiguration,
  76    PCMCIAConfiguration,
  77    MPIConfiguration,
  78    MPSAConfiguration,
  79    PNPISAConfiguration,
  80    MaximumBusDataType,
  81 } BUS_DATA_TYPE, *PBUS_DATA_TYPE;
  82
  83 typedef struct _DEVICE_DESCRIPTION
  84 {
  85   ULONG Version;
  86   BOOLEAN Master;
  87   BOOLEAN ScatterGather;
  88   BOOLEAN DemandMode;
  89   BOOLEAN AutoInitialize;
  90   BOOLEAN Dma32BitAddresses;
  91   BOOLEAN IgnoreCount;
  92   BOOLEAN Reserved1;        /* Must be false */
  93   BOOLEAN Dma64BitAddresses;
  94   ULONG BusNumber;
  95   ULONG DmaChannel;
  96   INTERFACE_TYPE InterfaceType;
  97   DMA_WIDTH DmaWidth;
  98   DMA_SPEED DmaSpeed;
  99   ULONG MaximumLength;
 100   ULONG DmaPort;
 101 } DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
 102
 103
 104 /* PCI bus definitions */
 105
 106 #define PCI_TYPE0_ADDRESSES     6
 107 #define PCI_TYPE1_ADDRESSES     2
 108 #define PCI_TYPE2_ADDRESSES     5
 109
 110 typedef struct _PCI_COMMON_CONFIG
 111 {
 112   USHORT VendorID;              /* read-only */
 113   USHORT DeviceID;              /* read-only */
 114   USHORT Command;
 115   USHORT Status;
 116   UCHAR  RevisionID;            /* read-only */
 117   UCHAR  ProgIf;                /* read-only */
 118   UCHAR  SubClass;              /* read-only */
 119   UCHAR  BaseClass;             /* read-only */
 120   UCHAR  CacheLineSize;         /* read-only */
 121   UCHAR  LatencyTimer;          /* read-only */
 122   UCHAR  HeaderType;            /* read-only */
 123   UCHAR  BIST;
 124   union
 125     {
 126       struct _PCI_HEADER_TYPE_0
 127         {
 128           ULONG  BaseAddresses[PCI_TYPE0_ADDRESSES];
 129           ULONG  CIS;
 130           USHORT SubVendorID;
 131           USHORT SubSystemID;
 132           ULONG  ROMBaseAddress;
 133           ULONG  Reserved2[2];
 134
 135           UCHAR  InterruptLine;
 136           UCHAR  InterruptPin;          /* read-only */
 137           UCHAR  MinimumGrant;          /* read-only */
 138           UCHAR  MaximumLatency;        /* read-only */
 139         } type0;
 140
 141       /* PCI to PCI Bridge */
 142       struct _PCI_HEADER_TYPE_1
 143         {
 144           ULONG  BaseAddresses[PCI_TYPE1_ADDRESSES];
 145           UCHAR  PrimaryBus;
 146           UCHAR  SecondaryBus;
 147           UCHAR  SubordinateBus;
 148           UCHAR  SecondaryLatency;
 149           UCHAR  IOBase;
 150           UCHAR  IOLimit;
 151           USHORT SecondaryStatus;
 152           USHORT MemoryBase;
 153           USHORT MemoryLimit;
 154           USHORT PrefetchBase;
 155           USHORT PrefetchLimit;
 156           ULONG  PrefetchBaseUpper32;
 157           ULONG  PrefetchLimitUpper32;
 158           USHORT IOBaseUpper16;
 159           USHORT IOLimitUpper16;
 160           UCHAR  CapabilitiesPtr;
 161           UCHAR  Reserved1[3];
 162           ULONG  ROMBaseAddress;
 163           UCHAR  InterruptLine;
 164           UCHAR  InterruptPin;
 165           USHORT BridgeControl;
 166         } type1;
 167
 168       /* PCI to CARDBUS Bridge */
 169       struct _PCI_HEADER_TYPE_2
 170         {
 171           ULONG  SocketRegistersBaseAddress;
 172           UCHAR  CapabilitiesPtr;
 173           UCHAR  Reserved;
 174           USHORT SecondaryStatus;
 175           UCHAR  PrimaryBus;
 176           UCHAR  SecondaryBus;
 177           UCHAR  SubordinateBus;
 178           UCHAR  SecondaryLatency;
 179           struct
 180             {
 181               ULONG Base;
 182               ULONG Limit;
 183             } Range[PCI_TYPE2_ADDRESSES-1];
 184           UCHAR  InterruptLine;
 185           UCHAR  InterruptPin;
 186           USHORT BridgeControl;
 187         } type2;
 188     } u;
 189   UCHAR DeviceSpecific[192];
 190 } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
 191
 192 #define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
 193
 194 #define PCI_MAX_DEVICES                     32
 195 #define PCI_MAX_FUNCTION                    8
 196
 197 #define PCI_INVALID_VENDORID                0xFFFF
 198
 199 /* Bit encodings for PCI_COMMON_CONFIG.HeaderType */
 200
 201 #define PCI_MULTIFUNCTION                   0x80
 202 #define PCI_DEVICE_TYPE                     0x00
 203 #define PCI_BRIDGE_TYPE                     0x01
 204
 205
 206 /* Bit encodings for PCI_COMMON_CONFIG.Command */
 207
 208 #define PCI_ENABLE_IO_SPACE                 0x0001
 209 #define PCI_ENABLE_MEMORY_SPACE             0x0002
 210 #define PCI_ENABLE_BUS_MASTER               0x0004
 211 #define PCI_ENABLE_SPECIAL_CYCLES           0x0008
 212 #define PCI_ENABLE_WRITE_AND_INVALIDATE     0x0010
 213 #define PCI_ENABLE_VGA_COMPATIBLE_PALETTE   0x0020
 214 #define PCI_ENABLE_PARITY                   0x0040
 215 #define PCI_ENABLE_WAIT_CYCLE               0x0080
 216 #define PCI_ENABLE_SERR                     0x0100
 217 #define PCI_ENABLE_FAST_BACK_TO_BACK        0x0200
 218
 219
 220 /* Bit encodings for PCI_COMMON_CONFIG.Status */
 221
 222 #define PCI_STATUS_FAST_BACK_TO_BACK        0x0080
 223 #define PCI_STATUS_DATA_PARITY_DETECTED     0x0100
 224 #define PCI_STATUS_DEVSEL                   0x0600  /* 2 bits wide */
 225 #define PCI_STATUS_SIGNALED_TARGET_ABORT    0x0800
 226 #define PCI_STATUS_RECEIVED_TARGET_ABORT    0x1000
 227 #define PCI_STATUS_RECEIVED_MASTER_ABORT    0x2000
 228 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR    0x4000
 229 #define PCI_STATUS_DETECTED_PARITY_ERROR    0x8000
 230
 231
 232 /* PCI device classes */
 233
 234 #define PCI_CLASS_PRE_20                    0x00
 235 #define PCI_CLASS_MASS_STORAGE_CTLR         0x01
 236 #define PCI_CLASS_NETWORK_CTLR              0x02
 237 #define PCI_CLASS_DISPLAY_CTLR              0x03
 238 #define PCI_CLASS_MULTIMEDIA_DEV            0x04
 239 #define PCI_CLASS_MEMORY_CTLR               0x05
 240 #define PCI_CLASS_BRIDGE_DEV                0x06
 241 #define PCI_CLASS_SIMPLE_COMMS_CTLR         0x07
 242 #define PCI_CLASS_BASE_SYSTEM_DEV           0x08
 243 #define PCI_CLASS_INPUT_DEV                 0x09
 244 #define PCI_CLASS_DOCKING_STATION           0x0a
 245 #define PCI_CLASS_PROCESSOR                 0x0b
 246 #define PCI_CLASS_SERIAL_BUS_CTLR           0x0c
 247
 248
 249 /* PCI device subclasses for class 1 (mass storage controllers)*/
 250
 251 #define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR      0x00
 252 #define PCI_SUBCLASS_MSC_IDE_CTLR           0x01
 253 #define PCI_SUBCLASS_MSC_FLOPPY_CTLR        0x02
 254 #define PCI_SUBCLASS_MSC_IPI_CTLR           0x03
 255 #define PCI_SUBCLASS_MSC_RAID_CTLR          0x04
 256 #define PCI_SUBCLASS_MSC_OTHER              0x80
 257
 258
 259 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
 260
 261 #define PCI_ADDRESS_IO_SPACE                0x00000001
 262 #define PCI_ADDRESS_MEMORY_TYPE_MASK        0x00000006
 263 #define PCI_ADDRESS_MEMORY_PREFETCHABLE     0x00000008
 264
 265 #define PCI_ADDRESS_IO_ADDRESS_MASK         0xfffffffc
 266 #define PCI_ADDRESS_MEMORY_ADDRESS_MASK     0xfffffff0
 267 #define PCI_ADDRESS_ROM_ADDRESS_MASK        0xfffff800
 268
 269 #define PCI_TYPE_32BIT      0
 270 #define PCI_TYPE_20BIT      2
 271 #define PCI_TYPE_64BIT      4
 272
 273
 274 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
 275
 276 #define PCI_ROMADDRESS_ENABLED              0x00000001
 277
 278
 279
 280 typedef struct _PCI_SLOT_NUMBER
 281 {
 282   union
 283     {
 284       struct
 285         {
 286           ULONG DeviceNumber:5;
 287           ULONG FunctionNumber:3;
 288           ULONG Reserved:24;
 289         } bits;
 290       ULONG AsULONG;
 291     } u;
 292 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
 293
 294 #endif /* __USE_W32API */
 295
 296 /* Hal dispatch table */
 297
 298 typedef enum _HAL_QUERY_INFORMATION_CLASS
 299 {
 300   HalInstalledBusInformation,
 301   HalProfileSourceInformation,
 302   HalSystemDockInformation,
 303   HalPowerInformation,
 304   HalProcessorSpeedInformation,
 305   HalCallbackInformation,
 306   HalMapRegisterInformation,
 307   HalMcaLogInformation,
 308   HalFrameBufferCachingInformation,
 309   HalDisplayBiosInformation
 310   /* information levels >= 0x8000000 reserved for OEM use */
 311 } HAL_QUERY_INFORMATION_CLASS, *PHAL_QUERY_INFORMATION_CLASS;
 312
 313
 314 typedef enum _HAL_SET_INFORMATION_CLASS
 315 {
 316   HalProfileSourceInterval,
 317   HalProfileSourceInterruptHandler,
 318   HalMcaRegisterDriver
 319 } HAL_SET_INFORMATION_CLASS, *PHAL_SET_INFORMATION_CLASS;
 320
 321
 322 typedef struct _BUS_HANDLER *PBUS_HANDLER;
 323 typedef struct _DEVICE_HANDLER_OBJECT *PDEVICE_HANDLER_OBJECT;
 324
 325
 326 typedef BOOLEAN STDCALL_FUNC
 327 (*PHAL_RESET_DISPLAY_PARAMETERS)(ULONG Columns, ULONG Rows);
 328
 329 typedef NTSTATUS STDCALL_FUNC
 330 (*pHalQuerySystemInformation)(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 331                               IN ULONG BufferSize,
 332                               IN OUT PVOID Buffer,
 333                               OUT PULONG ReturnedLength);
 334
 335
 336 typedef NTSTATUS STDCALL_FUNC
 337 (*pHalSetSystemInformation)(IN HAL_SET_INFORMATION_CLASS InformationClass,
 338                             IN ULONG BufferSize,
 339                             IN PVOID Buffer);
 340
 341
 342 typedef NTSTATUS STDCALL_FUNC
 343 (*pHalQueryBusSlots)(IN PBUS_HANDLER BusHandler,
 344                      IN ULONG BufferSize,
 345                      OUT PULONG SlotNumbers,
 346                      OUT PULONG ReturnedLength);
 347
 348
 349 /* Control codes of HalDeviceControl function */
 350 #define BCTL_EJECT                              0x0001
 351 #define BCTL_QUERY_DEVICE_ID                    0x0002
 352 #define BCTL_QUERY_DEVICE_UNIQUE_ID             0x0003
 353 #define BCTL_QUERY_DEVICE_CAPABILITIES          0x0004
 354 #define BCTL_QUERY_DEVICE_RESOURCES             0x0005
 355 #define BCTL_QUERY_DEVICE_RESOURCE_REQUIREMENTS 0x0006
 356 #define BCTL_QUERY_EJECT                            0x0007
 357 #define BCTL_SET_LOCK                               0x0008
 358 #define BCTL_SET_POWER                              0x0009
 359 #define BCTL_SET_RESUME                             0x000A
 360 #define BCTL_SET_DEVICE_RESOURCES                   0x000B
 361
 362 /* Defines for BCTL structures */
 363 typedef struct
 364 {
 365   BOOLEAN PowerSupported;
 366   BOOLEAN ResumeSupported;
 367   BOOLEAN LockSupported;
 368   BOOLEAN EjectSupported;
 369   BOOLEAN Removable;
 370 } BCTL_DEVICE_CAPABILITIES, *PBCTL_DEVICE_CAPABILITIES;
 371
 372
 373 typedef struct _DEVICE_CONTROL_CONTEXT
 374 {
 375   NTSTATUS Status;
 376   PDEVICE_HANDLER_OBJECT DeviceHandler;
 377   PDEVICE_OBJECT DeviceObject;
 378   ULONG ControlCode;
 379   PVOID Buffer;
 380   PULONG BufferLength;
 381   PVOID Context;
 382 } DEVICE_CONTROL_CONTEXT, *PDEVICE_CONTROL_CONTEXT;
 383
 384
 385 typedef VOID STDCALL_FUNC
 386 (*PDEVICE_CONTROL_COMPLETION)(IN PDEVICE_CONTROL_CONTEXT ControlContext);
 387
 388
 389 typedef NTSTATUS STDCALL_FUNC
 390 (*pHalDeviceControl)(IN PDEVICE_HANDLER_OBJECT DeviceHandler,
 391                      IN PDEVICE_OBJECT DeviceObject,
 392                      IN ULONG ControlCode,
 393                      IN OUT PVOID Buffer OPTIONAL,
 394                      IN OUT PULONG BufferLength OPTIONAL,
 395                      IN PVOID Context,
 396                      IN PDEVICE_CONTROL_COMPLETION CompletionRoutine);
 397
 398 typedef VOID FASTCALL_FUNC
 399 (*pHalExamineMBR)(IN PDEVICE_OBJECT DeviceObject,
 400                   IN ULONG SectorSize,
 401                   IN ULONG MBRTypeIdentifier,
 402                   OUT PVOID *Buffer);
 403
 404 typedef VOID FASTCALL_FUNC
 405 (*pHalIoAssignDriveLetters)(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 406                             IN PSTRING NtDeviceName,
 407                             OUT PUCHAR NtSystemPath,
 408                             OUT PSTRING NtSystemPathString);
 409
 410 typedef NTSTATUS FASTCALL_FUNC
 411 (*pHalIoReadPartitionTable)(IN PDEVICE_OBJECT DeviceObject,
 412                             IN ULONG SectorSize,
 413                             IN BOOLEAN ReturnRecognizedPartitions,
 414                             OUT PDRIVE_LAYOUT_INFORMATION *PartitionBuffer);
 415
 416 typedef NTSTATUS FASTCALL_FUNC
 417 (*pHalIoSetPartitionInformation)(IN PDEVICE_OBJECT DeviceObject,
 418                                  IN ULONG SectorSize,
 419                                  IN ULONG PartitionNumber,
 420                                  IN ULONG PartitionType);
 421
 422 typedef NTSTATUS FASTCALL_FUNC
 423 (*pHalIoWritePartitionTable)(IN PDEVICE_OBJECT DeviceObject,
 424                              IN ULONG SectorSize,
 425                              IN ULONG SectorsPerTrack,
 426                              IN ULONG NumberOfHeads,
 427                              IN PDRIVE_LAYOUT_INFORMATION PartitionBuffer);
 428
 429 typedef PBUS_HANDLER FASTCALL_FUNC
 430 (*pHalHandlerForBus)(IN INTERFACE_TYPE InterfaceType,
 431                      IN ULONG BusNumber);
 432
 433 typedef VOID FASTCALL_FUNC
 434 (*pHalReferenceBusHandler)(IN PBUS_HANDLER BusHandler);
 435
 436
 437 typedef struct _HAL_DISPATCH
 438 {
 439   ULONG                         Version;
 440   pHalQuerySystemInformation    HalQuerySystemInformation;
 441   pHalSetSystemInformation      HalSetSystemInformation;
 442   pHalQueryBusSlots             HalQueryBusSlots;
 443   pHalDeviceControl             HalDeviceControl;
 444   pHalExamineMBR                HalExamineMBR;
 445   pHalIoAssignDriveLetters      HalIoAssignDriveLetters;
 446   pHalIoReadPartitionTable      HalIoReadPartitionTable;
 447   pHalIoSetPartitionInformation HalIoSetPartitionInformation;
 448   pHalIoWritePartitionTable     HalIoWritePartitionTable;
 449   pHalHandlerForBus             HalReferenceHandlerForBus;
 450   pHalReferenceBusHandler       HalReferenceBusHandler;
 451   pHalReferenceBusHandler       HalDereferenceBusHandler;
 452 } HAL_DISPATCH, *PHAL_DISPATCH;
 453
 454 #ifndef __USE_W32API
 455
 456 #ifdef __NTOSKRNL__
 457 extern HAL_DISPATCH EXPORTED HalDispatchTable;
 458 #else
 459 extern PHAL_DISPATCH IMPORTED HalDispatchTable;
 460 #endif
 461
 462 #endif /* !__USE_W32API */
 463
 464 #ifdef __NTOSKRNL__
 465 #define HALDISPATCH (&HalDispatchTable)
 466 #else
 467 #define HALDISPATCH ((PHAL_DISPATCH)&HalDispatchTable)
 468 #endif
 469
 470
 471 #define HAL_DISPATCH_VERSION            1
 472 #define HalDispatchTableVersion         HALDISPATCH->Version
 473 #define HalQuerySystemInformation       HALDISPATCH->HalQuerySystemInformation
 474 #define HalSetSystemInformation         HALDISPATCH->HalSetSystemInformation
 475 #define HalQueryBusSlots                HALDISPATCH->HalQueryBusSlots
 476 #define HalDeviceControl                HALDISPATCH->HalDeviceControl
 477 #define HalExamineMBR                   HALDISPATCH->HalExamineMBR
 478 #define HalIoAssignDriveLetters         HALDISPATCH->HalIoAssignDriveLetters
 479 #define HalIoReadPartitionTable         HALDISPATCH->HalIoReadPartitionTable
 480 #define HalIoSetPartitionInformation    HALDISPATCH->HalIoSetPartitionInformation
 481 #define HalIoWritePartitionTable        HALDISPATCH->HalIoWritePartitionTable
 482 #define HalReferenceHandlerForBus       HALDISPATCH->HalReferenceHandlerForBus
 483 #define HalReferenceBusHandler          HALDISPATCH->HalReferenceBusHandler
 484 #define HalDereferenceBusHandler        HALDISPATCH->HalDereferenceBusHandler
 485
 486
 487 /* Hal private dispatch table */
 488
 489 typedef struct _HAL_PRIVATE_DISPATCH
 490 {
 491   ULONG Version;
 492 } HAL_PRIVATE_DISPATCH, *PHAL_PRIVATE_DISPATCH;
 493
 494 #ifndef __USE_W32API
 495
 496 #ifdef __NTOSKRNL__
 497 extern HAL_PRIVATE_DISPATCH EXPORTED HalPrivateDispatchTable;
 498 #else
 499 extern PHAL_PRIVATE_DISPATCH IMPORTED HalPrivateDispatchTable;
 500 #endif
 501
 502 #endif /* !__USE_W32API */
 503
 504 #define HAL_PRIVATE_DISPATCH_VERSION    1
 505
 506
 507
 508 /*
 509  * Kernel debugger section
 510  */
 511
 512 typedef struct _KD_PORT_INFORMATION
 513 {
 514   ULONG ComPort;
 515   ULONG BaudRate;
 516   ULONG BaseAddress;
 517 } KD_PORT_INFORMATION, *PKD_PORT_INFORMATION;
 518
 519
 520 #ifdef __NTHAL__
 521 extern ULONG EXPORTED KdComPortInUse;
 522 #else
 523 extern ULONG IMPORTED KdComPortInUse;
 524 #endif
 525
 526 #endif /* __INCLUDE_DDK_HALTYPES_H */
 527
 528 /* EOF */