2 * Lowlevel memory managment definitions
8 #define PAGE_MASK(x) ((x)&(~0xfff))
9 #define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
11 /* Memory layout base addresses */
12 #define HYPER_SPACE 0xFFFFF70000000000ULL
13 #define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
14 #define MI_SESSION_SPACE_MINIMUM (PVOID)0xFFFFF90000000000ULL
15 #define MI_SESSION_VIEW_END (PVOID)0xFFFFF97FFF000000ULL
16 #define MI_SESSION_SPACE_END (PVOID)0xFFFFF98000000000ULL
17 #define MI_SYSTEM_PTE_START (PVOID)0xFFFFFAA000000000ULL
18 #define MI_PAGED_POOL_START (PVOID)0xFFFFFA8000000000ULL
19 #define MI_NON_PAGED_SYSTEM_START_MIN 0xFFFFFAA000000000ULL
20 #define MI_PFN_DATABASE (PVOID)0xFFFFFAC000000000ULL
21 #define MI_NONPAGED_POOL_END (PVOID)0xFFFFFAE000000000ULL
22 #define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
23 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
24 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xFFFFF78000001000ULL // CHECKME
27 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
28 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
29 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
30 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
31 #define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
32 #define MI_MAX_FREE_PAGE_LISTS 4
33 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
34 #define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024)
35 #define MI_SESSION_POOL_SIZE (16 * 1024 * 1024)
36 #define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024)
37 #define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024)
38 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
39 MI_SESSION_POOL_SIZE + \
40 MI_SESSION_IMAGE_SIZE + \
41 MI_SESSION_WORKING_SET_SIZE)
42 #define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
43 #define MI_NUMBER_SYSTEM_PTES 22000
47 MmGetPageDirectory(VOID
)
49 return (PULONG64
)__readcr3();
54 MiAddressToPxe(PVOID Address
)
56 ULONG64 Offset
= (ULONG64
)Address
>> (PXI_SHIFT
- 3);
57 Offset
&= PXI_MASK
<< 3;
58 return (PMMPTE
)(PXE_BASE
+ Offset
);
63 MiAddressToPpe(PVOID Address
)
65 ULONG64 Offset
= (ULONG64
)Address
>> (PPI_SHIFT
- 3);
66 Offset
&= 0x3FFFF << 3;
67 return (PMMPTE
)(PPE_BASE
+ Offset
);
72 _MiAddressToPde(PVOID Address
)
74 ULONG64 Offset
= (ULONG64
)Address
>> (PDI_SHIFT
- 3);
75 Offset
&= 0x7FFFFFF << 3;
76 return (PMMPTE
)(PDE_BASE
+ Offset
);
78 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
82 _MiAddressToPte(PVOID Address
)
84 ULONG64 Offset
= (ULONG64
)Address
>> (PTI_SHIFT
- 3);
85 Offset
&= 0xFFFFFFFFFULL
<< 3;
86 return (PMMPTE
)(PTE_BASE
+ Offset
);
88 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
90 /* Convert a PTE into a corresponding address */
93 MiPteToAddress(PMMPTE Pte
)
96 LONG64 Temp
= (LONG64
)Pte
;
104 MiIsPdeForAddressValid(PVOID Address
)
106 return ((MiAddressToPxe(Address
)->u
.Hard
.Valid
) &&
107 (MiAddressToPpe(Address
)->u
.Hard
.Valid
) &&
108 (MiAddressToPde(Address
)->u
.Hard
.Valid
));
111 #define ADDR_TO_PAGE_TABLE(v) (((ULONG_PTR)(v)) / (512 * PAGE_SIZE))
112 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
113 #define ADDR_TO_PTE_OFFSET(v) ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE)
115 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
117 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
118 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
119 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
120 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
122 /* We don't use these hacks */
125 MmUpdatePageDir(PEPROCESS Process
, PVOID Address
, ULONG Size
)
132 MmInitGlobalKernelPageDirectory(VOID
)
137 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
138 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
140 /* Easy accessing PFN in PTE */
141 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
143 // FIXME, only copied from x86
144 #define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
145 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
146 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
147 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
148 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
149 #if !defined(CONFIG_SMP)
150 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
152 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
154 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
155 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
156 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
157 #if !defined(CONFIG_SMP)
158 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
160 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
164 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
165 ((x) / (4*1024*1024))
167 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
168 ((((x)) % (4*1024*1024)) / (4*1024))
170 #define NR_SECTION_PAGE_TABLES 1024
171 #define NR_SECTION_PAGE_ENTRIES 1024
173 //#define TEB_BASE 0x7FFDE000
175 #define MI_HYPERSPACE_PTES (256 - 1)
176 #define MI_ZERO_PTES (32)
177 #define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
178 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
179 MI_HYPERSPACE_PTES * PAGE_SIZE)
180 #define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
183 /* On x86, these two are the same */
185 #define PMMPDE PMMPTE
188 * FIXME - different architectures have different cache line sizes...
190 #define MM_CACHE_LINE_SIZE 32