reactos/ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * Lowlevel memory managment definitions
   3  */
   4
   5 #pragma once
   6
   7 #define _MI_PAGING_LEVELS 4
   8
   9 /* Helper macros */
  10 #define PAGE_MASK(x)            ((x)&(~0xfff))
  11 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  12
  13 /* Memory layout base addresses */
  14 #define MI_HIGHEST_USER_ADDRESS         (PVOID)0x000007FFFFFEFFFFULL
  15 #define MI_USER_PROBE_ADDRESS           (PVOID)0x000007FFFFFF0000ULL
  16 #define MI_DEFAULT_SYSTEM_RANGE_START   (PVOID)0xFFFF080000000000ULL
  17 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  18 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  19 #define MI_SESSION_SPACE_MINIMUM        (PVOID)0xFFFFF90000000000ULL
  20 #define MI_SESSION_VIEW_END             (PVOID)0xFFFFF97FFF000000ULL
  21 #define MI_SESSION_SPACE_END            (PVOID)0xFFFFF98000000000ULL
  22 #define MI_SYSTEM_PTE_START             (PVOID)0xFFFFFAA000000000ULL
  23 #define MI_PAGED_POOL_START             (PVOID)0xFFFFFA8000000000ULL
  24 #define MI_NON_PAGED_SYSTEM_START_MIN          0xFFFFFAA000000000ULL
  25 #define MI_PFN_DATABASE                 (PVOID)0xFFFFFAC000000000ULL
  26 #define MI_NONPAGED_POOL_END            (PVOID)0xFFFFFAE000000000ULL
  27 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  28 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  29 #define MI_SYSTEM_CACHE_WS_START        (PVOID)0xFFFFF78000001000ULL // CHECKME
  30
  31 #define MI_LOWEST_VAD_ADDRESS           (PVOID)0x000000007FF00000ULL
  32
  33 #define MI_SYSTEM_PTE_BASE              (PVOID)MiAddressToPte(KSEG0_BASE)
  34
  35 /* Memory sizes */
  36 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  37 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
  38 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
  39 #define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128ULL * 1024 * 1024 * 1024)
  40 #define MI_MAX_NONPAGED_POOL_SIZE              (128ULL * 1024 * 1024 * 1024)
  41 #define MI_MAX_FREE_PAGE_LISTS                 4
  42 #define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
  43 #define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
  44 #define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
  45 #define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
  46 #define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
  47 #define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
  48                                                 MI_SESSION_POOL_SIZE + \
  49                                                 MI_SESSION_IMAGE_SIZE + \
  50                                                 MI_SESSION_WORKING_SET_SIZE)
  51 #define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
  52 #define MI_NUMBER_SYSTEM_PTES 22000
  53
  54 #define MI_MIN_SECONDARY_COLORS                 8
  55 #define MI_SECONDARY_COLORS                     64
  56 #define MI_MAX_SECONDARY_COLORS                 1024
  57
  58 #define MI_MIN_ALLOCATION_FRAGMENT              (4 * _1KB)
  59 #define MI_ALLOCATION_FRAGMENT                  (64 * _1KB)
  60 #define MI_MAX_ALLOCATION_FRAGMENT              (2  * _1MB)
  61
  62 #define MM_HIGHEST_VAD_ADDRESS \
  63     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  64
  65 #define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
  66 #define MM_SYSTEM_RANGE_START_WOW64   0x80000000
  67
  68 PULONG64
  69 FORCEINLINE
  70 MmGetPageDirectory(VOID)
  71 {
  72     return (PULONG64)__readcr3();
  73 }
  74
  75 PMMPTE
  76 FORCEINLINE
  77 MiAddressToPxe(PVOID Address)
  78 {
  79     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
  80     Offset &= PXI_MASK << 3;
  81     return (PMMPTE)(PXE_BASE + Offset);
  82 }
  83
  84 PMMPTE
  85 FORCEINLINE
  86 MiAddressToPpe(PVOID Address)
  87 {
  88     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
  89     Offset &= 0x3FFFF << 3;
  90     return (PMMPTE)(PPE_BASE + Offset);
  91 }
  92
  93 PMMPTE
  94 FORCEINLINE
  95 _MiAddressToPde(PVOID Address)
  96 {
  97     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
  98     Offset &= 0x7FFFFFF << 3;
  99     return (PMMPTE)(PDE_BASE + Offset);
 100 }
 101 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
 102
 103 PMMPTE
 104 FORCEINLINE
 105 _MiAddressToPte(PVOID Address)
 106 {
 107     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
 108     Offset &= 0xFFFFFFFFFULL << 3;
 109     return (PMMPTE)(PTE_BASE + Offset);
 110 }
 111 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
 112
 113 ULONG
 114 FORCEINLINE
 115 MiAddressToPti(PVOID Address)
 116 {
 117     return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
 118 }
 119 #define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
 120
 121 ULONG
 122 FORCEINLINE
 123 MiAddressToPxi(PVOID Address)
 124 {
 125     return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
 126 }
 127
 128
 129 /* Convert a PTE into a corresponding address */
 130 PVOID
 131 FORCEINLINE
 132 MiPteToAddress(PMMPTE Pte)
 133 {
 134     /* Use signed math */
 135     LONG64 Temp = (LONG64)Pte;
 136     Temp <<= 25;
 137     Temp >>= 16;
 138     return (PVOID)Temp;
 139 }
 140 #define MiPdeToAddress MiPteToAddress
 141
 142 BOOLEAN
 143 FORCEINLINE
 144 MiIsPdeForAddressValid(PVOID Address)
 145 {
 146     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
 147             (MiAddressToPpe(Address)->u.Hard.Valid) &&
 148             (MiAddressToPde(Address)->u.Hard.Valid));
 149 }
 150
 151 #define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
 152 #define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
 153
 154 #define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
 155 #define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
 156 #define ADDR_TO_PTE_OFFSET(v)  ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
 157
 158 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
 159
 160 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
 161 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
 162 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 163 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 164
 165 FORCEINLINE
 166 VOID
 167 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 168                       IN PMMPTE PointerPte)
 169 {
 170     /* Store the Address */
 171     NewPte->u.Long = (ULONG64)PointerPte;
 172
 173     /* Mark this as a prototype PTE */
 174     NewPte->u.Proto.Prototype = 1;
 175     NewPte->u.Proto.Valid  = 1;
 176     NewPte->u.Proto.ReadOnly = 0;
 177     NewPte->u.Proto.Protection = 0;
 178 }
 179
 180 /* Sign extend 48 bits */
 181 #define MiProtoPteToPte(x)                  \
 182     (PMMPTE)((LONG64)(x)->u.Proto.ProtoAddress)
 183
 184 /* We don't use these hacks */
 185 VOID
 186 FORCEINLINE
 187 MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
 188 {
 189     /* Nothing to do */
 190 }
 191
 192 VOID
 193 FORCEINLINE
 194 MmInitGlobalKernelPageDirectory(VOID)
 195 {
 196     /* Nothing to do */
 197 }
 198
 199 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
 200 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
 201
 202 /* Easy accessing PFN in PTE */
 203 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 204
 205 // FIXME, only copied from x86
 206 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 207 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 208 #define MI_MAKE_ACCESSED_PAGE(x)   ((x)->u.Hard.Accessed = 1)
 209 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 210 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 211 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 212 #define MI_IS_PAGE_LARGE(x)        ((x)->u.Hard.LargePage == 1)
 213 #if !defined(CONFIG_SMP)
 214 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 215 #else
 216 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
 217 #endif
 218 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 219 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 220 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 221 #if !defined(CONFIG_SMP)
 222 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 223 #else
 224 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
 225 #endif
 226
 227 // FIXME!!!
 228 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 229     ((x) / (4*1024*1024))
 230
 231 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 232     ((((x)) % (4*1024*1024)) / (4*1024))
 233
 234 #define NR_SECTION_PAGE_TABLES              1024
 235 #define NR_SECTION_PAGE_ENTRIES             1024
 236
 237 //#define TEB_BASE                            0x7FFDE000
 238
 239 #define MI_HYPERSPACE_PTES                  (256 - 1)
 240 #define MI_ZERO_PTES                        (32)
 241 #define MI_MAPPING_RANGE_START              (ULONG)HYPER_SPACE
 242 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
 243                                              MI_HYPERSPACE_PTES * PAGE_SIZE)
 244 #define MI_DUMMY_PTE                        (PMMPTE)(MI_MAPPING_RANGE_END + \
 245                                                       PAGE_SIZE)
 246 #define MI_VAD_BITMAP                       (PMMPTE)(MI_DUMMY_PTE + \
 247                                                       PAGE_SIZE)
 248 #define MI_WORKING_SET_LIST                 (PMMPTE)(MI_VAD_BITMAP + \
 249                                                       PAGE_SIZE)
 250
 251
 252 /* On x86, these two are the same */
 253 #define MMPDE MMPTE
 254 #define PMMPDE PMMPTE
 255
 256 /*
 257 * FIXME - different architectures have different cache line sizes...
 258 */
 259 #define MM_CACHE_LINE_SIZE                  32
 260