reactos/ntoskrnl/include/internal/i386/mm.h

   1 /*
   2  * Lowlevel memory managment definitions
   3  */
   4
   5 #pragma once
   6
   7 struct _EPROCESS;
   8 PULONG MmGetPageDirectory(VOID);
   9
  10 #define PAGE_MASK(x)            ((x)&(~0xfff))
  11 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  12
  13 /* Base addresses of PTE and PDE */
  14 #define PAGETABLE_MAP       (0xc0000000)
  15 #define PAGEDIRECTORY_MAP   (0xc0000000 + (PAGETABLE_MAP / (1024)))
  16
  17 /* FIXME: These are different for PAE */
  18 #define PTE_BASE    0xC0000000
  19 #define PDE_BASE    0xC0300000
  20 #define PDE_TOP     0xC0300FFF
  21 #define PTE_TOP     0xC03FFFFF
  22 #define HYPER_SPACE 0xC0400000
  23
  24 /* Converting address to a corresponding PDE or PTE entry */
  25 #define MiAddressToPde(x) \
  26     ((PMMPTE)(((((ULONG)(x)) >> 22) << 2) + PAGEDIRECTORY_MAP))
  27 #define MiAddressToPte(x) \
  28     ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PAGETABLE_MAP))
  29 #define MiAddressToPteOffset(x) \
  30     ((((ULONG)(x)) << 10) >> 22)
  31
  32 //
  33 // Convert a PTE into a corresponding address
  34 //
  35 #define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
  36
  37 #define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
  38 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
  39 #define ADDR_TO_PTE_OFFSET(v)  ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
  40
  41 /* Easy accessing PFN in PTE */
  42 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
  43
  44 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
  45 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
  46 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
  47 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
  48 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
  49 #if !defined(CONFIG_SMP)
  50 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
  51 #else
  52 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
  53 #endif
  54 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
  55 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
  56 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
  57 #if !defined(CONFIG_SMP)
  58 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
  59 #else
  60 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
  61 #endif
  62
  63 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
  64     ((x) / (4*1024*1024))
  65
  66 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
  67     ((((x)) % (4*1024*1024)) / (4*1024))
  68
  69 #define NR_SECTION_PAGE_TABLES              1024
  70 #define NR_SECTION_PAGE_ENTRIES             1024
  71
  72 #define TEB_BASE                            0x7FFDE000
  73
  74 #define MI_HYPERSPACE_PTES                  (256 - 1)
  75 #define MI_ZERO_PTES                        (32)
  76 #define MI_MAPPING_RANGE_START              (ULONG)HYPER_SPACE
  77 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
  78                                              MI_HYPERSPACE_PTES * PAGE_SIZE)
  79 #define MI_ZERO_PTE                         (PMMPTE)(MI_MAPPING_RANGE_END + \
  80                                              PAGE_SIZE)
  81
  82 /* On x86, these two are the same */
  83 #define MMPDE MMPTE
  84 #define PMMPDE PMMPTE
  85
  86 /*
  87 * FIXME - different architectures have different cache line sizes...
  88 */
  89 #define MM_CACHE_LINE_SIZE                  32