reactos/ntoskrnl/mm/ARM3/miarm.h

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/miarm.h
   5  * PURPOSE:         ARM Memory Manager Header
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 #ifndef _M_AMD64
  10
  11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING   ((255 * _1MB) >> PAGE_SHIFT)
  12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING          ((19 * _1MB) >> PAGE_SHIFT)
  13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST           ((32 * _1MB) >> PAGE_SHIFT)
  14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE          (128 * _1MB)
  15 #define MI_MAX_NONPAGED_POOL_SIZE               (128 * _1MB)
  16 #define MI_MAX_FREE_PAGE_LISTS                  4
  17
  18 #define MI_MIN_INIT_PAGED_POOLSIZE              (32 * _1MB)
  19
  20 #define MI_SESSION_VIEW_SIZE                    (20 * _1MB)
  21 #define MI_SESSION_POOL_SIZE                    (16 * _1MB)
  22 #define MI_SESSION_IMAGE_SIZE                   (8 * _1MB)
  23 #define MI_SESSION_WORKING_SET_SIZE             (4 * _1MB)
  24 #define MI_SESSION_SIZE                         (MI_SESSION_VIEW_SIZE + \
  25                                                  MI_SESSION_POOL_SIZE + \
  26                                                  MI_SESSION_IMAGE_SIZE + \
  27                                                  MI_SESSION_WORKING_SET_SIZE)
  28
  29 #define MI_SYSTEM_VIEW_SIZE                     (16 * _1MB)
  30
  31 #define MI_SYSTEM_CACHE_WS_START                (PVOID)0xC0C00000
  32 #define MI_PAGED_POOL_START                     (PVOID)0xE1000000
  33 #define MI_NONPAGED_POOL_END                    (PVOID)0xFFBE0000
  34 #define MI_DEBUG_MAPPING                        (PVOID)0xFFBFF000
  35
  36 #define MI_SYSTEM_PTE_BASE                      (PVOID)MiAddressToPte(NULL)
  37
  38 #define MI_MIN_SECONDARY_COLORS                 8
  39 #define MI_SECONDARY_COLORS                     64
  40 #define MI_MAX_SECONDARY_COLORS                 1024
  41
  42 #define MI_MIN_ALLOCATION_FRAGMENT              (4 * _1KB)
  43 #define MI_ALLOCATION_FRAGMENT                  (64 * _1KB)
  44 #define MI_MAX_ALLOCATION_FRAGMENT              (2  * _1MB)
  45
  46 #define MM_HIGHEST_VAD_ADDRESS \
  47     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  48 #define MI_LOWEST_VAD_ADDRESS                   (PVOID)MM_LOWEST_USER_ADDRESS
  49
  50 #endif /* !_M_AMD64 */
  51
  52 /* Make the code cleaner with some definitions for size multiples */
  53 #define _1KB (1024u)
  54 #define _1MB (1024 * _1KB)
  55 #define _1GB (1024 * _1MB)
  56
  57 /* Everyone loves 64K */
  58 #define _64K (64 * _1KB)
  59
  60 /* Area mapped by a PDE */
  61 #define PDE_MAPPED_VA  (PTE_COUNT * PAGE_SIZE)
  62
  63 /* Size of a page table */
  64 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
  65
  66 /* Size of a page directory */
  67 #define PD_SIZE  (PDE_COUNT * sizeof(MMPDE))
  68
  69 /* Size of all page directories for a process */
  70 #define SYSTEM_PD_SIZE (PD_COUNT * PD_SIZE)
  71
  72 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
  73 #ifdef _M_IX86
  74 #define PD_COUNT  1
  75 #define PDE_COUNT 1024
  76 #define PTE_COUNT 1024
  77 C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
  78 #elif _M_ARM
  79 #define PD_COUNT  1
  80 #define PDE_COUNT 4096
  81 #define PTE_COUNT 256
  82 #else
  83 #define PD_COUNT  PPE_PER_PAGE
  84 #define PDE_COUNT PDE_PER_PAGE
  85 #define PTE_COUNT PTE_PER_PAGE
  86 #endif
  87
  88 #ifdef _M_IX86
  89 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_I386
  90 #elif _M_ARM
  91 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_ARM
  92 #elif _M_AMD64
  93 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_AMD64
  94 #else
  95 #error Define these please!
  96 #endif
  97
  98 //
  99 // Protection Bits part of the internal memory manager Protection Mask
 100 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
 101 // and public assertions.
 102 //
 103 #define MM_ZERO_ACCESS         0
 104 #define MM_READONLY            1
 105 #define MM_EXECUTE             2
 106 #define MM_EXECUTE_READ        3
 107 #define MM_READWRITE           4
 108 #define MM_WRITECOPY           5
 109 #define MM_EXECUTE_READWRITE   6
 110 #define MM_EXECUTE_WRITECOPY   7
 111 #define MM_NOCACHE             8
 112 #define MM_DECOMMIT            0x10
 113 #define MM_NOACCESS            (MM_DECOMMIT | MM_NOCACHE)
 114 #define MM_INVALID_PROTECTION  0xFFFFFFFF
 115
 116 //
 117 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
 118 // The Memory Manager's definition define the attributes that must be preserved
 119 // and these PTE definitions describe the attributes in the hardware sense. This
 120 // helps deal with hardware differences between the actual boolean expression of
 121 // the argument.
 122 //
 123 // For example, in the logical attributes, we want to express read-only as a flag
 124 // but on x86, it is writability that must be set. On the other hand, on x86, just
 125 // like in the kernel, it is disabling the caches that requires a special flag,
 126 // while on certain architectures such as ARM, it is enabling the cache which
 127 // requires a flag.
 128 //
 129 #if defined(_M_IX86) || defined(_M_AMD64)
 130 //
 131 // Access Flags
 132 //
 133 #define PTE_READONLY            0 // Doesn't exist on x86
 134 #define PTE_EXECUTE             0 // Not worrying about NX yet
 135 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 136 #define PTE_READWRITE           0x2
 137 #define PTE_WRITECOPY           0x200
 138 #define PTE_EXECUTE_READWRITE   0x2 // Not worrying about NX yet
 139 #define PTE_EXECUTE_WRITECOPY   0x200
 140 #define PTE_PROTOTYPE           0x400
 141 //
 142 // Cache flags
 143 //
 144 #define PTE_ENABLE_CACHE        0
 145 #define PTE_DISABLE_CACHE       0x10
 146 #define PTE_WRITECOMBINED_CACHE 0x10
 147 #elif defined(_M_ARM)
 148 #define PTE_READONLY            0x200
 149 #define PTE_EXECUTE             0 // Not worrying about NX yet
 150 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 151 #define PTE_READWRITE           0 // Doesn't exist on ARM
 152 #define PTE_WRITECOPY           0 // Doesn't exist on ARM
 153 #define PTE_EXECUTE_READWRITE   0 // Not worrying about NX yet
 154 #define PTE_EXECUTE_WRITECOPY   0 // Not worrying about NX yet
 155 #define PTE_PROTOTYPE           0x400 // Using the Shared bit
 156 //
 157 // Cache flags
 158 //
 159 #define PTE_ENABLE_CACHE        0
 160 #define PTE_DISABLE_CACHE       0x10
 161 #define PTE_WRITECOMBINED_CACHE 0x10
 162 #else
 163 #error Define these please!
 164 #endif
 165
 166 extern const ULONG MmProtectToPteMask[32];
 167 extern const ULONG MmProtectToValue[32];
 168
 169 //
 170 // Assertions for session images, addresses, and PTEs
 171 //
 172 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
 173     (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
 174
 175 #define MI_IS_SESSION_ADDRESS(Address) \
 176     (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
 177
 178 #define MI_IS_SESSION_PTE(Pte) \
 179     ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
 180
 181 #define MI_IS_PAGE_TABLE_ADDRESS(Address) \
 182     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)PTE_TOP))
 183
 184 #define MI_IS_SYSTEM_PAGE_TABLE_ADDRESS(Address) \
 185     (((Address) >= (PVOID)MiAddressToPte(MmSystemRangeStart)) && ((Address) <= (PVOID)PTE_TOP))
 186
 187 #define MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address) \
 188     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)MmHyperSpaceEnd))
 189
 190 //
 191 // Corresponds to MMPTE_SOFTWARE.Protection
 192 //
 193 #ifdef _M_IX86
 194 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 195 #elif _M_ARM
 196 #define MM_PTE_SOFTWARE_PROTECTION_BITS   6
 197 #elif _M_AMD64
 198 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 199 #else
 200 #error Define these please!
 201 #endif
 202
 203 //
 204 // Creates a software PTE with the given protection
 205 //
 206 #define MI_MAKE_SOFTWARE_PTE(p, x)          ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
 207
 208 //
 209 // Marks a PTE as deleted
 210 //
 211 #define MI_SET_PFN_DELETED(x)               ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
 212 #define MI_IS_PFN_DELETED(x)                ((ULONG_PTR)((x)->PteAddress) & 1)
 213
 214 //
 215 // Special values for LoadedImports
 216 //
 217 #define MM_SYSLDR_NO_IMPORTS   (PVOID)0xFFFFFFFE
 218 #define MM_SYSLDR_BOOT_LOADED  (PVOID)0xFFFFFFFF
 219 #define MM_SYSLDR_SINGLE_ENTRY 0x1
 220
 221 #if defined(_M_IX86) || defined(_M_ARM)
 222 //
 223 // PFN List Sentinel
 224 //
 225 #define LIST_HEAD 0xFFFFFFFF
 226
 227 //
 228 // Because GCC cannot automatically downcast 0xFFFFFFFF to lesser-width bits,
 229 // we need a manual definition suited to the number of bits in the PteFrame.
 230 // This is used as a LIST_HEAD for the colored list
 231 //
 232 #define COLORED_LIST_HEAD ((1 << 25) - 1) // 0x1FFFFFF
 233 #elif defined(_M_AMD64)
 234 #define LIST_HEAD 0xFFFFFFFFFFFFFFFFLL
 235 #define COLORED_LIST_HEAD ((1 << 57) - 1) // 0x1FFFFFFFFFFFFFFLL
 236 #else
 237 #error Define these please!
 238 #endif
 239
 240 //
 241 // Special IRQL value (found in assertions)
 242 //
 243 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
 244
 245 //
 246 // Returns the color of a page
 247 //
 248 #define MI_GET_PAGE_COLOR(x)                ((x) & MmSecondaryColorMask)
 249 #define MI_GET_NEXT_COLOR(x)                (MI_GET_PAGE_COLOR(++MmSystemPageColor))
 250 #define MI_GET_NEXT_PROCESS_COLOR(x)        (MI_GET_PAGE_COLOR(++(x)->NextPageColor))
 251
 252 #ifndef _M_AMD64
 253 //
 254 // Decodes a Prototype PTE into the underlying PTE
 255 //
 256 #define MiProtoPteToPte(x)                  \
 257     (PMMPTE)((ULONG_PTR)MmPagedPoolStart +  \
 258              (((x)->u.Proto.ProtoAddressHigh << 7) | (x)->u.Proto.ProtoAddressLow))
 259 #endif
 260
 261 //
 262 // Prototype PTEs that don't yet have a pagefile association
 263 //
 264 #define MI_PTE_LOOKUP_NEEDED 0xFFFFF
 265
 266 //
 267 // System views are binned into 64K chunks
 268 //
 269 #define MI_SYSTEM_VIEW_BUCKET_SIZE  _64K
 270
 271 //
 272 // FIXFIX: These should go in ex.h after the pool merge
 273 //
 274 #ifdef _M_AMD64
 275 #define POOL_BLOCK_SIZE 16
 276 #else
 277 #define POOL_BLOCK_SIZE  8
 278 #endif
 279 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
 280 #define BASE_POOL_TYPE_MASK 1
 281 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
 282
 283 typedef struct _POOL_DESCRIPTOR
 284 {
 285     POOL_TYPE PoolType;
 286     ULONG PoolIndex;
 287     ULONG RunningAllocs;
 288     ULONG RunningDeAllocs;
 289     ULONG TotalPages;
 290     ULONG TotalBigPages;
 291     ULONG Threshold;
 292     PVOID LockAddress;
 293     PVOID PendingFrees;
 294     LONG PendingFreeDepth;
 295     SIZE_T TotalBytes;
 296     SIZE_T Spare0;
 297     LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
 298 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 299
 300 typedef struct _POOL_HEADER
 301 {
 302     union
 303     {
 304         struct
 305         {
 306 #ifdef _M_AMD64
 307             ULONG PreviousSize:8;
 308             ULONG PoolIndex:8;
 309             ULONG BlockSize:8;
 310             ULONG PoolType:8;
 311 #else
 312             USHORT PreviousSize:9;
 313             USHORT PoolIndex:7;
 314             USHORT BlockSize:9;
 315             USHORT PoolType:7;
 316 #endif
 317         };
 318         ULONG Ulong1;
 319     };
 320 #ifdef _M_AMD64
 321     ULONG PoolTag;
 322 #endif
 323     union
 324     {
 325 #ifdef _M_AMD64
 326         PEPROCESS ProcessBilled;
 327 #else
 328         ULONG PoolTag;
 329 #endif
 330         struct
 331         {
 332             USHORT AllocatorBackTraceIndex;
 333             USHORT PoolTagHash;
 334         };
 335     };
 336 } POOL_HEADER, *PPOOL_HEADER;
 337
 338 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
 339 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
 340
 341 extern ULONG ExpNumberOfPagedPools;
 342 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
 343 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
 344 extern PVOID PoolTrackTable;
 345
 346 //
 347 // END FIXFIX
 348 //
 349
 350 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
 351 {
 352     LIST_ENTRY Links;
 353     UNICODE_STRING BaseName;
 354 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
 355
 356 typedef enum _MMSYSTEM_PTE_POOL_TYPE
 357 {
 358     SystemPteSpace,
 359     NonPagedPoolExpansion,
 360     MaximumPtePoolTypes
 361 } MMSYSTEM_PTE_POOL_TYPE;
 362
 363 typedef enum _MI_PFN_CACHE_ATTRIBUTE
 364 {
 365     MiNonCached,
 366     MiCached,
 367     MiWriteCombined,
 368     MiNotMapped
 369 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
 370
 371 typedef struct _PHYSICAL_MEMORY_RUN
 372 {
 373     ULONG BasePage;
 374     ULONG PageCount;
 375 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
 376
 377 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
 378 {
 379     ULONG NumberOfRuns;
 380     ULONG NumberOfPages;
 381     PHYSICAL_MEMORY_RUN Run[1];
 382 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
 383
 384 typedef struct _MMCOLOR_TABLES
 385 {
 386     PFN_NUMBER Flink;
 387     PVOID Blink;
 388     PFN_NUMBER Count;
 389 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 390
 391 typedef struct _MI_LARGE_PAGE_RANGES
 392 {
 393     PFN_NUMBER StartFrame;
 394     PFN_NUMBER LastFrame;
 395 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
 396
 397 typedef struct _MMVIEW
 398 {
 399     ULONG_PTR Entry;
 400     PCONTROL_AREA ControlArea;
 401 } MMVIEW, *PMMVIEW;
 402
 403 typedef struct _MMSESSION
 404 {
 405     KGUARDED_MUTEX SystemSpaceViewLock;
 406     PKGUARDED_MUTEX SystemSpaceViewLockPointer;
 407     PCHAR SystemSpaceViewStart;
 408     PMMVIEW SystemSpaceViewTable;
 409     ULONG SystemSpaceHashSize;
 410     ULONG SystemSpaceHashEntries;
 411     ULONG SystemSpaceHashKey;
 412     ULONG BitmapFailures;
 413     PRTL_BITMAP SystemSpaceBitMap;
 414 } MMSESSION, *PMMSESSION;
 415
 416 extern MMPTE HyperTemplatePte;
 417 extern MMPDE ValidKernelPde;
 418 extern MMPTE ValidKernelPte;
 419 extern MMPDE DemandZeroPde;
 420 extern MMPTE DemandZeroPte;
 421 extern MMPTE PrototypePte;
 422 extern BOOLEAN MmLargeSystemCache;
 423 extern BOOLEAN MmZeroPageFile;
 424 extern BOOLEAN MmProtectFreedNonPagedPool;
 425 extern BOOLEAN MmTrackLockedPages;
 426 extern BOOLEAN MmTrackPtes;
 427 extern BOOLEAN MmDynamicPfn;
 428 extern BOOLEAN MmMirroring;
 429 extern BOOLEAN MmMakeLowMemory;
 430 extern BOOLEAN MmEnforceWriteProtection;
 431 extern SIZE_T MmAllocationFragment;
 432 extern ULONG MmConsumedPoolPercentage;
 433 extern ULONG MmVerifyDriverBufferType;
 434 extern ULONG MmVerifyDriverLevel;
 435 extern WCHAR MmVerifyDriverBuffer[512];
 436 extern WCHAR MmLargePageDriverBuffer[512];
 437 extern LIST_ENTRY MiLargePageDriverList;
 438 extern BOOLEAN MiLargePageAllDrivers;
 439 extern ULONG MmVerifyDriverBufferLength;
 440 extern ULONG MmLargePageDriverBufferLength;
 441 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
 442 extern SIZE_T MmMaximumNonPagedPoolInBytes;
 443 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
 444 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
 445 extern PVOID MmNonPagedSystemStart;
 446 extern PVOID MmNonPagedPoolStart;
 447 extern PVOID MmNonPagedPoolExpansionStart;
 448 extern PVOID MmNonPagedPoolEnd;
 449 extern SIZE_T MmSizeOfPagedPoolInBytes;
 450 extern PVOID MmPagedPoolStart;
 451 extern PVOID MmPagedPoolEnd;
 452 extern PVOID MmSessionBase;
 453 extern SIZE_T MmSessionSize;
 454 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
 455 extern PMMPTE MiFirstReservedZeroingPte;
 456 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
 457 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
 458 extern SIZE_T MmBootImageSize;
 459 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
 460 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
 461 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
 462 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
 463 extern ULONG_PTR MxPfnAllocation;
 464 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
 465 extern RTL_BITMAP MiPfnBitMap;
 466 extern KGUARDED_MUTEX MmPagedPoolMutex;
 467 extern PVOID MmPagedPoolStart;
 468 extern PVOID MmPagedPoolEnd;
 469 extern PVOID MmNonPagedSystemStart;
 470 extern PVOID MiSystemViewStart;
 471 extern SIZE_T MmSystemViewSize;
 472 extern PVOID MmSessionBase;
 473 extern PVOID MiSessionSpaceEnd;
 474 extern PMMPTE MiSessionImagePteStart;
 475 extern PMMPTE MiSessionImagePteEnd;
 476 extern PMMPTE MiSessionBasePte;
 477 extern PMMPTE MiSessionLastPte;
 478 extern SIZE_T MmSizeOfPagedPoolInBytes;
 479 extern PMMPDE MmSystemPagePtes;
 480 extern PVOID MmSystemCacheStart;
 481 extern PVOID MmSystemCacheEnd;
 482 extern MMSUPPORT MmSystemCacheWs;
 483 extern SIZE_T MmAllocatedNonPagedPool;
 484 extern ULONG_PTR MmSubsectionBase;
 485 extern ULONG MmSpecialPoolTag;
 486 extern PVOID MmHyperSpaceEnd;
 487 extern PMMWSL MmSystemCacheWorkingSetList;
 488 extern SIZE_T MmMinimumNonPagedPoolSize;
 489 extern ULONG MmMinAdditionNonPagedPoolPerMb;
 490 extern SIZE_T MmDefaultMaximumNonPagedPool;
 491 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
 492 extern ULONG MmSecondaryColors;
 493 extern ULONG MmSecondaryColorMask;
 494 extern ULONG_PTR MmNumberOfSystemPtes;
 495 extern ULONG MmMaximumNonPagedPoolPercent;
 496 extern ULONG MmLargeStackSize;
 497 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
 498 extern ULONG MmProductType;
 499 extern MM_SYSTEMSIZE MmSystemSize;
 500 extern PKEVENT MiLowMemoryEvent;
 501 extern PKEVENT MiHighMemoryEvent;
 502 extern PKEVENT MiLowPagedPoolEvent;
 503 extern PKEVENT MiHighPagedPoolEvent;
 504 extern PKEVENT MiLowNonPagedPoolEvent;
 505 extern PKEVENT MiHighNonPagedPoolEvent;
 506 extern PFN_NUMBER MmLowMemoryThreshold;
 507 extern PFN_NUMBER MmHighMemoryThreshold;
 508 extern PFN_NUMBER MiLowPagedPoolThreshold;
 509 extern PFN_NUMBER MiHighPagedPoolThreshold;
 510 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
 511 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
 512 extern PFN_NUMBER MmMinimumFreePages;
 513 extern PFN_NUMBER MmPlentyFreePages;
 514 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
 515 extern PFN_NUMBER MmResidentAvailablePages;
 516 extern PFN_NUMBER MmResidentAvailableAtInit;
 517 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
 518 extern PFN_NUMBER MmTotalSystemDriverPages;
 519 extern PVOID MiSessionImageStart;
 520 extern PVOID MiSessionImageEnd;
 521 extern PMMPTE MiHighestUserPte;
 522 extern PMMPDE MiHighestUserPde;
 523 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
 524 extern PMMPTE MmSharedUserDataPte;
 525 extern LIST_ENTRY MmProcessList;
 526 extern BOOLEAN MmZeroingPageThreadActive;
 527 extern KEVENT MmZeroingPageEvent;
 528 extern ULONG MmSystemPageColor;
 529 extern ULONG MmProcessColorSeed;
 530 extern PMMWSL MmWorkingSetList;
 531
 532 //
 533 // Figures out the hardware bits for a PTE
 534 //
 535 ULONG
 536 FORCEINLINE
 537 MiDetermineUserGlobalPteMask(IN PVOID PointerPte)
 538 {
 539     MMPTE TempPte;
 540
 541     /* Start fresh */
 542     TempPte.u.Long = 0;
 543
 544     /* Make it valid and accessed */
 545     TempPte.u.Hard.Valid = TRUE;
 546     MI_MAKE_ACCESSED_PAGE(&TempPte);
 547
 548     /* Is this for user-mode? */
 549     if ((PointerPte <= (PVOID)MiHighestUserPte) ||
 550         ((PointerPte >= (PVOID)MiAddressToPde(NULL)) &&
 551          (PointerPte <= (PVOID)MiHighestUserPde)))
 552     {
 553         /* Set the owner bit */
 554         MI_MAKE_OWNER_PAGE(&TempPte);
 555     }
 556
 557     /* FIXME: We should also set the global bit */
 558
 559     /* Return the protection */
 560     return TempPte.u.Long;
 561 }
 562
 563 //
 564 // Creates a valid kernel PTE with the given protection
 565 //
 566 FORCEINLINE
 567 VOID
 568 MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte,
 569                             IN PMMPTE MappingPte,
 570                             IN ULONG ProtectionMask,
 571                             IN PFN_NUMBER PageFrameNumber)
 572 {
 573     /* Only valid for kernel, non-session PTEs */
 574     ASSERT(MappingPte > MiHighestUserPte);
 575     ASSERT(!MI_IS_SESSION_PTE(MappingPte));
 576     ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
 577
 578     /* Start fresh */
 579     *NewPte = ValidKernelPte;
 580
 581     /* Set the protection and page */
 582     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 583     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 584 }
 585
 586 //
 587 // Creates a valid PTE with the given protection
 588 //
 589 FORCEINLINE
 590 VOID
 591 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
 592                      IN PMMPTE MappingPte,
 593                      IN ULONG ProtectionMask,
 594                      IN PFN_NUMBER PageFrameNumber)
 595 {
 596     /* Set the protection and page */
 597     NewPte->u.Long = MiDetermineUserGlobalPteMask(MappingPte);
 598     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 599     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 600 }
 601
 602 //
 603 // Creates a valid user PTE with the given protection
 604 //
 605 FORCEINLINE
 606 VOID
 607 MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte,
 608                           IN PMMPTE MappingPte,
 609                           IN ULONG ProtectionMask,
 610                           IN PFN_NUMBER PageFrameNumber)
 611 {
 612     /* Only valid for kernel, non-session PTEs */
 613     ASSERT(MappingPte <= MiHighestUserPte);
 614
 615     /* Start fresh */
 616     *NewPte = ValidKernelPte;
 617
 618     /* Set the protection and page */
 619     NewPte->u.Hard.Owner = TRUE;
 620     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 621     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 622 }
 623
 624 #ifndef _M_AMD64
 625 //
 626 // Builds a Prototype PTE for the address of the PTE
 627 //
 628 FORCEINLINE
 629 VOID
 630 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 631                       IN PMMPTE PointerPte)
 632 {
 633     ULONG_PTR Offset;
 634
 635     /* Mark this as a prototype */
 636     NewPte->u.Long = 0;
 637     NewPte->u.Proto.Prototype = 1;
 638
 639     /*
 640      * Prototype PTEs are only valid in paged pool by design, this little trick
 641      * lets us only use 28 bits for the adress of the PTE
 642      */
 643     Offset = (ULONG_PTR)PointerPte - (ULONG_PTR)MmPagedPoolStart;
 644
 645     /* 7 bits go in the "low", and the other 21 bits go in the "high" */
 646     NewPte->u.Proto.ProtoAddressLow = Offset & 0x7F;
 647     NewPte->u.Proto.ProtoAddressHigh = (Offset & 0xFFFFFF80) >> 7;
 648     ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
 649 }
 650 #endif
 651
 652 //
 653 // Returns if the page is physically resident (ie: a large page)
 654 // FIXFIX: CISC/x86 only?
 655 //
 656 FORCEINLINE
 657 BOOLEAN
 658 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
 659 {
 660     PMMPDE PointerPde;
 661
 662     /* Large pages are never paged out, always physically resident */
 663     PointerPde = MiAddressToPde(Address);
 664     return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
 665 }
 666
 667 //
 668 // Writes a valid PTE
 669 //
 670 VOID
 671 FORCEINLINE
 672 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
 673                    IN MMPTE TempPte)
 674 {
 675     /* Write the valid PTE */
 676     ASSERT(PointerPte->u.Hard.Valid == 0);
 677     ASSERT(TempPte.u.Hard.Valid == 1);
 678     *PointerPte = TempPte;
 679 }
 680
 681 //
 682 // Writes an invalid PTE
 683 //
 684 VOID
 685 FORCEINLINE
 686 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
 687                      IN MMPTE InvalidPte)
 688 {
 689     /* Write the invalid PTE */
 690     ASSERT(InvalidPte.u.Hard.Valid == 0);
 691     *PointerPte = InvalidPte;
 692 }
 693
 694 //
 695 // Writes a valid PDE
 696 //
 697 VOID
 698 FORCEINLINE
 699 MI_WRITE_VALID_PDE(IN PMMPDE PointerPde,
 700                    IN MMPDE TempPde)
 701 {
 702     /* Write the valid PDE */
 703     ASSERT(PointerPde->u.Hard.Valid == 0);
 704     ASSERT(TempPde.u.Hard.Valid == 1);
 705     *PointerPde = TempPde;
 706 }
 707
 708 //
 709 // Writes an invalid PDE
 710 //
 711 VOID
 712 FORCEINLINE
 713 MI_WRITE_INVALID_PDE(IN PMMPDE PointerPde,
 714                      IN MMPDE InvalidPde)
 715 {
 716     /* Write the invalid PDE */
 717     ASSERT(InvalidPde.u.Hard.Valid == 0);
 718     *PointerPde = InvalidPde;
 719 }
 720
 721 //
 722 // Checks if the thread already owns a working set
 723 //
 724 FORCEINLINE
 725 BOOLEAN
 726 MM_ANY_WS_LOCK_HELD(IN PETHREAD Thread)
 727 {
 728     /* If any of these are held, return TRUE */
 729     return ((Thread->OwnsProcessWorkingSetExclusive) ||
 730             (Thread->OwnsProcessWorkingSetShared) ||
 731             (Thread->OwnsSystemWorkingSetExclusive) ||
 732             (Thread->OwnsSystemWorkingSetShared) ||
 733             (Thread->OwnsSessionWorkingSetExclusive) ||
 734             (Thread->OwnsSessionWorkingSetShared));
 735 }
 736
 737 //
 738 // Checks if the process owns the working set lock
 739 //
 740 FORCEINLINE
 741 BOOLEAN
 742 MI_WS_OWNER(IN PEPROCESS Process)
 743 {
 744     /* Check if this process is the owner, and that the thread owns the WS */
 745     return ((KeGetCurrentThread()->ApcState.Process == &Process->Pcb) &&
 746             ((PsGetCurrentThread()->OwnsProcessWorkingSetExclusive) ||
 747              (PsGetCurrentThread()->OwnsProcessWorkingSetShared)));
 748 }
 749
 750 //
 751 // Locks the working set for the given process
 752 //
 753 FORCEINLINE
 754 VOID
 755 MiLockProcessWorkingSet(IN PEPROCESS Process,
 756                         IN PETHREAD Thread)
 757 {
 758     /* Shouldn't already be owning the process working set */
 759     ASSERT(Thread->OwnsProcessWorkingSetShared == FALSE);
 760     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 761
 762     /* Block APCs, make sure that still nothing is already held */
 763     KeEnterGuardedRegion();
 764     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 765
 766     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 767
 768     /* FIXME: This also can't be checked because Vm is used by MAREAs) */
 769     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 770
 771     /* Okay, now we can own it exclusively */
 772     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 773     Thread->OwnsProcessWorkingSetExclusive = TRUE;
 774 }
 775
 776 //
 777 // Unlocks the working set for the given process
 778 //
 779 FORCEINLINE
 780 VOID
 781 MiUnlockProcessWorkingSet(IN PEPROCESS Process,
 782                           IN PETHREAD Thread)
 783 {
 784     /* Make sure this process really is owner, and it was a safe acquisition */
 785     ASSERT(MI_WS_OWNER(Process));
 786     /* This can't be checked because Vm is used by MAREAs) */
 787     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 788
 789     /* The thread doesn't own it anymore */
 790     ASSERT(Thread->OwnsProcessWorkingSetExclusive == TRUE);
 791     Thread->OwnsProcessWorkingSetExclusive = FALSE;
 792
 793     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 794
 795     /* Unblock APCs */
 796     KeLeaveGuardedRegion();
 797 }
 798
 799 //
 800 // Locks the working set
 801 //
 802 FORCEINLINE
 803 VOID
 804 MiLockWorkingSet(IN PETHREAD Thread,
 805                  IN PMMSUPPORT WorkingSet)
 806 {
 807     /* Block APCs */
 808     KeEnterGuardedRegion();
 809
 810     /* Working set should be in global memory */
 811     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 812
 813     /* Thread shouldn't already be owning something */
 814     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 815
 816     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 817
 818     /* Which working set is this? */
 819     if (WorkingSet == &MmSystemCacheWs)
 820     {
 821         /* Own the system working set */
 822         ASSERT((Thread->OwnsSystemWorkingSetExclusive == FALSE) &&
 823                (Thread->OwnsSystemWorkingSetShared == FALSE));
 824         Thread->OwnsSystemWorkingSetExclusive = TRUE;
 825     }
 826     else if (WorkingSet->Flags.SessionSpace)
 827     {
 828         /* We don't implement this yet */
 829         UNIMPLEMENTED;
 830         while (TRUE);
 831     }
 832     else
 833     {
 834         /* Own the process working set */
 835         ASSERT((Thread->OwnsProcessWorkingSetExclusive == FALSE) &&
 836                (Thread->OwnsProcessWorkingSetShared == FALSE));
 837         Thread->OwnsProcessWorkingSetExclusive = TRUE;
 838     }
 839 }
 840
 841 //
 842 // Unlocks the working set
 843 //
 844 FORCEINLINE
 845 VOID
 846 MiUnlockWorkingSet(IN PETHREAD Thread,
 847                    IN PMMSUPPORT WorkingSet)
 848 {
 849     /* Working set should be in global memory */
 850     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 851
 852     /* Which working set is this? */
 853     if (WorkingSet == &MmSystemCacheWs)
 854     {
 855         /* Release the system working set */
 856         ASSERT((Thread->OwnsSystemWorkingSetExclusive == TRUE) ||
 857                (Thread->OwnsSystemWorkingSetShared == TRUE));
 858         Thread->OwnsSystemWorkingSetExclusive = FALSE;
 859     }
 860     else if (WorkingSet->Flags.SessionSpace)
 861     {
 862         /* We don't implement this yet */
 863         UNIMPLEMENTED;
 864         while (TRUE);
 865     }
 866     else
 867     {
 868         /* Release the process working set */
 869         ASSERT((Thread->OwnsProcessWorkingSetExclusive) ||
 870                (Thread->OwnsProcessWorkingSetShared));
 871         Thread->OwnsProcessWorkingSetExclusive = FALSE;
 872     }
 873
 874     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 875
 876     /* Unblock APCs */
 877     KeLeaveGuardedRegion();
 878 }
 879
 880 //
 881 // Returns the ProtoPTE inside a VAD for the given VPN
 882 //
 883 FORCEINLINE
 884 PMMPTE
 885 MI_GET_PROTOTYPE_PTE_FOR_VPN(IN PMMVAD Vad,
 886                              IN ULONG_PTR Vpn)
 887 {
 888     PMMPTE ProtoPte;
 889
 890     /* Find the offset within the VAD's prototype PTEs */
 891     ProtoPte = Vad->FirstPrototypePte + (Vpn - Vad->StartingVpn);
 892     ASSERT(ProtoPte <= Vad->LastContiguousPte);
 893     return ProtoPte;
 894 }
 895
 896 //
 897 // Returns the PFN Database entry for the given page number
 898 // Warning: This is not necessarily a valid PFN database entry!
 899 //
 900 FORCEINLINE
 901 PMMPFN
 902 MI_PFN_ELEMENT(IN PFN_NUMBER Pfn)
 903 {
 904     /* Get the entry */
 905     return &MmPfnDatabase[Pfn];
 906 };
 907
 908 BOOLEAN
 909 NTAPI
 910 MmArmInitSystem(
 911     IN ULONG Phase,
 912     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 913 );
 914
 915 NTSTATUS
 916 NTAPI
 917 MiInitMachineDependent(
 918     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 919 );
 920
 921 VOID
 922 NTAPI
 923 MiComputeColorInformation(
 924     VOID
 925 );
 926
 927 VOID
 928 NTAPI
 929 MiMapPfnDatabase(
 930     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 931 );
 932
 933 VOID
 934 NTAPI
 935 MiInitializeColorTables(
 936     VOID
 937 );
 938
 939 VOID
 940 NTAPI
 941 MiInitializePfnDatabase(
 942     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 943 );
 944
 945 BOOLEAN
 946 NTAPI
 947 MiInitializeMemoryEvents(
 948     VOID
 949 );
 950
 951 PFN_NUMBER
 952 NTAPI
 953 MxGetNextPage(
 954     IN PFN_NUMBER PageCount
 955 );
 956
 957 PPHYSICAL_MEMORY_DESCRIPTOR
 958 NTAPI
 959 MmInitializeMemoryLimits(
 960     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 961     IN PBOOLEAN IncludeType
 962 );
 963
 964 PFN_NUMBER
 965 NTAPI
 966 MiPagesInLoaderBlock(
 967     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 968     IN PBOOLEAN IncludeType
 969 );
 970
 971 VOID
 972 FASTCALL
 973 MiSyncARM3WithROS(
 974     IN PVOID AddressStart,
 975     IN PVOID AddressEnd
 976 );
 977
 978 NTSTATUS
 979 NTAPI
 980 MmArmAccessFault(
 981     IN BOOLEAN StoreInstruction,
 982     IN PVOID Address,
 983     IN KPROCESSOR_MODE Mode,
 984     IN PVOID TrapInformation
 985 );
 986
 987 NTSTATUS
 988 FASTCALL
 989 MiCheckPdeForPagedPool(
 990     IN PVOID Address
 991 );
 992
 993 VOID
 994 NTAPI
 995 MiInitializeNonPagedPool(
 996     VOID
 997 );
 998
 999 VOID
1000 NTAPI
1001 MiInitializeNonPagedPoolThresholds(
1002     VOID
1003 );
1004
1005 VOID
1006 NTAPI
1007 MiInitializePoolEvents(
1008     VOID
1009 );
1010
1011 VOID                      //
1012 NTAPI                     //
1013 InitializePool(           //
1014     IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
1015     IN ULONG Threshold    //
1016 );                        //
1017
1018 VOID
1019 NTAPI
1020 MiInitializeSystemPtes(
1021     IN PMMPTE StartingPte,
1022     IN ULONG NumberOfPtes,
1023     IN MMSYSTEM_PTE_POOL_TYPE PoolType
1024 );
1025
1026 PMMPTE
1027 NTAPI
1028 MiReserveSystemPtes(
1029     IN ULONG NumberOfPtes,
1030     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
1031 );
1032
1033 VOID
1034 NTAPI
1035 MiReleaseSystemPtes(
1036     IN PMMPTE StartingPte,
1037     IN ULONG NumberOfPtes,
1038     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
1039 );
1040
1041
1042 PFN_NUMBER
1043 NTAPI
1044 MiFindContiguousPages(
1045     IN PFN_NUMBER LowestPfn,
1046     IN PFN_NUMBER HighestPfn,
1047     IN PFN_NUMBER BoundaryPfn,
1048     IN PFN_NUMBER SizeInPages,
1049     IN MEMORY_CACHING_TYPE CacheType
1050 );
1051
1052 PVOID
1053 NTAPI
1054 MiCheckForContiguousMemory(
1055     IN PVOID BaseAddress,
1056     IN PFN_NUMBER BaseAddressPages,
1057     IN PFN_NUMBER SizeInPages,
1058     IN PFN_NUMBER LowestPfn,
1059     IN PFN_NUMBER HighestPfn,
1060     IN PFN_NUMBER BoundaryPfn,
1061     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
1062 );
1063
1064 PMDL
1065 NTAPI
1066 MiAllocatePagesForMdl(
1067     IN PHYSICAL_ADDRESS LowAddress,
1068     IN PHYSICAL_ADDRESS HighAddress,
1069     IN PHYSICAL_ADDRESS SkipBytes,
1070     IN SIZE_T TotalBytes,
1071     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
1072     IN ULONG Flags
1073 );
1074
1075 PVOID
1076 NTAPI
1077 MiMapLockedPagesInUserSpace(
1078     IN PMDL Mdl,
1079     IN PVOID BaseVa,
1080     IN MEMORY_CACHING_TYPE CacheType,
1081     IN PVOID BaseAddress
1082 );
1083
1084 VOID
1085 NTAPI
1086 MiUnmapLockedPagesInUserSpace(
1087     IN PVOID BaseAddress,
1088     IN PMDL Mdl
1089 );
1090
1091 VOID
1092 NTAPI
1093 MiInsertPageInList(
1094     IN PMMPFNLIST ListHead,
1095     IN PFN_NUMBER PageFrameIndex
1096 );
1097
1098 VOID
1099 NTAPI
1100 MiUnlinkFreeOrZeroedPage(
1101     IN PMMPFN Entry
1102 );
1103
1104 PFN_NUMBER
1105 NTAPI
1106 MiAllocatePfn(
1107     IN PMMPTE PointerPte,
1108     IN ULONG Protection
1109 );
1110
1111 VOID
1112 NTAPI
1113 MiInitializePfn(
1114     IN PFN_NUMBER PageFrameIndex,
1115     IN PMMPTE PointerPte,
1116     IN BOOLEAN Modified
1117 );
1118
1119 VOID
1120 NTAPI
1121 MiInitializePfnForOtherProcess(
1122     IN PFN_NUMBER PageFrameIndex,
1123     IN PMMPTE PointerPte,
1124     IN PFN_NUMBER PteFrame
1125 );
1126
1127 VOID
1128 NTAPI
1129 MiDecrementShareCount(
1130     IN PMMPFN Pfn1,
1131     IN PFN_NUMBER PageFrameIndex
1132 );
1133
1134 VOID
1135 NTAPI
1136 MiDecrementReferenceCount(
1137     IN PMMPFN Pfn1,
1138     IN PFN_NUMBER PageFrameIndex
1139 );
1140
1141 PFN_NUMBER
1142 NTAPI
1143 MiRemoveAnyPage(
1144     IN ULONG Color
1145 );
1146
1147 PFN_NUMBER
1148 NTAPI
1149 MiRemoveZeroPage(
1150     IN ULONG Color
1151 );
1152
1153 VOID
1154 NTAPI
1155 MiZeroPhysicalPage(
1156     IN PFN_NUMBER PageFrameIndex
1157 );
1158
1159 VOID
1160 NTAPI
1161 MiInsertPageInFreeList(
1162     IN PFN_NUMBER PageFrameIndex
1163 );
1164
1165 PFN_NUMBER
1166 NTAPI
1167 MiDeleteSystemPageableVm(
1168     IN PMMPTE PointerPte,
1169     IN PFN_NUMBER PageCount,
1170     IN ULONG Flags,
1171     OUT PPFN_NUMBER ValidPages
1172 );
1173
1174 PLDR_DATA_TABLE_ENTRY
1175 NTAPI
1176 MiLookupDataTableEntry(
1177     IN PVOID Address
1178 );
1179
1180 VOID
1181 NTAPI
1182 MiInitializeDriverLargePageList(
1183     VOID
1184 );
1185
1186 VOID
1187 NTAPI
1188 MiInitializeLargePageSupport(
1189     VOID
1190 );
1191
1192 VOID
1193 NTAPI
1194 MiSyncCachedRanges(
1195     VOID
1196 );
1197
1198 BOOLEAN
1199 NTAPI
1200 MiIsPfnInUse(
1201     IN PMMPFN Pfn1
1202 );
1203
1204 PMMVAD
1205 NTAPI
1206 MiLocateAddress(
1207     IN PVOID VirtualAddress
1208 );
1209
1210 PMMADDRESS_NODE
1211 NTAPI
1212 MiCheckForConflictingNode(
1213     IN ULONG_PTR StartVpn,
1214     IN ULONG_PTR EndVpn,
1215     IN PMM_AVL_TABLE Table
1216 );
1217
1218 TABLE_SEARCH_RESULT
1219 NTAPI
1220 MiFindEmptyAddressRangeDownTree(
1221     IN SIZE_T Length,
1222     IN ULONG_PTR BoundaryAddress,
1223     IN ULONG_PTR Alignment,
1224     IN PMM_AVL_TABLE Table,
1225     OUT PULONG_PTR Base,
1226     OUT PMMADDRESS_NODE *Parent
1227 );
1228
1229 NTSTATUS
1230 NTAPI
1231 MiFindEmptyAddressRangeInTree(
1232     IN SIZE_T Length,
1233     IN ULONG_PTR Alignment,
1234     IN PMM_AVL_TABLE Table,
1235     OUT PMMADDRESS_NODE *PreviousVad,
1236     OUT PULONG_PTR Base
1237 );
1238
1239 VOID
1240 NTAPI
1241 MiInsertVad(
1242     IN PMMVAD Vad,
1243     IN PEPROCESS Process
1244 );
1245
1246 VOID
1247 NTAPI
1248 MiInsertNode(
1249     IN PMM_AVL_TABLE Table,
1250     IN PMMADDRESS_NODE NewNode,
1251     PMMADDRESS_NODE Parent,
1252     TABLE_SEARCH_RESULT Result
1253 );
1254
1255 VOID
1256 NTAPI
1257 MiRemoveNode(
1258     IN PMMADDRESS_NODE Node,
1259     IN PMM_AVL_TABLE Table
1260 );
1261
1262 PMMADDRESS_NODE
1263 NTAPI
1264 MiGetPreviousNode(
1265     IN PMMADDRESS_NODE Node
1266 );
1267
1268 PMMADDRESS_NODE
1269 NTAPI
1270 MiGetNextNode(
1271     IN PMMADDRESS_NODE Node
1272 );
1273
1274 BOOLEAN
1275 NTAPI
1276 MiInitializeSystemSpaceMap(
1277     IN PVOID InputSession OPTIONAL
1278 );
1279
1280 ULONG
1281 NTAPI
1282 MiMakeProtectionMask(
1283     IN ULONG Protect
1284 );
1285
1286 VOID
1287 NTAPI
1288 MiDeleteVirtualAddresses(
1289     IN ULONG_PTR Va,
1290     IN ULONG_PTR EndingAddress,
1291     IN PMMVAD Vad
1292 );
1293
1294 ULONG
1295 NTAPI
1296 MiMakeSystemAddressValid(
1297     IN PVOID PageTableVirtualAddress,
1298     IN PEPROCESS CurrentProcess
1299 );
1300
1301 ULONG
1302 NTAPI
1303 MiMakeSystemAddressValidPfn(
1304     IN PVOID VirtualAddress,
1305     IN KIRQL OldIrql
1306 );
1307
1308 VOID
1309 NTAPI
1310 MiRemoveMappedView(
1311     IN PEPROCESS CurrentProcess,
1312     IN PMMVAD Vad
1313 );
1314
1315 PSUBSECTION
1316 NTAPI
1317 MiLocateSubsection(
1318     IN PMMVAD Vad,
1319     IN ULONG_PTR Vpn
1320 );
1321
1322 //
1323 // MiRemoveZeroPage will use inline code to zero out the page manually if only
1324 // free pages are available. In some scenarios, we don't/can't run that piece of
1325 // code and would rather only have a real zero page. If we can't have a zero page,
1326 // then we'd like to have our own code to grab a free page and zero it out, by
1327 // using MiRemoveAnyPage. This macro implements this.
1328 //
1329 PFN_NUMBER
1330 FORCEINLINE
1331 MiRemoveZeroPageSafe(IN ULONG Color)
1332 {
1333     if (MmFreePagesByColor[ZeroedPageList][Color].Flink != LIST_HEAD) return MiRemoveZeroPage(Color);
1334     return 0;
1335 }
1336
1337 //
1338 // New ARM3<->RosMM PAGE Architecture
1339 //
1340 #define MI_GET_ROS_DATA(x)   ((PMMROSPFN)(x->RosMmData))
1341 #define MI_IS_ROS_PFN(x)     (((x)->u4.AweAllocation == TRUE) && (MI_GET_ROS_DATA(x) != NULL))
1342 #define ASSERT_IS_ROS_PFN(x) ASSERT(MI_IS_ROS_PFN(x) == TRUE);
1343 typedef struct _MMROSPFN
1344 {
1345     PMM_RMAP_ENTRY RmapListHead;
1346     SWAPENTRY SwapEntry;
1347 } MMROSPFN, *PMMROSPFN;
1348
1349 #define RosMmData            AweReferenceCount
1350
1351 /* EOF */