reactos/ntoskrnl/mm/ARM3/miarm.h

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/miarm.h
   5  * PURPOSE:         ARM Memory Manager Header
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 #ifndef _M_AMD64
  10
  11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
  13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
  14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128 * 1024 * 1024)
  15 #define MI_MAX_NONPAGED_POOL_SIZE              (128 * 1024 * 1024)
  16 #define MI_MAX_FREE_PAGE_LISTS                 4
  17
  18 #define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
  19
  20 #define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
  21 #define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
  22 #define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
  23 #define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
  24 #define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
  25                                                 MI_SESSION_POOL_SIZE + \
  26                                                 MI_SESSION_IMAGE_SIZE + \
  27                                                 MI_SESSION_WORKING_SET_SIZE)
  28
  29 #define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
  30
  31 #define MI_SYSTEM_CACHE_WS_START               (PVOID)0xC0C00000
  32 #define MI_PAGED_POOL_START                    (PVOID)0xE1000000
  33 #define MI_NONPAGED_POOL_END                   (PVOID)0xFFBE0000
  34 #define MI_DEBUG_MAPPING                       (PVOID)0xFFBFF000
  35
  36 #define MI_MIN_SECONDARY_COLORS                 8
  37 #define MI_SECONDARY_COLORS                     64
  38 #define MI_MAX_SECONDARY_COLORS                 1024
  39
  40 #define MM_HIGHEST_VAD_ADDRESS \
  41     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  42
  43 /* The range 0x10000->0x7FEFFFFF is reserved for the ROSMM MAREA Allocator */
  44 #define MI_LOWEST_VAD_ADDRESS                   (PVOID)0x7FF00000
  45
  46 #endif /* !_M_AMD64 */
  47
  48 /* Make the code cleaner with some definitions for size multiples */
  49 #define _1KB (1024)
  50 #define _1MB (1024 * _1KB)
  51
  52 /* Area mapped by a PDE */
  53 #define PDE_MAPPED_VA  (PTE_COUNT * PAGE_SIZE)
  54
  55 /* Size of a page table */
  56 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
  57
  58 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
  59 #ifdef _M_IX86
  60 #define PD_COUNT  1
  61 #define PDE_COUNT 1024
  62 #define PTE_COUNT 1024
  63 #elif _M_ARM
  64 #define PD_COUNT  1
  65 #define PDE_COUNT 4096
  66 #define PTE_COUNT 256
  67 #else
  68 #define PD_COUNT  PPE_PER_PAGE
  69 #define PDE_COUNT PDE_PER_PAGE
  70 #define PTE_COUNT PTE_PER_PAGE
  71 #endif
  72
  73 #ifdef _M_IX86
  74 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_I386
  75 #elif _M_ARM
  76 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_ARM
  77 #elif _M_AMD64
  78 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_AMD64
  79 #else
  80 #error Define these please!
  81 #endif
  82
  83 //
  84 // Protection Bits part of the internal memory manager Protection Mask
  85 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
  86 // and public assertions.
  87 //
  88 #define MM_ZERO_ACCESS         0
  89 #define MM_READONLY            1
  90 #define MM_EXECUTE             2
  91 #define MM_EXECUTE_READ        3
  92 #define MM_READWRITE           4
  93 #define MM_WRITECOPY           5
  94 #define MM_EXECUTE_READWRITE   6
  95 #define MM_EXECUTE_WRITECOPY   7
  96 #define MM_NOCACHE             8
  97 #define MM_DECOMMIT            0x10
  98 #define MM_NOACCESS            (MM_DECOMMIT | MM_NOCACHE)
  99
 100 //
 101 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
 102 // The Memory Manager's definition define the attributes that must be preserved
 103 // and these PTE definitions describe the attributes in the hardware sense. This
 104 // helps deal with hardware differences between the actual boolean expression of
 105 // the argument.
 106 //
 107 // For example, in the logical attributes, we want to express read-only as a flag
 108 // but on x86, it is writability that must be set. On the other hand, on x86, just
 109 // like in the kernel, it is disabling the caches that requires a special flag,
 110 // while on certain architectures such as ARM, it is enabling the cache which
 111 // requires a flag.
 112 //
 113 #if defined(_M_IX86) || defined(_M_AMD64)
 114 //
 115 // Access Flags
 116 //
 117 #define PTE_READONLY            0
 118 #define PTE_EXECUTE             0 // Not worrying about NX yet
 119 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 120 #define PTE_READWRITE           0x2
 121 #define PTE_WRITECOPY           0x200
 122 #define PTE_EXECUTE_READWRITE   0x0
 123 #define PTE_EXECUTE_WRITECOPY   0x200
 124 //
 125 // Cache flags
 126 //
 127 #define PTE_ENABLE_CACHE        0
 128 #define PTE_DISABLE_CACHE       0x10
 129 #define PTE_WRITECOMBINED_CACHE 0x10
 130 #elif defined(_M_ARM)
 131 #else
 132 #error Define these please!
 133 #endif
 134 static const
 135 ULONG
 136 MmProtectToPteMask[32] =
 137 {
 138     //
 139     // These are the base MM_ protection flags
 140     //
 141     0,
 142     PTE_READONLY            | PTE_ENABLE_CACHE,
 143     PTE_EXECUTE             | PTE_ENABLE_CACHE,
 144     PTE_EXECUTE_READ        | PTE_ENABLE_CACHE,
 145     PTE_READWRITE           | PTE_ENABLE_CACHE,
 146     PTE_WRITECOPY           | PTE_ENABLE_CACHE,
 147     PTE_EXECUTE_READWRITE   | PTE_ENABLE_CACHE,
 148     PTE_EXECUTE_WRITECOPY   | PTE_ENABLE_CACHE,
 149     //
 150     // These OR in the MM_NOCACHE flag
 151     //
 152     0,
 153     PTE_READONLY            | PTE_DISABLE_CACHE,
 154     PTE_EXECUTE             | PTE_DISABLE_CACHE,
 155     PTE_EXECUTE_READ        | PTE_DISABLE_CACHE,
 156     PTE_READWRITE           | PTE_DISABLE_CACHE,
 157     PTE_WRITECOPY           | PTE_DISABLE_CACHE,
 158     PTE_EXECUTE_READWRITE   | PTE_DISABLE_CACHE,
 159     PTE_EXECUTE_WRITECOPY   | PTE_DISABLE_CACHE,
 160     //
 161     // These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM
 162     //
 163     0,
 164     PTE_READONLY            | PTE_ENABLE_CACHE,
 165     PTE_EXECUTE             | PTE_ENABLE_CACHE,
 166     PTE_EXECUTE_READ        | PTE_ENABLE_CACHE,
 167     PTE_READWRITE           | PTE_ENABLE_CACHE,
 168     PTE_WRITECOPY           | PTE_ENABLE_CACHE,
 169     PTE_EXECUTE_READWRITE   | PTE_ENABLE_CACHE,
 170     PTE_EXECUTE_WRITECOPY   | PTE_ENABLE_CACHE,
 171     //
 172     // These OR in the MM_NOACCESS flag, which seems to enable WriteCombining?
 173     //
 174     0,
 175     PTE_READONLY            | PTE_WRITECOMBINED_CACHE,
 176     PTE_EXECUTE             | PTE_WRITECOMBINED_CACHE,
 177     PTE_EXECUTE_READ        | PTE_WRITECOMBINED_CACHE,
 178     PTE_READWRITE           | PTE_WRITECOMBINED_CACHE,
 179     PTE_WRITECOPY           | PTE_WRITECOMBINED_CACHE,
 180     PTE_EXECUTE_READWRITE   | PTE_WRITECOMBINED_CACHE,
 181     PTE_EXECUTE_WRITECOPY   | PTE_WRITECOMBINED_CACHE,
 182 };
 183
 184 //
 185 // Assertions for session images, addresses, and PTEs
 186 //
 187 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
 188     (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
 189
 190 #define MI_IS_SESSION_ADDRESS(Address) \
 191     (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
 192
 193 #define MI_IS_SESSION_PTE(Pte) \
 194     ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
 195
 196 #define MI_IS_PAGE_TABLE_ADDRESS(Address) \
 197     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)PTE_TOP))
 198
 199 #define MI_IS_SYSTEM_PAGE_TABLE_ADDRESS(Address) \
 200     (((Address) >= (PVOID)MiAddressToPte(MmSystemRangeStart)) && ((Address) <= (PVOID)PTE_TOP))
 201
 202 //
 203 // Corresponds to MMPTE_SOFTWARE.Protection
 204 //
 205 #ifdef _M_IX86
 206 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 207 #elif _M_ARM
 208 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 209 #elif _M_AMD64
 210 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 211 #else
 212 #error Define these please!
 213 #endif
 214
 215 //
 216 // Creates a software PTE with the given protection
 217 //
 218 #define MI_MAKE_SOFTWARE_PTE(p, x)          ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
 219
 220 //
 221 // Marks a PTE as deleted
 222 //
 223 #define MI_SET_PFN_DELETED(x)               ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
 224 #define MI_IS_PFN_DELETED(x)                ((ULONG_PTR)((x)->PteAddress) & 1)
 225
 226 //
 227 // Special values for LoadedImports
 228 //
 229 #define MM_SYSLDR_NO_IMPORTS   (PVOID)0xFFFFFFFE
 230 #define MM_SYSLDR_BOOT_LOADED  (PVOID)0xFFFFFFFF
 231 #define MM_SYSLDR_SINGLE_ENTRY 0x1
 232
 233 //
 234 // PFN List Sentinel
 235 //
 236 #define LIST_HEAD 0xFFFFFFFF
 237
 238 //
 239 // Special IRQL value (found in assertions)
 240 //
 241 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
 242
 243 //
 244 // FIXFIX: These should go in ex.h after the pool merge
 245 //
 246 #ifdef _M_AMD64
 247 #define POOL_BLOCK_SIZE 16
 248 #else
 249 #define POOL_BLOCK_SIZE  8
 250 #endif
 251 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
 252 #define BASE_POOL_TYPE_MASK 1
 253 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
 254
 255 typedef struct _POOL_DESCRIPTOR
 256 {
 257     POOL_TYPE PoolType;
 258     ULONG PoolIndex;
 259     ULONG RunningAllocs;
 260     ULONG RunningDeAllocs;
 261     ULONG TotalPages;
 262     ULONG TotalBigPages;
 263     ULONG Threshold;
 264     PVOID LockAddress;
 265     PVOID PendingFrees;
 266     LONG PendingFreeDepth;
 267     SIZE_T TotalBytes;
 268     SIZE_T Spare0;
 269     LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
 270 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 271
 272 typedef struct _POOL_HEADER
 273 {
 274     union
 275     {
 276         struct
 277         {
 278 #ifdef _M_AMD64
 279             ULONG PreviousSize:8;
 280             ULONG PoolIndex:8;
 281             ULONG BlockSize:8;
 282             ULONG PoolType:8;
 283 #else
 284             USHORT PreviousSize:9;
 285             USHORT PoolIndex:7;
 286             USHORT BlockSize:9;
 287             USHORT PoolType:7;
 288 #endif
 289         };
 290         ULONG Ulong1;
 291     };
 292 #ifdef _M_AMD64
 293     ULONG PoolTag;
 294 #endif
 295     union
 296     {
 297 #ifdef _M_AMD64
 298         PEPROCESS ProcessBilled;
 299 #else
 300         ULONG PoolTag;
 301 #endif
 302         struct
 303         {
 304             USHORT AllocatorBackTraceIndex;
 305             USHORT PoolTagHash;
 306         };
 307     };
 308 } POOL_HEADER, *PPOOL_HEADER;
 309
 310 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
 311 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
 312
 313 extern ULONG ExpNumberOfPagedPools;
 314 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
 315 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
 316 extern PVOID PoolTrackTable;
 317
 318 //
 319 // END FIXFIX
 320 //
 321
 322 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
 323 {
 324     LIST_ENTRY Links;
 325     UNICODE_STRING BaseName;
 326 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
 327
 328 typedef enum _MMSYSTEM_PTE_POOL_TYPE
 329 {
 330     SystemPteSpace,
 331     NonPagedPoolExpansion,
 332     MaximumPtePoolTypes
 333 } MMSYSTEM_PTE_POOL_TYPE;
 334
 335 typedef enum _MI_PFN_CACHE_ATTRIBUTE
 336 {
 337     MiNonCached,
 338     MiCached,
 339     MiWriteCombined,
 340     MiNotMapped
 341 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
 342
 343 typedef struct _PHYSICAL_MEMORY_RUN
 344 {
 345     ULONG BasePage;
 346     ULONG PageCount;
 347 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
 348
 349 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
 350 {
 351     ULONG NumberOfRuns;
 352     ULONG NumberOfPages;
 353     PHYSICAL_MEMORY_RUN Run[1];
 354 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
 355
 356 typedef struct _MMCOLOR_TABLES
 357 {
 358     PFN_NUMBER Flink;
 359     PVOID Blink;
 360     PFN_NUMBER Count;
 361 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 362
 363 typedef struct _MI_LARGE_PAGE_RANGES
 364 {
 365     PFN_NUMBER StartFrame;
 366     PFN_NUMBER LastFrame;
 367 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
 368
 369 extern MMPTE HyperTemplatePte;
 370 extern MMPDE ValidKernelPde;
 371 extern MMPTE ValidKernelPte;
 372 extern BOOLEAN MmLargeSystemCache;
 373 extern BOOLEAN MmZeroPageFile;
 374 extern BOOLEAN MmProtectFreedNonPagedPool;
 375 extern BOOLEAN MmTrackLockedPages;
 376 extern BOOLEAN MmTrackPtes;
 377 extern BOOLEAN MmDynamicPfn;
 378 extern BOOLEAN MmMirroring;
 379 extern BOOLEAN MmMakeLowMemory;
 380 extern BOOLEAN MmEnforceWriteProtection;
 381 extern ULONG MmAllocationFragment;
 382 extern ULONG MmConsumedPoolPercentage;
 383 extern ULONG MmVerifyDriverBufferType;
 384 extern ULONG MmVerifyDriverLevel;
 385 extern WCHAR MmVerifyDriverBuffer[512];
 386 extern WCHAR MmLargePageDriverBuffer[512];
 387 extern LIST_ENTRY MiLargePageDriverList;
 388 extern BOOLEAN MiLargePageAllDrivers;
 389 extern ULONG MmVerifyDriverBufferLength;
 390 extern ULONG MmLargePageDriverBufferLength;
 391 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
 392 extern SIZE_T MmMaximumNonPagedPoolInBytes;
 393 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
 394 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
 395 extern PVOID MmNonPagedSystemStart;
 396 extern PVOID MmNonPagedPoolStart;
 397 extern PVOID MmNonPagedPoolExpansionStart;
 398 extern PVOID MmNonPagedPoolEnd;
 399 extern SIZE_T MmSizeOfPagedPoolInBytes;
 400 extern PVOID MmPagedPoolStart;
 401 extern PVOID MmPagedPoolEnd;
 402 extern PVOID MmSessionBase;
 403 extern SIZE_T MmSessionSize;
 404 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
 405 extern PMMPTE MiFirstReservedZeroingPte;
 406 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
 407 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
 408 extern SIZE_T MmBootImageSize;
 409 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
 410 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
 411 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
 412 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
 413 extern ULONG_PTR MxPfnAllocation;
 414 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
 415 extern RTL_BITMAP MiPfnBitMap;
 416 extern KGUARDED_MUTEX MmPagedPoolMutex;
 417 extern PVOID MmPagedPoolStart;
 418 extern PVOID MmPagedPoolEnd;
 419 extern PVOID MmNonPagedSystemStart;
 420 extern PVOID MiSystemViewStart;
 421 extern SIZE_T MmSystemViewSize;
 422 extern PVOID MmSessionBase;
 423 extern PVOID MiSessionSpaceEnd;
 424 extern PMMPTE MiSessionImagePteStart;
 425 extern PMMPTE MiSessionImagePteEnd;
 426 extern PMMPTE MiSessionBasePte;
 427 extern PMMPTE MiSessionLastPte;
 428 extern SIZE_T MmSizeOfPagedPoolInBytes;
 429 extern PMMPTE MmSystemPagePtes;
 430 extern PVOID MmSystemCacheStart;
 431 extern PVOID MmSystemCacheEnd;
 432 extern MMSUPPORT MmSystemCacheWs;
 433 extern SIZE_T MmAllocatedNonPagedPool;
 434 extern ULONG_PTR MmSubsectionBase;
 435 extern ULONG MmSpecialPoolTag;
 436 extern PVOID MmHyperSpaceEnd;
 437 extern PMMWSL MmSystemCacheWorkingSetList;
 438 extern SIZE_T MmMinimumNonPagedPoolSize;
 439 extern ULONG MmMinAdditionNonPagedPoolPerMb;
 440 extern SIZE_T MmDefaultMaximumNonPagedPool;
 441 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
 442 extern ULONG MmSecondaryColors;
 443 extern ULONG MmSecondaryColorMask;
 444 extern ULONG_PTR MmNumberOfSystemPtes;
 445 extern ULONG MmMaximumNonPagedPoolPercent;
 446 extern ULONG MmLargeStackSize;
 447 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
 448 extern ULONG MmProductType;
 449 extern MM_SYSTEMSIZE MmSystemSize;
 450 extern PKEVENT MiLowMemoryEvent;
 451 extern PKEVENT MiHighMemoryEvent;
 452 extern PKEVENT MiLowPagedPoolEvent;
 453 extern PKEVENT MiHighPagedPoolEvent;
 454 extern PKEVENT MiLowNonPagedPoolEvent;
 455 extern PKEVENT MiHighNonPagedPoolEvent;
 456 extern PFN_NUMBER MmLowMemoryThreshold;
 457 extern PFN_NUMBER MmHighMemoryThreshold;
 458 extern PFN_NUMBER MiLowPagedPoolThreshold;
 459 extern PFN_NUMBER MiHighPagedPoolThreshold;
 460 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
 461 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
 462 extern PFN_NUMBER MmMinimumFreePages;
 463 extern PFN_NUMBER MmPlentyFreePages;
 464 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
 465 extern PFN_NUMBER MmResidentAvailablePages;
 466 extern PFN_NUMBER MmResidentAvailableAtInit;
 467 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
 468 extern PFN_NUMBER MmTotalSystemDriverPages;
 469 extern PVOID MiSessionImageStart;
 470 extern PVOID MiSessionImageEnd;
 471 extern PMMPTE MiHighestUserPte;
 472 extern PMMPDE MiHighestUserPde;
 473 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
 474
 475 #define MI_PFN_TO_PFNENTRY(x)     (&MmPfnDatabase[1][x])
 476 #define MI_PFNENTRY_TO_PFN(x)     (x - MmPfnDatabase[1])
 477
 478 //
 479 // Figures out the hardware bits for a PTE
 480 //
 481 ULONG
 482 FORCEINLINE
 483 MiDetermineUserGlobalPteMask(IN PMMPTE PointerPte)
 484 {
 485     MMPTE TempPte;
 486
 487     /* Start fresh */
 488     TempPte.u.Long = 0;
 489
 490     /* Make it valid and accessed */
 491     TempPte.u.Hard.Valid = TRUE;
 492     TempPte.u.Hard.Accessed = TRUE;
 493
 494     /* Is this for user-mode? */
 495     if ((PointerPte <= MiHighestUserPte) ||
 496         ((PointerPte >= MiAddressToPde(NULL)) && (PointerPte <= MiHighestUserPde)))
 497     {
 498         /* Set the owner bit */
 499         TempPte.u.Hard.Owner = TRUE;
 500     }
 501
 502     /* FIXME: We should also set the global bit */
 503
 504     /* Return the protection */
 505     return TempPte.u.Long;
 506 }
 507
 508 //
 509 // Creates a valid kernel PTE with the given protection
 510 //
 511 FORCEINLINE
 512 VOID
 513 MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte,
 514                             IN PMMPTE MappingPte,
 515                             IN ULONG ProtectionMask,
 516                             IN PFN_NUMBER PageFrameNumber)
 517 {
 518     /* Only valid for kernel, non-session PTEs */
 519     ASSERT(MappingPte > MiHighestUserPte);
 520     ASSERT(!MI_IS_SESSION_PTE(MappingPte));
 521     ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
 522
 523     /* Start fresh */
 524     *NewPte = ValidKernelPte;
 525
 526     /* Set the protection and page */
 527     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 528     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 529 }
 530
 531 //
 532 // Creates a valid PTE with the given protection
 533 //
 534 FORCEINLINE
 535 VOID
 536 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
 537                      IN PMMPTE MappingPte,
 538                      IN ULONG ProtectionMask,
 539                      IN PFN_NUMBER PageFrameNumber)
 540 {
 541     /* Set the protection and page */
 542     NewPte->u.Long = MiDetermineUserGlobalPteMask(MappingPte);
 543     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 544     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 545 }
 546
 547 //
 548 // Creates a valid user PTE with the given protection
 549 //
 550 FORCEINLINE
 551 VOID
 552 MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte,
 553                           IN PMMPTE MappingPte,
 554                           IN ULONG ProtectionMask,
 555                           IN PFN_NUMBER PageFrameNumber)
 556 {
 557     /* Only valid for kernel, non-session PTEs */
 558     ASSERT(MappingPte <= MiHighestUserPte);
 559
 560     /* Start fresh */
 561     *NewPte = ValidKernelPte;
 562
 563     /* Set the protection and page */
 564     NewPte->u.Hard.Owner = TRUE;
 565     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 566     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 567 }
 568
 569 //
 570 // Returns if the page is physically resident (ie: a large page)
 571 // FIXFIX: CISC/x86 only?
 572 //
 573 FORCEINLINE
 574 BOOLEAN
 575 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
 576 {
 577     PMMPDE PointerPde;
 578
 579     /* Large pages are never paged out, always physically resident */
 580     PointerPde = MiAddressToPde(Address);
 581     return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
 582 }
 583
 584 //
 585 // Writes a valid PTE
 586 //
 587 VOID
 588 FORCEINLINE
 589 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
 590                    IN MMPTE TempPte)
 591 {
 592     /* Write the valid PTE */
 593     ASSERT(PointerPte->u.Hard.Valid == 0);
 594     ASSERT(TempPte.u.Hard.Valid == 1);
 595     *PointerPte = TempPte;
 596 }
 597
 598 //
 599 // Writes an invalid PTE
 600 //
 601 VOID
 602 FORCEINLINE
 603 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
 604                      IN MMPTE InvalidPte)
 605 {
 606     /* Write the invalid PTE */
 607     ASSERT(InvalidPte.u.Hard.Valid == 0);
 608     *PointerPte = InvalidPte;
 609 }
 610
 611 NTSTATUS
 612 NTAPI
 613 MmArmInitSystem(
 614     IN ULONG Phase,
 615     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 616 );
 617
 618 NTSTATUS
 619 NTAPI
 620 MiInitMachineDependent(
 621     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 622 );
 623
 624 VOID
 625 NTAPI
 626 MiComputeColorInformation(
 627     VOID
 628 );
 629
 630 VOID
 631 NTAPI
 632 MiMapPfnDatabase(
 633     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 634 );
 635
 636 VOID
 637 NTAPI
 638 MiInitializeColorTables(
 639     VOID
 640 );
 641
 642 VOID
 643 NTAPI
 644 MiInitializePfnDatabase(
 645     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 646 );
 647
 648 BOOLEAN
 649 NTAPI
 650 MiInitializeMemoryEvents(
 651     VOID
 652 );
 653
 654 PFN_NUMBER
 655 NTAPI
 656 MxGetNextPage(
 657     IN PFN_NUMBER PageCount
 658 );
 659
 660 PPHYSICAL_MEMORY_DESCRIPTOR
 661 NTAPI
 662 MmInitializeMemoryLimits(
 663     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 664     IN PBOOLEAN IncludeType
 665 );
 666
 667 PFN_NUMBER
 668 NTAPI
 669 MiPagesInLoaderBlock(
 670     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 671     IN PBOOLEAN IncludeType
 672 );
 673
 674 VOID
 675 FASTCALL
 676 MiSyncARM3WithROS(
 677     IN PVOID AddressStart,
 678     IN PVOID AddressEnd
 679 );
 680
 681 NTSTATUS
 682 NTAPI
 683 MmArmAccessFault(
 684     IN BOOLEAN StoreInstruction,
 685     IN PVOID Address,
 686     IN KPROCESSOR_MODE Mode,
 687     IN PVOID TrapInformation
 688 );
 689
 690 NTSTATUS
 691 FASTCALL
 692 MiCheckPdeForPagedPool(
 693     IN PVOID Address
 694 );
 695
 696 VOID
 697 NTAPI
 698 MiInitializeNonPagedPool(
 699     VOID
 700 );
 701
 702 VOID
 703 NTAPI
 704 MiInitializeNonPagedPoolThresholds(
 705     VOID
 706 );
 707
 708 VOID
 709 NTAPI
 710 MiInitializePoolEvents(
 711     VOID
 712 );
 713
 714 VOID                      //
 715 NTAPI                     //
 716 InitializePool(           //
 717     IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
 718     IN ULONG Threshold    //
 719 );                        //
 720
 721 VOID
 722 NTAPI
 723 MiInitializeSystemPtes(
 724     IN PMMPTE StartingPte,
 725     IN ULONG NumberOfPtes,
 726     IN MMSYSTEM_PTE_POOL_TYPE PoolType
 727 );
 728
 729 PMMPTE
 730 NTAPI
 731 MiReserveSystemPtes(
 732     IN ULONG NumberOfPtes,
 733     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 734 );
 735
 736 VOID
 737 NTAPI
 738 MiReleaseSystemPtes(
 739     IN PMMPTE StartingPte,
 740     IN ULONG NumberOfPtes,
 741     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 742 );
 743
 744
 745 PFN_NUMBER
 746 NTAPI
 747 MiFindContiguousPages(
 748     IN PFN_NUMBER LowestPfn,
 749     IN PFN_NUMBER HighestPfn,
 750     IN PFN_NUMBER BoundaryPfn,
 751     IN PFN_NUMBER SizeInPages,
 752     IN MEMORY_CACHING_TYPE CacheType
 753 );
 754
 755 PVOID
 756 NTAPI
 757 MiCheckForContiguousMemory(
 758     IN PVOID BaseAddress,
 759     IN PFN_NUMBER BaseAddressPages,
 760     IN PFN_NUMBER SizeInPages,
 761     IN PFN_NUMBER LowestPfn,
 762     IN PFN_NUMBER HighestPfn,
 763     IN PFN_NUMBER BoundaryPfn,
 764     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
 765 );
 766
 767 PMDL
 768 NTAPI
 769 MiAllocatePagesForMdl(
 770     IN PHYSICAL_ADDRESS LowAddress,
 771     IN PHYSICAL_ADDRESS HighAddress,
 772     IN PHYSICAL_ADDRESS SkipBytes,
 773     IN SIZE_T TotalBytes,
 774     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
 775     IN ULONG Flags
 776 );
 777
 778 PVOID
 779 NTAPI
 780 MiMapLockedPagesInUserSpace(
 781     IN PMDL Mdl,
 782     IN PVOID BaseVa,
 783     IN MEMORY_CACHING_TYPE CacheType,
 784     IN PVOID BaseAddress
 785 );
 786
 787 VOID
 788 NTAPI
 789 MiUnmapLockedPagesInUserSpace(
 790     IN PVOID BaseAddress,
 791     IN PMDL Mdl
 792 );
 793
 794 VOID
 795 NTAPI
 796 MiInsertInListTail(
 797     IN PMMPFNLIST ListHead,
 798     IN PMMPFN Entry
 799 );
 800
 801 VOID
 802 NTAPI
 803 MiInsertZeroListAtBack(
 804     IN PFN_NUMBER PageIndex
 805 );
 806
 807 VOID
 808 NTAPI
 809 MiUnlinkFreeOrZeroedPage(
 810     IN PMMPFN Entry
 811 );
 812
 813 PMMPFN
 814 NTAPI
 815 MiRemoveHeadList(
 816     IN PMMPFNLIST ListHead
 817 );
 818
 819 PFN_NUMBER
 820 NTAPI
 821 MiAllocatePfn(
 822     IN PMMPTE PointerPte,
 823     IN ULONG Protection
 824 );
 825
 826 VOID
 827 NTAPI
 828 MiInitializePfn(
 829     IN PFN_NUMBER PageFrameIndex,
 830     IN PMMPTE PointerPte,
 831     IN BOOLEAN Modified
 832 );
 833
 834 VOID
 835 NTAPI
 836 MiInitializePfnForOtherProcess(
 837     IN PFN_NUMBER PageFrameIndex,
 838     IN PMMPTE PointerPte,
 839     IN PFN_NUMBER PteFrame
 840 );
 841
 842 VOID
 843 NTAPI
 844 MiDecrementShareCount(
 845     IN PMMPFN Pfn1,
 846     IN PFN_NUMBER PageFrameIndex
 847 );
 848
 849 PFN_NUMBER
 850 NTAPI
 851 MiRemoveAnyPage(
 852     IN ULONG Color
 853 );
 854
 855 PFN_NUMBER
 856 NTAPI
 857 MiRemoveZeroPage(
 858     IN ULONG Color
 859 );
 860
 861 VOID
 862 NTAPI
 863 MiInsertPageInFreeList(
 864     IN PFN_NUMBER PageFrameIndex
 865 );
 866
 867 PFN_NUMBER
 868 NTAPI
 869 MiDeleteSystemPageableVm(
 870     IN PMMPTE PointerPte,
 871     IN PFN_NUMBER PageCount,
 872     IN ULONG Flags,
 873     OUT PPFN_NUMBER ValidPages
 874 );
 875
 876 PLDR_DATA_TABLE_ENTRY
 877 NTAPI
 878 MiLookupDataTableEntry(
 879     IN PVOID Address
 880 );
 881
 882 VOID
 883 NTAPI
 884 MiInitializeDriverLargePageList(
 885     VOID
 886 );
 887
 888 VOID
 889 NTAPI
 890 MiInitializeLargePageSupport(
 891     VOID
 892 );
 893
 894 VOID
 895 NTAPI
 896 MiSyncCachedRanges(
 897     VOID
 898 );
 899
 900 BOOLEAN
 901 NTAPI
 902 MiIsPfnInUse(
 903     IN PMMPFN Pfn1
 904 );
 905
 906 PMMVAD
 907 NTAPI
 908 MiLocateAddress(
 909     IN PVOID VirtualAddress
 910 );
 911
 912 PMMADDRESS_NODE
 913 NTAPI
 914 MiCheckForConflictingNode(
 915     IN ULONG_PTR StartVpn,
 916     IN ULONG_PTR EndVpn,
 917     IN PMM_AVL_TABLE Table
 918 );
 919
 920 NTSTATUS
 921 NTAPI
 922 MiFindEmptyAddressRangeDownTree(
 923     IN SIZE_T Length,
 924     IN ULONG_PTR BoundaryAddress,
 925     IN ULONG_PTR Alignment,
 926     IN PMM_AVL_TABLE Table,
 927     OUT PULONG_PTR Base
 928 );
 929
 930 VOID
 931 NTAPI
 932 MiInsertNode(
 933     IN PMMADDRESS_NODE NewNode,
 934     IN PMM_AVL_TABLE Table
 935 );
 936
 937 /* EOF */