2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/mminit.c
5 * PURPOSE: ARM Memory Manager Initialization
6 * PROGRAMMERS: ReactOS Portable Systems Group
9 /* INCLUDES *******************************************************************/
16 #define MODULE_INVOLVED_IN_ARM3
19 /* GLOBALS ********************************************************************/
22 // These are all registry-configurable, but by default, the memory manager will
23 // figure out the most appropriate values.
25 ULONG MmMaximumNonPagedPoolPercent
;
26 SIZE_T MmSizeOfNonPagedPoolInBytes
;
27 SIZE_T MmMaximumNonPagedPoolInBytes
;
29 /* Some of the same values, in pages */
30 PFN_NUMBER MmMaximumNonPagedPoolInPages
;
33 // These numbers describe the discrete equation components of the nonpaged
34 // pool sizing algorithm.
36 // They are described on http://support.microsoft.com/default.aspx/kb/126402/ja
37 // along with the algorithm that uses them, which is implemented later below.
39 SIZE_T MmMinimumNonPagedPoolSize
= 256 * 1024;
40 ULONG MmMinAdditionNonPagedPoolPerMb
= 32 * 1024;
41 SIZE_T MmDefaultMaximumNonPagedPool
= 1024 * 1024;
42 ULONG MmMaxAdditionNonPagedPoolPerMb
= 400 * 1024;
45 // The memory layout (and especially variable names) of the NT kernel mode
46 // components can be a bit hard to twig, especially when it comes to the non
49 // There are really two components to the non-paged pool:
51 // - The initial nonpaged pool, sized dynamically up to a maximum.
52 // - The expansion nonpaged pool, sized dynamically up to a maximum.
54 // The initial nonpaged pool is physically continuous for performance, and
55 // immediately follows the PFN database, typically sharing the same PDE. It is
56 // a very small resource (32MB on a 1GB system), and capped at 128MB.
58 // Right now we call this the "ARM³ Nonpaged Pool" and it begins somewhere after
59 // the PFN database (which starts at 0xB0000000).
61 // The expansion nonpaged pool, on the other hand, can grow much bigger (400MB
62 // for a 1GB system). On ARM³ however, it is currently capped at 128MB.
64 // The address where the initial nonpaged pool starts is aptly named
65 // MmNonPagedPoolStart, and it describes a range of MmSizeOfNonPagedPoolInBytes
68 // Expansion nonpaged pool starts at an address described by the variable called
69 // MmNonPagedPoolExpansionStart, and it goes on for MmMaximumNonPagedPoolInBytes
70 // minus MmSizeOfNonPagedPoolInBytes bytes, always reaching MmNonPagedPoolEnd
71 // (because of the way it's calculated) at 0xFFBE0000.
73 // Initial nonpaged pool is allocated and mapped early-on during boot, but what
74 // about the expansion nonpaged pool? It is instead composed of special pages
75 // which belong to what are called System PTEs. These PTEs are the matter of a
76 // later discussion, but they are also considered part of the "nonpaged" OS, due
77 // to the fact that they are never paged out -- once an address is described by
78 // a System PTE, it is always valid, until the System PTE is torn down.
80 // System PTEs are actually composed of two "spaces", the system space proper,
81 // and the nonpaged pool expansion space. The latter, as we've already seen,
82 // begins at MmNonPagedPoolExpansionStart. Based on the number of System PTEs
83 // that the system will support, the remaining address space below this address
84 // is used to hold the system space PTEs. This address, in turn, is held in the
85 // variable named MmNonPagedSystemStart, which itself is never allowed to go
86 // below 0xEB000000 (thus creating an upper bound on the number of System PTEs).
88 // This means that 330MB are reserved for total nonpaged system VA, on top of
89 // whatever the initial nonpaged pool allocation is.
91 // The following URLs, valid as of April 23rd, 2008, support this evidence:
93 // http://www.cs.miami.edu/~burt/journal/NT/memory.html
94 // http://www.ditii.com/2007/09/28/windows-memory-management-x86-virtual-address-space/
96 PVOID MmNonPagedSystemStart
;
97 PVOID MmNonPagedPoolStart
;
98 PVOID MmNonPagedPoolExpansionStart
;
99 PVOID MmNonPagedPoolEnd
= MI_NONPAGED_POOL_END
;
102 // This is where paged pool starts by default
104 PVOID MmPagedPoolStart
= MI_PAGED_POOL_START
;
105 PVOID MmPagedPoolEnd
;
108 // And this is its default size
110 SIZE_T MmSizeOfPagedPoolInBytes
= MI_MIN_INIT_PAGED_POOLSIZE
;
111 PFN_NUMBER MmSizeOfPagedPoolInPages
= MI_MIN_INIT_PAGED_POOLSIZE
/ PAGE_SIZE
;
114 // Session space starts at 0xBFFFFFFF and grows downwards
115 // By default, it includes an 8MB image area where we map win32k and video card
116 // drivers, followed by a 4MB area containing the session's working set. This is
117 // then followed by a 20MB mapped view area and finally by the session's paged
118 // pool, by default 16MB.
120 // On a normal system, this results in session space occupying the region from
121 // 0xBD000000 to 0xC0000000
123 // See miarm.h for the defines that determine the sizing of this region. On an
124 // NT system, some of these can be configured through the registry, but we don't
127 PVOID MiSessionSpaceEnd
; // 0xC0000000
128 PVOID MiSessionImageEnd
; // 0xC0000000
129 PVOID MiSessionImageStart
; // 0xBF800000
130 PVOID MiSessionViewStart
; // 0xBE000000
131 PVOID MiSessionPoolEnd
; // 0xBE000000
132 PVOID MiSessionPoolStart
; // 0xBD000000
133 PVOID MmSessionBase
; // 0xBD000000
134 SIZE_T MmSessionSize
;
135 SIZE_T MmSessionViewSize
;
136 SIZE_T MmSessionPoolSize
;
137 SIZE_T MmSessionImageSize
;
140 * These are the PTE addresses of the boundaries carved out above
142 PMMPTE MiSessionImagePteStart
;
143 PMMPTE MiSessionImagePteEnd
;
144 PMMPTE MiSessionBasePte
;
145 PMMPTE MiSessionLastPte
;
148 // The system view space, on the other hand, is where sections that are memory
149 // mapped into "system space" end up.
151 // By default, it is a 16MB region.
153 PVOID MiSystemViewStart
;
154 SIZE_T MmSystemViewSize
;
157 // A copy of the system page directory (the page directory associated with the
158 // System process) is kept (double-mapped) by the manager in order to lazily
159 // map paged pool PDEs into external processes when they fault on a paged pool
162 PFN_NUMBER MmSystemPageDirectory
[PD_COUNT
];
163 PMMPTE MmSystemPagePtes
;
166 // The system cache starts right after hyperspace. The first few pages are for
167 // keeping track of the system working set list.
169 // This should be 0xC0C00000 -- the cache itself starts at 0xC1000000
171 PMMWSL MmSystemCacheWorkingSetList
= MI_SYSTEM_CACHE_WS_START
;
174 // Windows NT seems to choose between 7000, 11000 and 50000
175 // On systems with more than 32MB, this number is then doubled, and further
176 // aligned up to a PDE boundary (4MB).
178 ULONG_PTR MmNumberOfSystemPtes
;
181 // This is how many pages the PFN database will take up
182 // In Windows, this includes the Quark Color Table, but not in ARM³
184 PFN_NUMBER MxPfnAllocation
;
187 // Unlike the old ReactOS Memory Manager, ARM³ (and Windows) does not keep track
188 // of pages that are not actually valid physical memory, such as ACPI reserved
189 // regions, BIOS address ranges, or holes in physical memory address space which
190 // could indicate device-mapped I/O memory.
192 // In fact, the lack of a PFN entry for a page usually indicates that this is
193 // I/O space instead.
195 // A bitmap, called the PFN bitmap, keeps track of all page frames by assigning
196 // a bit to each. If the bit is set, then the page is valid physical RAM.
198 RTL_BITMAP MiPfnBitMap
;
201 // This structure describes the different pieces of RAM-backed address space
203 PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock
;
206 // This is where we keep track of the most basic physical layout markers
208 PFN_NUMBER MmNumberOfPhysicalPages
, MmHighestPhysicalPage
, MmLowestPhysicalPage
= -1;
211 // The total number of pages mapped by the boot loader, which include the kernel
212 // HAL, boot drivers, registry, NLS files and other loader data structures is
213 // kept track of here. This depends on "LoaderPagesSpanned" being correct when
214 // coming from the loader.
216 // This number is later aligned up to a PDE boundary.
218 SIZE_T MmBootImageSize
;
221 // These three variables keep track of the core separation of address space that
222 // exists between kernel mode and user mode.
224 ULONG_PTR MmUserProbeAddress
;
225 PVOID MmHighestUserAddress
;
226 PVOID MmSystemRangeStart
;
228 /* And these store the respective highest PTE/PDE address */
229 PMMPTE MiHighestUserPte
;
230 PMMPDE MiHighestUserPde
;
232 /* These variables define the system cache address space */
233 PVOID MmSystemCacheStart
;
234 PVOID MmSystemCacheEnd
;
235 MMSUPPORT MmSystemCacheWs
;
238 // This is where hyperspace ends (followed by the system cache working set)
240 PVOID MmHyperSpaceEnd
;
243 // Page coloring algorithm data
245 ULONG MmSecondaryColors
;
246 ULONG MmSecondaryColorMask
;
249 // Actual (registry-configurable) size of a GUI thread's stack
251 ULONG MmLargeStackSize
= KERNEL_LARGE_STACK_SIZE
;
254 // Before we have a PFN database, memory comes straight from our physical memory
255 // blocks, which is nice because it's guaranteed contiguous and also because once
256 // we take a page from here, the system doesn't see it anymore.
257 // However, once the fun is over, those pages must be re-integrated back into
258 // PFN society life, and that requires us keeping a copy of the original layout
259 // so that we can parse it later.
261 PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor
;
262 MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor
;
265 * For each page's worth bytes of L2 cache in a given set/way line, the zero and
266 * free lists are organized in what is called a "color".
268 * This array points to the two lists, so it can be thought of as a multi-dimensional
269 * array of MmFreePagesByColor[2][MmSecondaryColors]. Since the number is dynamic,
270 * we describe the array in pointer form instead.
272 * On a final note, the color tables themselves are right after the PFN database.
274 C_ASSERT(FreePageList
== 1);
275 PMMCOLOR_TABLES MmFreePagesByColor
[FreePageList
+ 1];
277 /* An event used in Phase 0 before the rest of the system is ready to go */
280 /* All the events used for memory threshold notifications */
281 PKEVENT MiLowMemoryEvent
;
282 PKEVENT MiHighMemoryEvent
;
283 PKEVENT MiLowPagedPoolEvent
;
284 PKEVENT MiHighPagedPoolEvent
;
285 PKEVENT MiLowNonPagedPoolEvent
;
286 PKEVENT MiHighNonPagedPoolEvent
;
288 /* The actual thresholds themselves, in page numbers */
289 PFN_NUMBER MmLowMemoryThreshold
;
290 PFN_NUMBER MmHighMemoryThreshold
;
291 PFN_NUMBER MiLowPagedPoolThreshold
;
292 PFN_NUMBER MiHighPagedPoolThreshold
;
293 PFN_NUMBER MiLowNonPagedPoolThreshold
;
294 PFN_NUMBER MiHighNonPagedPoolThreshold
;
297 * This number determines how many free pages must exist, at minimum, until we
298 * start trimming working sets and flushing modified pages to obtain more free
301 * This number changes if the system detects that this is a server product
303 PFN_NUMBER MmMinimumFreePages
= 26;
306 * This number indicates how many pages we consider to be a low limit of having
307 * "plenty" of free memory.
309 * It is doubled on systems that have more than 63MB of memory
311 PFN_NUMBER MmPlentyFreePages
= 400;
313 /* These values store the type of system this is (small, med, large) and if server */
315 MM_SYSTEMSIZE MmSystemSize
;
318 * These values store the cache working set minimums and maximums, in pages
320 * The minimum value is boosted on systems with more than 24MB of RAM, and cut
321 * down to only 32 pages on embedded (<24MB RAM) systems.
323 * An extra boost of 2MB is given on systems with more than 33MB of RAM.
325 PFN_NUMBER MmSystemCacheWsMinimum
= 288;
326 PFN_NUMBER MmSystemCacheWsMaximum
= 350;
328 /* FIXME: Move to cache/working set code later */
329 BOOLEAN MmLargeSystemCache
;
332 * This value determines in how many fragments/chunks the subsection prototype
333 * PTEs should be allocated when mapping a section object. It is configurable in
334 * the registry through the MapAllocationFragment parameter.
336 * The default is 64KB on systems with more than 1GB of RAM, 32KB on systems with
337 * more than 256MB of RAM, and 16KB on systems with less than 256MB of RAM.
339 * The maximum it can be set to is 2MB, and the minimum is 4KB.
341 SIZE_T MmAllocationFragment
;
344 * These two values track how much virtual memory can be committed, and when
345 * expansion should happen.
347 // FIXME: They should be moved elsewhere since it's not an "init" setting?
348 SIZE_T MmTotalCommitLimit
;
349 SIZE_T MmTotalCommitLimitMaximum
;
351 /* PRIVATE FUNCTIONS **********************************************************/
354 // In Bavaria, this is probably a hate crime
358 MiSyncARM3WithROS(IN PVOID AddressStart
,
362 // Puerile piece of junk-grade carbonized horseshit puss sold to the lowest bidder
364 ULONG Pde
= ADDR_TO_PDE_OFFSET(AddressStart
);
365 while (Pde
<= ADDR_TO_PDE_OFFSET(AddressEnd
))
368 // This both odious and heinous
370 extern ULONG MmGlobalKernelPageDirectory
[1024];
371 MmGlobalKernelPageDirectory
[Pde
] = ((PULONG
)PDE_BASE
)[Pde
];
378 MxGetNextPage(IN PFN_NUMBER PageCount
)
382 /* Make sure we have enough pages */
383 if (PageCount
> MxFreeDescriptor
->PageCount
)
385 /* Crash the system */
386 KeBugCheckEx(INSTALL_MORE_MEMORY
,
387 MmNumberOfPhysicalPages
,
388 MxFreeDescriptor
->PageCount
,
389 MxOldFreeDescriptor
.PageCount
,
393 /* Use our lowest usable free pages */
394 Pfn
= MxFreeDescriptor
->BasePage
;
395 MxFreeDescriptor
->BasePage
+= PageCount
;
396 MxFreeDescriptor
->PageCount
-= PageCount
;
402 MiComputeColorInformation(VOID
)
404 ULONG L2Associativity
;
406 /* Check if no setting was provided already */
407 if (!MmSecondaryColors
)
409 /* Get L2 cache information */
410 L2Associativity
= KeGetPcr()->SecondLevelCacheAssociativity
;
412 /* The number of colors is the number of cache bytes by set/way */
413 MmSecondaryColors
= KeGetPcr()->SecondLevelCacheSize
;
414 if (L2Associativity
) MmSecondaryColors
/= L2Associativity
;
417 /* Now convert cache bytes into pages */
418 MmSecondaryColors
>>= PAGE_SHIFT
;
419 if (!MmSecondaryColors
)
421 /* If there was no cache data from the KPCR, use the default colors */
422 MmSecondaryColors
= MI_SECONDARY_COLORS
;
426 /* Otherwise, make sure there aren't too many colors */
427 if (MmSecondaryColors
> MI_MAX_SECONDARY_COLORS
)
429 /* Set the maximum */
430 MmSecondaryColors
= MI_MAX_SECONDARY_COLORS
;
433 /* Make sure there aren't too little colors */
434 if (MmSecondaryColors
< MI_MIN_SECONDARY_COLORS
)
436 /* Set the default */
437 MmSecondaryColors
= MI_SECONDARY_COLORS
;
440 /* Finally make sure the colors are a power of two */
441 if (MmSecondaryColors
& (MmSecondaryColors
- 1))
443 /* Set the default */
444 MmSecondaryColors
= MI_SECONDARY_COLORS
;
448 /* Compute the mask and store it */
449 MmSecondaryColorMask
= MmSecondaryColors
- 1;
450 KeGetCurrentPrcb()->SecondaryColorMask
= MmSecondaryColorMask
;
455 MiInitializeColorTables(VOID
)
458 PMMPTE PointerPte
, LastPte
;
459 MMPTE TempPte
= ValidKernelPte
;
461 /* The color table starts after the ARM3 PFN database */
462 MmFreePagesByColor
[0] = (PMMCOLOR_TABLES
)&MmPfnDatabase
[MmHighestPhysicalPage
+ 1];
464 /* Loop the PTEs. We have two color tables for each secondary color */
465 PointerPte
= MiAddressToPte(&MmFreePagesByColor
[0][0]);
466 LastPte
= MiAddressToPte((ULONG_PTR
)MmFreePagesByColor
[0] +
467 (2 * MmSecondaryColors
* sizeof(MMCOLOR_TABLES
))
469 while (PointerPte
<= LastPte
)
471 /* Check for valid PTE */
472 if (PointerPte
->u
.Hard
.Valid
== 0)
474 /* Get a page and map it */
475 TempPte
.u
.Hard
.PageFrameNumber
= MxGetNextPage(1);
476 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
478 /* Zero out the page */
479 RtlZeroMemory(MiPteToAddress(PointerPte
), PAGE_SIZE
);
486 /* Now set the address of the next list, right after this one */
487 MmFreePagesByColor
[1] = &MmFreePagesByColor
[0][MmSecondaryColors
];
489 /* Now loop the lists to set them up */
490 for (i
= 0; i
< MmSecondaryColors
; i
++)
492 /* Set both free and zero lists for each color */
493 MmFreePagesByColor
[ZeroedPageList
][i
].Flink
= 0xFFFFFFFF;
494 MmFreePagesByColor
[ZeroedPageList
][i
].Blink
= (PVOID
)0xFFFFFFFF;
495 MmFreePagesByColor
[ZeroedPageList
][i
].Count
= 0;
496 MmFreePagesByColor
[FreePageList
][i
].Flink
= 0xFFFFFFFF;
497 MmFreePagesByColor
[FreePageList
][i
].Blink
= (PVOID
)0xFFFFFFFF;
498 MmFreePagesByColor
[FreePageList
][i
].Count
= 0;
504 MiIsRegularMemory(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
507 PLIST_ENTRY NextEntry
;
508 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
510 /* Loop the memory descriptors */
511 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
512 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
514 /* Get the memory descriptor */
515 MdBlock
= CONTAINING_RECORD(NextEntry
,
516 MEMORY_ALLOCATION_DESCRIPTOR
,
519 /* Check if this PFN could be part of the block */
520 if (Pfn
>= (MdBlock
->BasePage
))
522 /* Check if it really is part of the block */
523 if (Pfn
< (MdBlock
->BasePage
+ MdBlock
->PageCount
))
525 /* Check if the block is actually memory we don't map */
526 if ((MdBlock
->MemoryType
== LoaderFirmwarePermanent
) ||
527 (MdBlock
->MemoryType
== LoaderBBTMemory
) ||
528 (MdBlock
->MemoryType
== LoaderSpecialMemory
))
530 /* We don't need PFN database entries for this memory */
534 /* This is memory we want to map */
540 /* Blocks are ordered, so if it's not here, it doesn't exist */
544 /* Get to the next descriptor */
545 NextEntry
= MdBlock
->ListEntry
.Flink
;
548 /* Check if this PFN is actually from our free memory descriptor */
549 if ((Pfn
>= MxOldFreeDescriptor
.BasePage
) &&
550 (Pfn
< MxOldFreeDescriptor
.BasePage
+ MxOldFreeDescriptor
.PageCount
))
552 /* We use these pages for initial mappings, so we do want to count them */
556 /* Otherwise this isn't memory that we describe or care about */
562 MiMapPfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
564 ULONG FreePage
, FreePageCount
, PagesLeft
, BasePage
, PageCount
;
565 PLIST_ENTRY NextEntry
;
566 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
567 PMMPTE PointerPte
, LastPte
;
568 MMPTE TempPte
= ValidKernelPte
;
570 /* Get current page data, since we won't be using MxGetNextPage as it would corrupt our state */
571 FreePage
= MxFreeDescriptor
->BasePage
;
572 FreePageCount
= MxFreeDescriptor
->PageCount
;
575 /* Loop the memory descriptors */
576 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
577 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
579 /* Get the descriptor */
580 MdBlock
= CONTAINING_RECORD(NextEntry
,
581 MEMORY_ALLOCATION_DESCRIPTOR
,
583 if ((MdBlock
->MemoryType
== LoaderFirmwarePermanent
) ||
584 (MdBlock
->MemoryType
== LoaderBBTMemory
) ||
585 (MdBlock
->MemoryType
== LoaderSpecialMemory
))
587 /* These pages are not part of the PFN database */
588 NextEntry
= MdBlock
->ListEntry
.Flink
;
592 /* Next, check if this is our special free descriptor we've found */
593 if (MdBlock
== MxFreeDescriptor
)
595 /* Use the real numbers instead */
596 BasePage
= MxOldFreeDescriptor
.BasePage
;
597 PageCount
= MxOldFreeDescriptor
.PageCount
;
601 /* Use the descriptor's numbers */
602 BasePage
= MdBlock
->BasePage
;
603 PageCount
= MdBlock
->PageCount
;
606 /* Get the PTEs for this range */
607 PointerPte
= MiAddressToPte(&MmPfnDatabase
[BasePage
]);
608 LastPte
= MiAddressToPte(((ULONG_PTR
)&MmPfnDatabase
[BasePage
+ PageCount
]) - 1);
609 DPRINT("MD Type: %lx Base: %lx Count: %lx\n", MdBlock
->MemoryType
, BasePage
, PageCount
);
612 while (PointerPte
<= LastPte
)
614 /* We'll only touch PTEs that aren't already valid */
615 if (PointerPte
->u
.Hard
.Valid
== 0)
617 /* Use the next free page */
618 TempPte
.u
.Hard
.PageFrameNumber
= FreePage
;
619 ASSERT(FreePageCount
!= 0);
621 /* Consume free pages */
627 KeBugCheckEx(INSTALL_MORE_MEMORY
,
628 MmNumberOfPhysicalPages
,
630 MxOldFreeDescriptor
.PageCount
,
634 /* Write out this PTE */
636 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
639 RtlZeroMemory(MiPteToAddress(PointerPte
), PAGE_SIZE
);
646 /* Do the next address range */
647 NextEntry
= MdBlock
->ListEntry
.Flink
;
650 /* Now update the free descriptors to consume the pages we used up during the PFN allocation loop */
651 MxFreeDescriptor
->BasePage
= FreePage
;
652 MxFreeDescriptor
->PageCount
= FreePageCount
;
657 MiBuildPfnDatabaseFromPages(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
662 PFN_NUMBER PageFrameIndex
, StartupPdIndex
, PtePageIndex
;
664 ULONG_PTR BaseAddress
= 0;
666 /* PFN of the startup page directory */
667 StartupPdIndex
= PFN_FROM_PTE(MiAddressToPde(PDE_BASE
));
669 /* Start with the first PDE and scan them all */
670 PointerPde
= MiAddressToPde(NULL
);
671 Count
= PD_COUNT
* PDE_COUNT
;
672 for (i
= 0; i
< Count
; i
++)
674 /* Check for valid PDE */
675 if (PointerPde
->u
.Hard
.Valid
== 1)
677 /* Get the PFN from it */
678 PageFrameIndex
= PFN_FROM_PTE(PointerPde
);
680 /* Do we want a PFN entry for this page? */
681 if (MiIsRegularMemory(LoaderBlock
, PageFrameIndex
))
683 /* Yes we do, set it up */
684 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
685 Pfn1
->u4
.PteFrame
= StartupPdIndex
;
686 Pfn1
->PteAddress
= PointerPde
;
687 Pfn1
->u2
.ShareCount
++;
688 Pfn1
->u3
.e2
.ReferenceCount
= 1;
689 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
690 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
698 /* Now get the PTE and scan the pages */
699 PointerPte
= MiAddressToPte(BaseAddress
);
700 for (j
= 0; j
< PTE_COUNT
; j
++)
702 /* Check for a valid PTE */
703 if (PointerPte
->u
.Hard
.Valid
== 1)
705 /* Increase the shared count of the PFN entry for the PDE */
706 ASSERT(Pfn1
!= NULL
);
707 Pfn1
->u2
.ShareCount
++;
709 /* Now check if the PTE is valid memory too */
710 PtePageIndex
= PFN_FROM_PTE(PointerPte
);
711 if (MiIsRegularMemory(LoaderBlock
, PtePageIndex
))
714 * Only add pages above the end of system code or pages
715 * that are part of nonpaged pool
717 if ((BaseAddress
>= 0xA0000000) ||
718 ((BaseAddress
>= (ULONG_PTR
)MmNonPagedPoolStart
) &&
719 (BaseAddress
< (ULONG_PTR
)MmNonPagedPoolStart
+
720 MmSizeOfNonPagedPoolInBytes
)))
722 /* Get the PFN entry and make sure it too is valid */
723 Pfn2
= MiGetPfnEntry(PtePageIndex
);
724 if ((MmIsAddressValid(Pfn2
)) &&
725 (MmIsAddressValid(Pfn2
+ 1)))
727 /* Setup the PFN entry */
728 Pfn2
->u4
.PteFrame
= PageFrameIndex
;
729 Pfn2
->PteAddress
= PointerPte
;
730 Pfn2
->u2
.ShareCount
++;
731 Pfn2
->u3
.e2
.ReferenceCount
= 1;
732 Pfn2
->u3
.e1
.PageLocation
= ActiveAndValid
;
733 Pfn2
->u3
.e1
.CacheAttribute
= MiNonCached
;
741 BaseAddress
+= PAGE_SIZE
;
746 /* Next PDE mapped address */
747 BaseAddress
+= PDE_MAPPED_VA
;
757 MiBuildPfnDatabaseZeroPage(VOID
)
762 /* Grab the lowest page and check if it has no real references */
763 Pfn1
= MiGetPfnEntry(MmLowestPhysicalPage
);
764 if (!(MmLowestPhysicalPage
) && !(Pfn1
->u3
.e2
.ReferenceCount
))
766 /* Make it a bogus page to catch errors */
767 PointerPde
= MiAddressToPde(0xFFFFFFFF);
768 Pfn1
->u4
.PteFrame
= PFN_FROM_PTE(PointerPde
);
769 Pfn1
->PteAddress
= PointerPde
;
770 Pfn1
->u2
.ShareCount
++;
771 Pfn1
->u3
.e2
.ReferenceCount
= 0xFFF0;
772 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
773 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
779 MiBuildPfnDatabaseFromLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
781 PLIST_ENTRY NextEntry
;
782 PFN_NUMBER PageCount
= 0;
783 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
784 PFN_NUMBER PageFrameIndex
;
790 /* Now loop through the descriptors */
791 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
792 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
794 /* Get the current descriptor */
795 MdBlock
= CONTAINING_RECORD(NextEntry
,
796 MEMORY_ALLOCATION_DESCRIPTOR
,
800 PageCount
= MdBlock
->PageCount
;
801 PageFrameIndex
= MdBlock
->BasePage
;
803 /* Don't allow memory above what the PFN database is mapping */
804 if (PageFrameIndex
> MmHighestPhysicalPage
)
806 /* Since they are ordered, everything past here will be larger */
810 /* On the other hand, the end page might be higher up... */
811 if ((PageFrameIndex
+ PageCount
) > (MmHighestPhysicalPage
+ 1))
813 /* In which case we'll trim the descriptor to go as high as we can */
814 PageCount
= MmHighestPhysicalPage
+ 1 - PageFrameIndex
;
815 MdBlock
->PageCount
= PageCount
;
817 /* But if there's nothing left to trim, we got too high, so quit */
818 if (!PageCount
) break;
821 /* Now check the descriptor type */
822 switch (MdBlock
->MemoryType
)
824 /* Check for bad RAM */
827 DPRINT1("You have damaged RAM modules. Stopping boot\n");
831 /* Check for free RAM */
833 case LoaderLoadedProgram
:
834 case LoaderFirmwareTemporary
:
835 case LoaderOsloaderStack
:
837 /* Get the last page of this descriptor. Note we loop backwards */
838 PageFrameIndex
+= PageCount
- 1;
839 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
841 /* Lock the PFN Database */
842 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
845 /* If the page really has no references, mark it as free */
846 if (!Pfn1
->u3
.e2
.ReferenceCount
)
848 /* Add it to the free list */
849 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
850 MiInsertPageInFreeList(PageFrameIndex
);
853 /* Go to the next page */
858 /* Release PFN database */
859 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
861 /* Done with this block */
864 /* Check for pages that are invisible to us */
865 case LoaderFirmwarePermanent
:
866 case LoaderSpecialMemory
:
867 case LoaderBBTMemory
:
874 /* Map these pages with the KSEG0 mapping that adds 0x80000000 */
875 PointerPte
= MiAddressToPte(KSEG0_BASE
+ (PageFrameIndex
<< PAGE_SHIFT
));
876 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
879 /* Check if the page is really unused */
880 PointerPde
= MiAddressToPde(KSEG0_BASE
+ (PageFrameIndex
<< PAGE_SHIFT
));
881 if (!Pfn1
->u3
.e2
.ReferenceCount
)
883 /* Mark it as being in-use */
884 Pfn1
->u4
.PteFrame
= PFN_FROM_PTE(PointerPde
);
885 Pfn1
->PteAddress
= PointerPte
;
886 Pfn1
->u2
.ShareCount
++;
887 Pfn1
->u3
.e2
.ReferenceCount
= 1;
888 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
889 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
891 /* Check for RAM disk page */
892 if (MdBlock
->MemoryType
== LoaderXIPRom
)
894 /* Make it a pseudo-I/O ROM mapping */
896 Pfn1
->u2
.ShareCount
= 0;
897 Pfn1
->u3
.e2
.ReferenceCount
= 0;
898 Pfn1
->u3
.e1
.PageLocation
= 0;
900 Pfn1
->u4
.InPageError
= 0;
901 Pfn1
->u3
.e1
.PrototypePte
= 1;
905 /* Advance page structures */
913 /* Next descriptor entry */
914 NextEntry
= MdBlock
->ListEntry
.Flink
;
920 MiBuildPfnDatabaseSelf(VOID
)
922 PMMPTE PointerPte
, LastPte
;
925 /* Loop the PFN database page */
926 PointerPte
= MiAddressToPte(MiGetPfnEntry(MmLowestPhysicalPage
));
927 LastPte
= MiAddressToPte(MiGetPfnEntry(MmHighestPhysicalPage
));
928 while (PointerPte
<= LastPte
)
930 /* Make sure the page is valid */
931 if (PointerPte
->u
.Hard
.Valid
== 1)
933 /* Get the PFN entry and just mark it referenced */
934 Pfn1
= MiGetPfnEntry(PointerPte
->u
.Hard
.PageFrameNumber
);
935 Pfn1
->u2
.ShareCount
= 1;
936 Pfn1
->u3
.e2
.ReferenceCount
= 1;
946 MiInitializePfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
948 /* Scan memory and start setting up PFN entries */
949 MiBuildPfnDatabaseFromPages(LoaderBlock
);
951 /* Add the zero page */
952 MiBuildPfnDatabaseZeroPage();
954 /* Scan the loader block and build the rest of the PFN database */
955 MiBuildPfnDatabaseFromLoaderBlock(LoaderBlock
);
957 /* Finally add the pages for the PFN database itself */
958 MiBuildPfnDatabaseSelf();
963 MiAdjustWorkingSetManagerParameters(IN BOOLEAN Client
)
965 /* This function needs to do more work, for now, we tune page minimums */
967 /* Check for a system with around 64MB RAM or more */
968 if (MmNumberOfPhysicalPages
>= (63 * _1MB
) / PAGE_SIZE
)
970 /* Double the minimum amount of pages we consider for a "plenty free" scenario */
971 MmPlentyFreePages
*= 2;
977 MiNotifyMemoryEvents(VOID
)
979 /* Are we in a low-memory situation? */
980 if (MmAvailablePages
< MmLowMemoryThreshold
)
982 /* Clear high, set low */
983 if (KeReadStateEvent(MiHighMemoryEvent
)) KeClearEvent(MiHighMemoryEvent
);
984 if (!KeReadStateEvent(MiLowMemoryEvent
)) KeSetEvent(MiLowMemoryEvent
, 0, FALSE
);
986 else if (MmAvailablePages
< MmHighMemoryThreshold
)
988 /* We are in between, clear both */
989 if (KeReadStateEvent(MiHighMemoryEvent
)) KeClearEvent(MiHighMemoryEvent
);
990 if (KeReadStateEvent(MiLowMemoryEvent
)) KeClearEvent(MiLowMemoryEvent
);
994 /* Clear low, set high */
995 if (KeReadStateEvent(MiLowMemoryEvent
)) KeClearEvent(MiLowMemoryEvent
);
996 if (!KeReadStateEvent(MiHighMemoryEvent
)) KeSetEvent(MiHighMemoryEvent
, 0, FALSE
);
1002 MiCreateMemoryEvent(IN PUNICODE_STRING Name
,
1009 OBJECT_ATTRIBUTES ObjectAttributes
;
1010 SECURITY_DESCRIPTOR SecurityDescriptor
;
1013 Status
= RtlCreateSecurityDescriptor(&SecurityDescriptor
,
1014 SECURITY_DESCRIPTOR_REVISION
);
1015 if (!NT_SUCCESS(Status
)) return Status
;
1017 /* One ACL with 3 ACEs, containing each one SID */
1018 DaclLength
= sizeof(ACL
) +
1019 3 * sizeof(ACCESS_ALLOWED_ACE
) +
1020 RtlLengthSid(SeLocalSystemSid
) +
1021 RtlLengthSid(SeAliasAdminsSid
) +
1022 RtlLengthSid(SeWorldSid
);
1024 /* Allocate space for the DACL */
1025 Dacl
= ExAllocatePoolWithTag(PagedPool
, DaclLength
, 'lcaD');
1026 if (!Dacl
) return STATUS_INSUFFICIENT_RESOURCES
;
1028 /* Setup the ACL inside it */
1029 Status
= RtlCreateAcl(Dacl
, DaclLength
, ACL_REVISION
);
1030 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1032 /* Add query rights for everyone */
1033 Status
= RtlAddAccessAllowedAce(Dacl
,
1035 SYNCHRONIZE
| EVENT_QUERY_STATE
| READ_CONTROL
,
1037 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1039 /* Full rights for the admin */
1040 Status
= RtlAddAccessAllowedAce(Dacl
,
1044 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1046 /* As well as full rights for the system */
1047 Status
= RtlAddAccessAllowedAce(Dacl
,
1051 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1053 /* Set this DACL inside the SD */
1054 Status
= RtlSetDaclSecurityDescriptor(&SecurityDescriptor
,
1058 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1060 /* Setup the event attributes, making sure it's a permanent one */
1061 InitializeObjectAttributes(&ObjectAttributes
,
1063 OBJ_KERNEL_HANDLE
| OBJ_PERMANENT
,
1065 &SecurityDescriptor
);
1067 /* Create the event */
1068 Status
= ZwCreateEvent(&EventHandle
,
1077 /* Check if this is the success path */
1078 if (NT_SUCCESS(Status
))
1080 /* Add a reference to the object, then close the handle we had */
1081 Status
= ObReferenceObjectByHandle(EventHandle
,
1087 ZwClose (EventHandle
);
1096 MiInitializeMemoryEvents(VOID
)
1098 UNICODE_STRING LowString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowMemoryCondition");
1099 UNICODE_STRING HighString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighMemoryCondition");
1100 UNICODE_STRING LowPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowPagedPoolCondition");
1101 UNICODE_STRING HighPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighPagedPoolCondition");
1102 UNICODE_STRING LowNonPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowNonPagedPoolCondition");
1103 UNICODE_STRING HighNonPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighNonPagedPoolCondition");
1106 /* Check if we have a registry setting */
1107 if (MmLowMemoryThreshold
)
1109 /* Convert it to pages */
1110 MmLowMemoryThreshold
*= (_1MB
/ PAGE_SIZE
);
1114 /* The low memory threshold is hit when we don't consider that we have "plenty" of free pages anymore */
1115 MmLowMemoryThreshold
= MmPlentyFreePages
;
1117 /* More than one GB of memory? */
1118 if (MmNumberOfPhysicalPages
> 0x40000)
1120 /* Start at 32MB, and add another 16MB for each GB */
1121 MmLowMemoryThreshold
= (32 * _1MB
) / PAGE_SIZE
;
1122 MmLowMemoryThreshold
+= ((MmNumberOfPhysicalPages
- 0x40000) >> 7);
1124 else if (MmNumberOfPhysicalPages
> 0x8000)
1126 /* For systems with > 128MB RAM, add another 4MB for each 128MB */
1127 MmLowMemoryThreshold
+= ((MmNumberOfPhysicalPages
- 0x8000) >> 5);
1130 /* Don't let the minimum threshold go past 64MB */
1131 MmLowMemoryThreshold
= min(MmLowMemoryThreshold
, (64 * _1MB
) / PAGE_SIZE
);
1134 /* Check if we have a registry setting */
1135 if (MmHighMemoryThreshold
)
1137 /* Convert it into pages */
1138 MmHighMemoryThreshold
*= (_1MB
/ PAGE_SIZE
);
1142 /* Otherwise, the default is three times the low memory threshold */
1143 MmHighMemoryThreshold
= 3 * MmLowMemoryThreshold
;
1144 ASSERT(MmHighMemoryThreshold
> MmLowMemoryThreshold
);
1147 /* Make sure high threshold is actually higher than the low */
1148 MmHighMemoryThreshold
= max(MmHighMemoryThreshold
, MmLowMemoryThreshold
);
1150 /* Create the memory events for all the thresholds */
1151 Status
= MiCreateMemoryEvent(&LowString
, &MiLowMemoryEvent
);
1152 if (!NT_SUCCESS(Status
)) return FALSE
;
1153 Status
= MiCreateMemoryEvent(&HighString
, &MiHighMemoryEvent
);
1154 if (!NT_SUCCESS(Status
)) return FALSE
;
1155 Status
= MiCreateMemoryEvent(&LowPagedPoolString
, &MiLowPagedPoolEvent
);
1156 if (!NT_SUCCESS(Status
)) return FALSE
;
1157 Status
= MiCreateMemoryEvent(&HighPagedPoolString
, &MiHighPagedPoolEvent
);
1158 if (!NT_SUCCESS(Status
)) return FALSE
;
1159 Status
= MiCreateMemoryEvent(&LowNonPagedPoolString
, &MiLowNonPagedPoolEvent
);
1160 if (!NT_SUCCESS(Status
)) return FALSE
;
1161 Status
= MiCreateMemoryEvent(&HighNonPagedPoolString
, &MiHighNonPagedPoolEvent
);
1162 if (!NT_SUCCESS(Status
)) return FALSE
;
1164 /* Now setup the pool events */
1165 MiInitializePoolEvents();
1167 /* Set the initial event state */
1168 MiNotifyMemoryEvents();
1174 MiAddHalIoMappings(VOID
)
1179 ULONG i
, j
, PdeCount
;
1180 PFN_NUMBER PageFrameIndex
;
1182 /* HAL Heap address -- should be on a PDE boundary */
1183 BaseAddress
= (PVOID
)0xFFC00000;
1184 ASSERT(MiAddressToPteOffset(BaseAddress
) == 0);
1186 /* Check how many PDEs the heap has */
1187 PointerPde
= MiAddressToPde(BaseAddress
);
1188 PdeCount
= PDE_COUNT
- ADDR_TO_PDE_OFFSET(BaseAddress
);
1189 for (i
= 0; i
< PdeCount
; i
++)
1191 /* Does the HAL own this mapping? */
1192 if ((PointerPde
->u
.Hard
.Valid
== 1) &&
1193 (PointerPde
->u
.Hard
.LargePage
== 0))
1195 /* Get the PTE for it and scan each page */
1196 PointerPte
= MiAddressToPte(BaseAddress
);
1197 for (j
= 0 ; j
< PTE_COUNT
; j
++)
1199 /* Does the HAL own this page? */
1200 if (PointerPte
->u
.Hard
.Valid
== 1)
1202 /* Is the HAL using it for device or I/O mapped memory? */
1203 PageFrameIndex
= PFN_FROM_PTE(PointerPte
);
1204 if (!MiGetPfnEntry(PageFrameIndex
))
1206 /* FIXME: For PAT, we need to track I/O cache attributes for coherency */
1207 DPRINT1("HAL I/O Mapping at %p is unsafe\n", BaseAddress
);
1211 /* Move to the next page */
1212 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+ PAGE_SIZE
);
1218 /* Move to the next address */
1219 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+ PDE_MAPPED_VA
);
1222 /* Move to the next PDE */
1229 MmDumpArmPfnDatabase(VOID
)
1233 PCHAR Consumer
= "Unknown";
1235 ULONG ActivePages
= 0, FreePages
= 0, OtherPages
= 0;
1237 KeRaiseIrql(HIGH_LEVEL
, &OldIrql
);
1240 // Loop the PFN database
1242 for (i
= 0; i
<= MmHighestPhysicalPage
; i
++)
1244 Pfn1
= MiGetPfnEntry(i
);
1245 if (!Pfn1
) continue;
1248 // Get the page location
1250 switch (Pfn1
->u3
.e1
.PageLocation
)
1252 case ActiveAndValid
:
1254 Consumer
= "Active and Valid";
1260 Consumer
= "Free Page List";
1266 Consumer
= "Other (ASSERT!)";
1272 // Pretty-print the page
1274 DbgPrint("0x%08p:\t%20s\t(%02d.%02d) [%08p-%08p])\n",
1277 Pfn1
->u3
.e2
.ReferenceCount
,
1278 Pfn1
->u2
.ShareCount
,
1283 DbgPrint("Active: %d pages\t[%d KB]\n", ActivePages
, (ActivePages
<< PAGE_SHIFT
) / 1024);
1284 DbgPrint("Free: %d pages\t[%d KB]\n", FreePages
, (FreePages
<< PAGE_SHIFT
) / 1024);
1285 DbgPrint("Other: %d pages\t[%d KB]\n", OtherPages
, (OtherPages
<< PAGE_SHIFT
) / 1024);
1287 KeLowerIrql(OldIrql
);
1292 MiPagesInLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
1293 IN PBOOLEAN IncludeType
)
1295 PLIST_ENTRY NextEntry
;
1296 PFN_NUMBER PageCount
= 0;
1297 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
1300 // Now loop through the descriptors
1302 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1303 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1306 // Grab each one, and check if it's one we should include
1308 MdBlock
= CONTAINING_RECORD(NextEntry
,
1309 MEMORY_ALLOCATION_DESCRIPTOR
,
1311 if ((MdBlock
->MemoryType
< LoaderMaximum
) &&
1312 (IncludeType
[MdBlock
->MemoryType
]))
1315 // Add this to our running total
1317 PageCount
+= MdBlock
->PageCount
;
1321 // Try the next descriptor
1323 NextEntry
= MdBlock
->ListEntry
.Flink
;
1332 PPHYSICAL_MEMORY_DESCRIPTOR
1334 MmInitializeMemoryLimits(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
1335 IN PBOOLEAN IncludeType
)
1337 PLIST_ENTRY NextEntry
;
1338 ULONG Run
= 0, InitialRuns
= 0;
1339 PFN_NUMBER NextPage
= -1, PageCount
= 0;
1340 PPHYSICAL_MEMORY_DESCRIPTOR Buffer
, NewBuffer
;
1341 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
1344 // Scan the memory descriptors
1346 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1347 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1350 // For each one, increase the memory allocation estimate
1353 NextEntry
= NextEntry
->Flink
;
1357 // Allocate the maximum we'll ever need
1359 Buffer
= ExAllocatePoolWithTag(NonPagedPool
,
1360 sizeof(PHYSICAL_MEMORY_DESCRIPTOR
) +
1361 sizeof(PHYSICAL_MEMORY_RUN
) *
1364 if (!Buffer
) return NULL
;
1367 // For now that's how many runs we have
1369 Buffer
->NumberOfRuns
= InitialRuns
;
1372 // Now loop through the descriptors again
1374 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1375 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1378 // Grab each one, and check if it's one we should include
1380 MdBlock
= CONTAINING_RECORD(NextEntry
,
1381 MEMORY_ALLOCATION_DESCRIPTOR
,
1383 if ((MdBlock
->MemoryType
< LoaderMaximum
) &&
1384 (IncludeType
[MdBlock
->MemoryType
]))
1387 // Add this to our running total
1389 PageCount
+= MdBlock
->PageCount
;
1392 // Check if the next page is described by the next descriptor
1394 if (MdBlock
->BasePage
== NextPage
)
1397 // Combine it into the same physical run
1399 ASSERT(MdBlock
->PageCount
!= 0);
1400 Buffer
->Run
[Run
- 1].PageCount
+= MdBlock
->PageCount
;
1401 NextPage
+= MdBlock
->PageCount
;
1406 // Otherwise just duplicate the descriptor's contents
1408 Buffer
->Run
[Run
].BasePage
= MdBlock
->BasePage
;
1409 Buffer
->Run
[Run
].PageCount
= MdBlock
->PageCount
;
1410 NextPage
= Buffer
->Run
[Run
].BasePage
+ Buffer
->Run
[Run
].PageCount
;
1413 // And in this case, increase the number of runs
1420 // Try the next descriptor
1422 NextEntry
= MdBlock
->ListEntry
.Flink
;
1426 // We should not have been able to go past our initial estimate
1428 ASSERT(Run
<= Buffer
->NumberOfRuns
);
1431 // Our guess was probably exaggerated...
1433 if (InitialRuns
> Run
)
1436 // Allocate a more accurately sized buffer
1438 NewBuffer
= ExAllocatePoolWithTag(NonPagedPool
,
1439 sizeof(PHYSICAL_MEMORY_DESCRIPTOR
) +
1440 sizeof(PHYSICAL_MEMORY_RUN
) *
1446 // Copy the old buffer into the new, then free it
1448 RtlCopyMemory(NewBuffer
->Run
,
1450 sizeof(PHYSICAL_MEMORY_RUN
) * Run
);
1454 // Now use the new buffer
1461 // Write the final numbers, and return it
1463 Buffer
->NumberOfRuns
= Run
;
1464 Buffer
->NumberOfPages
= PageCount
;
1470 MiBuildPagedPool(VOID
)
1472 PMMPTE PointerPte
, PointerPde
;
1473 MMPTE TempPte
= ValidKernelPte
;
1474 PFN_NUMBER PageFrameIndex
;
1476 ULONG Size
, BitMapSize
;
1479 // Get the page frame number for the system page directory
1481 PointerPte
= MiAddressToPte(PDE_BASE
);
1482 ASSERT(PD_COUNT
== 1);
1483 MmSystemPageDirectory
[0] = PFN_FROM_PTE(PointerPte
);
1486 // Allocate a system PTE which will hold a copy of the page directory
1488 PointerPte
= MiReserveSystemPtes(1, SystemPteSpace
);
1490 MmSystemPagePtes
= MiPteToAddress(PointerPte
);
1493 // Make this system PTE point to the system page directory.
1494 // It is now essentially double-mapped. This will be used later for lazy
1495 // evaluation of PDEs accross process switches, similarly to how the Global
1496 // page directory array in the old ReactOS Mm is used (but in a less hacky
1499 TempPte
= ValidKernelPte
;
1500 ASSERT(PD_COUNT
== 1);
1501 TempPte
.u
.Hard
.PageFrameNumber
= MmSystemPageDirectory
[0];
1502 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
1505 // Let's get back to paged pool work: size it up.
1506 // By default, it should be twice as big as nonpaged pool.
1508 MmSizeOfPagedPoolInBytes
= 2 * MmMaximumNonPagedPoolInBytes
;
1509 if (MmSizeOfPagedPoolInBytes
> ((ULONG_PTR
)MmNonPagedSystemStart
-
1510 (ULONG_PTR
)MmPagedPoolStart
))
1513 // On the other hand, we have limited VA space, so make sure that the VA
1514 // for paged pool doesn't overflow into nonpaged pool VA. Otherwise, set
1515 // whatever maximum is possible.
1517 MmSizeOfPagedPoolInBytes
= (ULONG_PTR
)MmNonPagedSystemStart
-
1518 (ULONG_PTR
)MmPagedPoolStart
;
1522 // Get the size in pages and make sure paged pool is at least 32MB.
1524 Size
= MmSizeOfPagedPoolInBytes
;
1525 if (Size
< MI_MIN_INIT_PAGED_POOLSIZE
) Size
= MI_MIN_INIT_PAGED_POOLSIZE
;
1526 Size
= BYTES_TO_PAGES(Size
);
1529 // Now check how many PTEs will be required for these many pages.
1531 Size
= (Size
+ (1024 - 1)) / 1024;
1534 // Recompute the page-aligned size of the paged pool, in bytes and pages.
1536 MmSizeOfPagedPoolInBytes
= Size
* PAGE_SIZE
* 1024;
1537 MmSizeOfPagedPoolInPages
= MmSizeOfPagedPoolInBytes
>> PAGE_SHIFT
;
1540 // Let's be really sure this doesn't overflow into nonpaged system VA
1542 ASSERT((MmSizeOfPagedPoolInBytes
+ (ULONG_PTR
)MmPagedPoolStart
) <=
1543 (ULONG_PTR
)MmNonPagedSystemStart
);
1546 // This is where paged pool ends
1548 MmPagedPoolEnd
= (PVOID
)(((ULONG_PTR
)MmPagedPoolStart
+
1549 MmSizeOfPagedPoolInBytes
) - 1);
1552 // So now get the PDE for paged pool and zero it out
1554 PointerPde
= MiAddressToPde(MmPagedPoolStart
);
1555 RtlZeroMemory(PointerPde
,
1556 (1 + MiAddressToPde(MmPagedPoolEnd
) - PointerPde
) * sizeof(MMPTE
));
1559 // Next, get the first and last PTE
1561 PointerPte
= MiAddressToPte(MmPagedPoolStart
);
1562 MmPagedPoolInfo
.FirstPteForPagedPool
= PointerPte
;
1563 MmPagedPoolInfo
.LastPteForPagedPool
= MiAddressToPte(MmPagedPoolEnd
);
1566 // Lock the PFN database
1568 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
1570 /* Allocate a page and map the first paged pool PDE */
1571 PageFrameIndex
= MiRemoveZeroPage(0);
1572 TempPte
.u
.Hard
.PageFrameNumber
= PageFrameIndex
;
1573 MI_WRITE_VALID_PTE(PointerPde
, TempPte
);
1575 /* Initialize the PFN entry for it */
1576 MiInitializePfnForOtherProcess(PageFrameIndex
,
1578 MmSystemPageDirectory
[(PointerPde
- (PMMPTE
)PDE_BASE
) / PDE_COUNT
]);
1581 // Release the PFN database lock
1583 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
1586 // We only have one PDE mapped for now... at fault time, additional PDEs
1587 // will be allocated to handle paged pool growth. This is where they'll have
1590 MmPagedPoolInfo
.NextPdeForPagedPoolExpansion
= PointerPde
+ 1;
1593 // We keep track of each page via a bit, so check how big the bitmap will
1594 // have to be (make sure to align our page count such that it fits nicely
1595 // into a 4-byte aligned bitmap.
1597 // We'll also allocate the bitmap header itself part of the same buffer.
1600 ASSERT(Size
== MmSizeOfPagedPoolInPages
);
1602 Size
= sizeof(RTL_BITMAP
) + (((Size
+ 31) / 32) * sizeof(ULONG
));
1605 // Allocate the allocation bitmap, which tells us which regions have not yet
1606 // been mapped into memory
1608 MmPagedPoolInfo
.PagedPoolAllocationMap
= ExAllocatePoolWithTag(NonPagedPool
,
1611 ASSERT(MmPagedPoolInfo
.PagedPoolAllocationMap
);
1614 // Initialize it such that at first, only the first page's worth of PTEs is
1615 // marked as allocated (incidentially, the first PDE we allocated earlier).
1617 RtlInitializeBitMap(MmPagedPoolInfo
.PagedPoolAllocationMap
,
1618 (PULONG
)(MmPagedPoolInfo
.PagedPoolAllocationMap
+ 1),
1620 RtlSetAllBits(MmPagedPoolInfo
.PagedPoolAllocationMap
);
1621 RtlClearBits(MmPagedPoolInfo
.PagedPoolAllocationMap
, 0, 1024);
1624 // We have a second bitmap, which keeps track of where allocations end.
1625 // Given the allocation bitmap and a base address, we can therefore figure
1626 // out which page is the last page of that allocation, and thus how big the
1627 // entire allocation is.
1629 MmPagedPoolInfo
.EndOfPagedPoolBitmap
= ExAllocatePoolWithTag(NonPagedPool
,
1632 ASSERT(MmPagedPoolInfo
.EndOfPagedPoolBitmap
);
1633 RtlInitializeBitMap(MmPagedPoolInfo
.EndOfPagedPoolBitmap
,
1634 (PULONG
)(MmPagedPoolInfo
.EndOfPagedPoolBitmap
+ 1),
1638 // Since no allocations have been made yet, there are no bits set as the end
1640 RtlClearAllBits(MmPagedPoolInfo
.EndOfPagedPoolBitmap
);
1643 // Initialize paged pool.
1645 InitializePool(PagedPool
, 0);
1647 /* Default low threshold of 30MB or one fifth of paged pool */
1648 MiLowPagedPoolThreshold
= (30 * _1MB
) >> PAGE_SHIFT
;
1649 MiLowPagedPoolThreshold
= min(MiLowPagedPoolThreshold
, Size
/ 5);
1651 /* Default high threshold of 60MB or 25% */
1652 MiHighPagedPoolThreshold
= (60 * _1MB
) >> PAGE_SHIFT
;
1653 MiHighPagedPoolThreshold
= min(MiHighPagedPoolThreshold
, (Size
* 2) / 5);
1654 ASSERT(MiLowPagedPoolThreshold
< MiHighPagedPoolThreshold
);
1659 MmArmInitSystem(IN ULONG Phase
,
1660 IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
1663 BOOLEAN IncludeType
[LoaderMaximum
];
1665 PPHYSICAL_MEMORY_RUN Run
;
1666 PFN_NUMBER PageCount
;
1669 // Instantiate memory that we don't consider RAM/usable
1670 // We use the same exclusions that Windows does, in order to try to be
1671 // compatible with WinLDR-style booting
1673 for (i
= 0; i
< LoaderMaximum
; i
++) IncludeType
[i
] = TRUE
;
1674 IncludeType
[LoaderBad
] = FALSE
;
1675 IncludeType
[LoaderFirmwarePermanent
] = FALSE
;
1676 IncludeType
[LoaderSpecialMemory
] = FALSE
;
1677 IncludeType
[LoaderBBTMemory
] = FALSE
;
1680 /* Initialize the phase 0 temporary event */
1681 KeInitializeEvent(&MiTempEvent
, NotificationEvent
, FALSE
);
1683 /* Set all the events to use the temporary event for now */
1684 MiLowMemoryEvent
= &MiTempEvent
;
1685 MiHighMemoryEvent
= &MiTempEvent
;
1686 MiLowPagedPoolEvent
= &MiTempEvent
;
1687 MiHighPagedPoolEvent
= &MiTempEvent
;
1688 MiLowNonPagedPoolEvent
= &MiTempEvent
;
1689 MiHighNonPagedPoolEvent
= &MiTempEvent
;
1692 // Define the basic user vs. kernel address space separation
1694 MmSystemRangeStart
= (PVOID
)KSEG0_BASE
;
1695 MmUserProbeAddress
= (ULONG_PTR
)MmSystemRangeStart
- 0x10000;
1696 MmHighestUserAddress
= (PVOID
)(MmUserProbeAddress
- 1);
1698 /* Highest PTE and PDE based on the addresses above */
1699 MiHighestUserPte
= MiAddressToPte(MmHighestUserAddress
);
1700 MiHighestUserPde
= MiAddressToPde(MmHighestUserAddress
);
1703 // Get the size of the boot loader's image allocations and then round
1704 // that region up to a PDE size, so that any PDEs we might create for
1705 // whatever follows are separate from the PDEs that boot loader might've
1706 // already created (and later, we can blow all that away if we want to).
1708 MmBootImageSize
= KeLoaderBlock
->Extension
->LoaderPagesSpanned
;
1709 MmBootImageSize
*= PAGE_SIZE
;
1710 MmBootImageSize
= (MmBootImageSize
+ PDE_MAPPED_VA
- 1) & ~(PDE_MAPPED_VA
- 1);
1711 ASSERT((MmBootImageSize
% PDE_MAPPED_VA
) == 0);
1714 // Set the size of session view, pool, and image
1716 MmSessionSize
= MI_SESSION_SIZE
;
1717 MmSessionViewSize
= MI_SESSION_VIEW_SIZE
;
1718 MmSessionPoolSize
= MI_SESSION_POOL_SIZE
;
1719 MmSessionImageSize
= MI_SESSION_IMAGE_SIZE
;
1722 // Set the size of system view
1724 MmSystemViewSize
= MI_SYSTEM_VIEW_SIZE
;
1727 // This is where it all ends
1729 MiSessionImageEnd
= (PVOID
)PTE_BASE
;
1732 // This is where we will load Win32k.sys and the video driver
1734 MiSessionImageStart
= (PVOID
)((ULONG_PTR
)MiSessionImageEnd
-
1735 MmSessionImageSize
);
1738 // So the view starts right below the session working set (itself below
1741 MiSessionViewStart
= (PVOID
)((ULONG_PTR
)MiSessionImageEnd
-
1742 MmSessionImageSize
-
1743 MI_SESSION_WORKING_SET_SIZE
-
1747 // Session pool follows
1749 MiSessionPoolEnd
= MiSessionViewStart
;
1750 MiSessionPoolStart
= (PVOID
)((ULONG_PTR
)MiSessionPoolEnd
-
1754 // And it all begins here
1756 MmSessionBase
= MiSessionPoolStart
;
1759 // Sanity check that our math is correct
1761 ASSERT((ULONG_PTR
)MmSessionBase
+ MmSessionSize
== PTE_BASE
);
1764 // Session space ends wherever image session space ends
1766 MiSessionSpaceEnd
= MiSessionImageEnd
;
1769 // System view space ends at session space, so now that we know where
1770 // this is, we can compute the base address of system view space itself.
1772 MiSystemViewStart
= (PVOID
)((ULONG_PTR
)MmSessionBase
-
1775 /* Compute the PTE addresses for all the addresses we carved out */
1776 MiSessionImagePteStart
= MiAddressToPte(MiSessionImageStart
);
1777 MiSessionImagePteEnd
= MiAddressToPte(MiSessionImageEnd
);
1778 MiSessionBasePte
= MiAddressToPte(MmSessionBase
);
1779 MiSessionLastPte
= MiAddressToPte(MiSessionSpaceEnd
);
1781 /* Initialize the user mode image list */
1782 InitializeListHead(&MmLoadedUserImageList
);
1784 /* Initialize the paged pool mutex */
1785 KeInitializeGuardedMutex(&MmPagedPoolMutex
);
1787 /* Initialize the Loader Lock */
1788 KeInitializeMutant(&MmSystemLoadLock
, FALSE
);
1791 // Count physical pages on the system
1793 PageCount
= MiPagesInLoaderBlock(LoaderBlock
, IncludeType
);
1796 // Check if this is a machine with less than 19MB of RAM
1798 if (PageCount
< MI_MIN_PAGES_FOR_SYSPTE_TUNING
)
1801 // Use the very minimum of system PTEs
1803 MmNumberOfSystemPtes
= 7000;
1808 // Use the default, but check if we have more than 32MB of RAM
1810 MmNumberOfSystemPtes
= 11000;
1811 if (PageCount
> MI_MIN_PAGES_FOR_SYSPTE_BOOST
)
1814 // Double the amount of system PTEs
1816 MmNumberOfSystemPtes
<<= 1;
1820 DPRINT("System PTE count has been tuned to %d (%d bytes)\n",
1821 MmNumberOfSystemPtes
, MmNumberOfSystemPtes
* PAGE_SIZE
);
1823 /* Initialize the working set lock */
1824 ExInitializePushLock((PULONG_PTR
)&MmSystemCacheWs
.WorkingSetMutex
);
1826 /* Set commit limit */
1827 MmTotalCommitLimit
= 2 * _1GB
;
1828 MmTotalCommitLimitMaximum
= MmTotalCommitLimit
;
1830 /* Has the allocation fragment been setup? */
1831 if (!MmAllocationFragment
)
1833 /* Use the default value */
1834 MmAllocationFragment
= MI_ALLOCATION_FRAGMENT
;
1835 if (PageCount
< ((256 * _1MB
) / PAGE_SIZE
))
1837 /* On memory systems with less than 256MB, divide by 4 */
1838 MmAllocationFragment
= MI_ALLOCATION_FRAGMENT
/ 4;
1840 else if (PageCount
< (_1GB
/ PAGE_SIZE
))
1842 /* On systems with less than 1GB, divide by 2 */
1843 MmAllocationFragment
= MI_ALLOCATION_FRAGMENT
/ 2;
1848 /* Convert from 1KB fragments to pages */
1849 MmAllocationFragment
*= _1KB
;
1850 MmAllocationFragment
= ROUND_TO_PAGES(MmAllocationFragment
);
1852 /* Don't let it past the maximum */
1853 MmAllocationFragment
= min(MmAllocationFragment
,
1854 MI_MAX_ALLOCATION_FRAGMENT
);
1856 /* Don't let it too small either */
1857 MmAllocationFragment
= max(MmAllocationFragment
,
1858 MI_MIN_ALLOCATION_FRAGMENT
);
1861 /* Initialize the platform-specific parts */
1862 MiInitMachineDependent(LoaderBlock
);
1865 // Sync us up with ReactOS Mm
1867 MiSyncARM3WithROS(MmNonPagedSystemStart
, (PVOID
)((ULONG_PTR
)MmNonPagedPoolEnd
- 1));
1868 MiSyncARM3WithROS(MmPfnDatabase
, (PVOID
)((ULONG_PTR
)MmNonPagedPoolStart
+ MmSizeOfNonPagedPoolInBytes
- 1));
1869 MiSyncARM3WithROS((PVOID
)HYPER_SPACE
, (PVOID
)(HYPER_SPACE
+ PAGE_SIZE
- 1));
1872 // Build the physical memory block
1874 MmPhysicalMemoryBlock
= MmInitializeMemoryLimits(LoaderBlock
,
1878 // Allocate enough buffer for the PFN bitmap
1879 // Align it up to a 32-bit boundary
1881 Bitmap
= ExAllocatePoolWithTag(NonPagedPool
,
1882 (((MmHighestPhysicalPage
+ 1) + 31) / 32) * 4,
1889 KeBugCheckEx(INSTALL_MORE_MEMORY
,
1890 MmNumberOfPhysicalPages
,
1891 MmLowestPhysicalPage
,
1892 MmHighestPhysicalPage
,
1897 // Initialize it and clear all the bits to begin with
1899 RtlInitializeBitMap(&MiPfnBitMap
,
1901 MmHighestPhysicalPage
+ 1);
1902 RtlClearAllBits(&MiPfnBitMap
);
1905 // Loop physical memory runs
1907 for (i
= 0; i
< MmPhysicalMemoryBlock
->NumberOfRuns
; i
++)
1912 Run
= &MmPhysicalMemoryBlock
->Run
[i
];
1913 DPRINT("PHYSICAL RAM [0x%08p to 0x%08p]\n",
1914 Run
->BasePage
<< PAGE_SHIFT
,
1915 (Run
->BasePage
+ Run
->PageCount
) << PAGE_SHIFT
);
1918 // Make sure it has pages inside it
1923 // Set the bits in the PFN bitmap
1925 RtlSetBits(&MiPfnBitMap
, Run
->BasePage
, Run
->PageCount
);
1929 /* Look for large page cache entries that need caching */
1930 MiSyncCachedRanges();
1932 /* Loop for HAL Heap I/O device mappings that need coherency tracking */
1933 MiAddHalIoMappings();
1935 /* Set the initial resident page count */
1936 MmResidentAvailablePages
= MmAvailablePages
- 32;
1938 /* Initialize large page structures on PAE/x64, and MmProcessList on x86 */
1939 MiInitializeLargePageSupport();
1941 /* Check if the registry says any drivers should be loaded with large pages */
1942 MiInitializeDriverLargePageList();
1944 /* Relocate the boot drivers into system PTE space and fixup their PFNs */
1945 MiReloadBootLoadedDrivers(LoaderBlock
);
1947 /* FIXME: Call out into Driver Verifier for initialization */
1949 /* Check how many pages the system has */
1950 if (MmNumberOfPhysicalPages
<= ((13 * _1MB
) / PAGE_SIZE
))
1952 /* Set small system */
1953 MmSystemSize
= MmSmallSystem
;
1955 else if (MmNumberOfPhysicalPages
<= ((19 * _1MB
) / PAGE_SIZE
))
1957 /* Set small system and add 100 pages for the cache */
1958 MmSystemSize
= MmSmallSystem
;
1959 MmSystemCacheWsMinimum
+= 100;
1963 /* Set medium system and add 400 pages for the cache */
1964 MmSystemSize
= MmMediumSystem
;
1965 MmSystemCacheWsMinimum
+= 400;
1968 /* Check for less than 24MB */
1969 if (MmNumberOfPhysicalPages
< ((24 * _1MB
) / PAGE_SIZE
))
1971 /* No more than 32 pages */
1972 MmSystemCacheWsMinimum
= 32;
1975 /* Check for more than 32MB */
1976 if (MmNumberOfPhysicalPages
>= ((32 * _1MB
) / PAGE_SIZE
))
1978 /* Check for product type being "Wi" for WinNT */
1979 if (MmProductType
== '\0i\0W')
1981 /* Then this is a large system */
1982 MmSystemSize
= MmLargeSystem
;
1986 /* For servers, we need 64MB to consider this as being large */
1987 if (MmNumberOfPhysicalPages
>= ((64 * _1MB
) / PAGE_SIZE
))
1989 /* Set it as large */
1990 MmSystemSize
= MmLargeSystem
;
1995 /* Check for more than 33 MB */
1996 if (MmNumberOfPhysicalPages
> ((33 * _1MB
) / PAGE_SIZE
))
1998 /* Add another 500 pages to the cache */
1999 MmSystemCacheWsMinimum
+= 500;
2002 /* Now setup the shared user data fields */
2003 ASSERT(SharedUserData
->NumberOfPhysicalPages
== 0);
2004 SharedUserData
->NumberOfPhysicalPages
= MmNumberOfPhysicalPages
;
2005 SharedUserData
->LargePageMinimum
= 0;
2007 /* Check for workstation (Wi for WinNT) */
2008 if (MmProductType
== '\0i\0W')
2010 /* Set Windows NT Workstation product type */
2011 SharedUserData
->NtProductType
= NtProductWinNt
;
2016 /* Check for LanMan server */
2017 if (MmProductType
== '\0a\0L')
2019 /* This is a domain controller */
2020 SharedUserData
->NtProductType
= NtProductLanManNt
;
2024 /* Otherwise it must be a normal server */
2025 SharedUserData
->NtProductType
= NtProductServer
;
2028 /* Set the product type, and make the system more aggressive with low memory */
2030 MmMinimumFreePages
= 81;
2033 /* Update working set tuning parameters */
2034 MiAdjustWorkingSetManagerParameters(!MmProductType
);
2036 /* Finetune the page count by removing working set and NP expansion */
2037 MmResidentAvailablePages
-= MiExpansionPoolPagesInitialCharge
;
2038 MmResidentAvailablePages
-= MmSystemCacheWsMinimum
;
2039 MmResidentAvailableAtInit
= MmResidentAvailablePages
;
2040 if (MmResidentAvailablePages
<= 0)
2042 /* This should not happen */
2043 DPRINT1("System cache working set too big\n");
2047 /* Initialize the system cache */
2048 //MiInitializeSystemCache(MmSystemCacheWsMinimum, MmAvailablePages);
2050 /* Update the commit limit */
2051 MmTotalCommitLimit
= MmAvailablePages
;
2052 if (MmTotalCommitLimit
> 1024) MmTotalCommitLimit
-= 1024;
2053 MmTotalCommitLimitMaximum
= MmTotalCommitLimit
;
2055 /* Size up paged pool and build the shadow system page directory */
2058 /* Debugger physical memory support is now ready to be used */
2059 MmDebugPte
= MiAddressToPte(MiDebugMapping
);
2061 /* Initialize the loaded module list */
2062 MiInitializeLoadedModuleList(LoaderBlock
);
2066 // Always return success for now
2068 return STATUS_SUCCESS
;