-#ifndef __INTERNAL_HAL_BUS_H
-#define __INTERNAL_HAL_BUS_H
+#pragma once
+
+#define PCI_ADDRESS_MEMORY_SPACE 0x00000000
//
// Helper Macros
#define TYPE1_READ(x, y) \
TYPE1_START(x, y) \
*((POINTER_TO_(y))Buffer) = \
- READ_FROM(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i)); \
+ READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \
TYPE1_END(y)
//
//
#define TYPE1_WRITE(x, y) \
TYPE1_START(x, y) \
- WRITE_TO(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i), \
+ WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \
*((POINTER_TO_(y))Buffer)); \
TYPE1_END(y)
#define TYPE2_READ(x, y) \
TYPE2_START(x, y) \
*((POINTER_TO_(y))Buffer) = \
- READ_FROM(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT); \
+ READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \
TYPE2_END(y)
//
//
#define TYPE2_WRITE(x, y) \
TYPE2_START(x, y) \
- WRITE_TO(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT, \
+ WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \
*((POINTER_TO_(y))Buffer)); \
TYPE2_END(y)
+typedef NTSTATUS
+(NTAPI *PciIrqRange)(
+ IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN PCI_SLOT_NUMBER PciSlot,
+ OUT PSUPPORTED_RANGE *Interrupt
+);
+
typedef struct _PCIPBUSDATA
{
PCIBUSDATA CommonData;
} Type2;
} Config;
ULONG MaxDevice;
+ PciIrqRange GetIrqRange;
+ BOOLEAN BridgeConfigRead;
+ UCHAR ParentBus;
+ UCHAR Subtractive;
+ UCHAR reserved[1];
+ UCHAR SwizzleIn[4];
+ RTL_BITMAP DeviceConfigured;
+ ULONG ConfiguredBits[PCI_MAX_DEVICES * PCI_MAX_FUNCTION / 32];
} PCIPBUSDATA, *PPCIPBUSDATA;
typedef ULONG
{
UCHAR MajorRevision;
UCHAR MinorRevision;
- UCHAR NoBuses;
+ UCHAR NoBuses; // Number Of Buses
UCHAR HardwareMechanism;
ULONG ElementCount;
PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
} PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
+//
+// PCI Type 1 Ports
+//
+#define PCI_TYPE1_ADDRESS_PORT (PULONG)0xCF8
+#define PCI_TYPE1_DATA_PORT 0xCFC
+
+//
+// PCI Type 2 Ports
+//
+#define PCI_TYPE2_CSE_PORT (PUCHAR)0xCF8
+#define PCI_TYPE2_FORWARD_PORT (PUCHAR)0xCFA
+#define PCI_TYPE2_ADDRESS_BASE 0xC
+
+//
+// PCI Type 1 Configuration Register
+//
+typedef struct _PCI_TYPE1_CFG_BITS
+{
+ union
+ {
+ struct
+ {
+ ULONG Reserved1:2;
+ ULONG RegisterNumber:6;
+ ULONG FunctionNumber:3;
+ ULONG DeviceNumber:5;
+ ULONG BusNumber:8;
+ ULONG Reserved2:7;
+ ULONG Enable:1;
+ } bits;
+
+ ULONG AsULONG;
+ } u;
+} PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS;
+
+//
+// PCI Type 2 CSE Register
+//
+typedef struct _PCI_TYPE2_CSE_BITS
+{
+ union
+ {
+ struct
+ {
+ UCHAR Enable:1;
+ UCHAR FunctionNumber:3;
+ UCHAR Key:4;
+ } bits;
+
+ UCHAR AsUCHAR;
+ } u;
+} PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS;
+
+//
+// PCI Type 2 Address Register
+//
+typedef struct _PCI_TYPE2_ADDRESS_BITS
+{
+ union
+ {
+ struct
+ {
+ USHORT RegisterNumber:8;
+ USHORT Agent:4;
+ USHORT AddressBase:4;
+ } bits;
+
+ USHORT AsUSHORT;
+ } u;
+} PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS;
+
+typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
+{
+ union
+ {
+ struct
+ {
+ ULONG Reserved1:2;
+ ULONG RegisterNumber:6;
+ ULONG FunctionNumber:3;
+ ULONG Reserved2:21;
+ } bits;
+ ULONG AsULONG;
+ } u;
+} PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
+
+typedef struct _PCI_TYPE1_CFG_CYCLE_BITS
+{
+ union
+ {
+ struct
+ {
+ ULONG Reserved1:2;
+ ULONG RegisterNumber:6;
+ ULONG FunctionNumber:3;
+ ULONG DeviceNumber:5;
+ ULONG BusNumber:8;
+ ULONG Reserved2:8;
+ } bits;
+ ULONG AsULONG;
+ } u;
+} PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
+
+typedef struct _ARRAY
+{
+ ULONG ArraySize;
+ PVOID Element[ANYSIZE_ARRAY];
+} ARRAY, *PARRAY;
+
+typedef struct _HAL_BUS_HANDLER
+{
+ LIST_ENTRY AllHandlers;
+ ULONG ReferenceCount;
+ BUS_HANDLER Handler;
+} HAL_BUS_HANDLER, *PHAL_BUS_HANDLER;
+
/* FUNCTIONS *****************************************************************/
+/* SHARED (Fake PCI-BUS HANDLER) */
+
+extern PCI_CONFIG_HANDLER PCIConfigHandler;
+extern PCI_CONFIG_HANDLER PCIConfigHandlerType1;
+extern PCI_CONFIG_HANDLER PCIConfigHandlerType2;
+
+PPCI_REGISTRY_INFO_INTERNAL
+NTAPI
+HalpQueryPciRegistryInfo(
+ VOID
+);
+
VOID
NTAPI
HalpPCISynchronizeType1(
ULONG
NTAPI
-HalpGetSystemInterruptVector(
+HalpGetPCIData(
+ IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootBusHandler,
+ IN PCI_SLOT_NUMBER SlotNumber,
+ IN PVOID Buffer,
+ IN ULONG Offset,
+ IN ULONG Length
+);
+
+ULONG
+NTAPI
+HalpSetPCIData(
+ IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootBusHandler,
+ IN PCI_SLOT_NUMBER SlotNumber,
+ IN PVOID Buffer,
+ IN ULONG Offset,
+ IN ULONG Length
+);
+
+NTSTATUS
+NTAPI
+HalpAssignPCISlotResources(
+ IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN PUNICODE_STRING RegistryPath,
+ IN PUNICODE_STRING DriverClassName OPTIONAL,
+ IN PDRIVER_OBJECT DriverObject,
+ IN PDEVICE_OBJECT DeviceObject OPTIONAL,
+ IN ULONG Slot,
+ IN OUT PCM_RESOURCE_LIST *pAllocatedResources
+);
+
+/* NON-LEGACY */
+
+ULONG
+NTAPI
+HalpGetSystemInterruptVector_Acpi(
ULONG BusNumber,
ULONG BusInterruptLevel,
ULONG BusInterruptVector,
IN ULONG Length
);
+VOID
+NTAPI
+HalpInitializePciBus(
+ VOID
+);
+
+VOID
+NTAPI
+HalpInitializePciStubs(
+ VOID
+);
+
+BOOLEAN
+NTAPI
+HalpTranslateBusAddress(
+ IN INTERFACE_TYPE InterfaceType,
+ IN ULONG BusNumber,
+ IN PHYSICAL_ADDRESS BusAddress,
+ IN OUT PULONG AddressSpace,
+ OUT PPHYSICAL_ADDRESS TranslatedAddress
+);
+
+NTSTATUS
+NTAPI
+HalpAssignSlotResources(
+ IN PUNICODE_STRING RegistryPath,
+ IN PUNICODE_STRING DriverClassName,
+ IN PDRIVER_OBJECT DriverObject,
+ IN PDEVICE_OBJECT DeviceObject,
+ IN INTERFACE_TYPE BusType,
+ IN ULONG BusNumber,
+ IN ULONG SlotNumber,
+ IN OUT PCM_RESOURCE_LIST *AllocatedResources
+);
+
+BOOLEAN
+NTAPI
+HalpFindBusAddressTranslation(
+ IN PHYSICAL_ADDRESS BusAddress,
+ IN OUT PULONG AddressSpace,
+ OUT PPHYSICAL_ADDRESS TranslatedAddress,
+ IN OUT PULONG_PTR Context,
+ IN BOOLEAN NextBus
+);
+
+VOID
+NTAPI
+HalpRegisterPciDebuggingDeviceInfo(
+ VOID
+);
+
+/* LEGACY */
+
+BOOLEAN
+NTAPI
+HaliTranslateBusAddress(
+ IN INTERFACE_TYPE InterfaceType,
+ IN ULONG BusNumber,
+ IN PHYSICAL_ADDRESS BusAddress,
+ IN OUT PULONG AddressSpace,
+ OUT PPHYSICAL_ADDRESS TranslatedAddress
+);
+
+BOOLEAN
+NTAPI
+HaliFindBusAddressTranslation(
+ IN PHYSICAL_ADDRESS BusAddress,
+ IN OUT PULONG AddressSpace,
+ OUT PPHYSICAL_ADDRESS TranslatedAddress,
+ IN OUT PULONG_PTR Context,
+ IN BOOLEAN NextBus
+);
+
+NTSTATUS
+NTAPI
+HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList);
+
ULONG
NTAPI
-HalpGetPCIData(
+HalpGetPCIIntOnISABus(IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN ULONG BusInterruptLevel,
+ IN ULONG BusInterruptVector,
+ OUT PKIRQL Irql,
+ OUT PKAFFINITY Affinity);
+VOID
+NTAPI
+HalpPCIPin2ISALine(IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN PCI_SLOT_NUMBER SlotNumber,
+ IN PPCI_COMMON_CONFIG PciData);
+
+VOID
+NTAPI
+HalpPCIISALine2Pin(IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN PCI_SLOT_NUMBER SlotNumber,
+ IN PPCI_COMMON_CONFIG PciNewData,
+ IN PPCI_COMMON_CONFIG PciOldData);
+
+NTSTATUS
+NTAPI
+HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN PCI_SLOT_NUMBER PciSlot,
+ OUT PSUPPORTED_RANGE *Range);
+
+VOID
+NTAPI
+HalpInitBusHandler(
+ VOID
+);
+
+PBUS_HANDLER
+NTAPI
+HalpContextToBusHandler(
+ IN ULONG_PTR ContextValue
+);
+
+PBUS_HANDLER
+FASTCALL
+HaliReferenceHandlerForConfigSpace(
+ IN BUS_DATA_TYPE ConfigType,
+ IN ULONG BusNumber
+);
+
+ULONG
+NTAPI
+HalpNoBusData(
IN PBUS_HANDLER BusHandler,
- IN PBUS_HANDLER RootBusHandler,
- IN PCI_SLOT_NUMBER SlotNumber,
- IN PUCHAR Buffer,
+ IN PBUS_HANDLER RootHandler,
+ IN ULONG SlotNumber,
+ IN PVOID Buffer,
IN ULONG Offset,
IN ULONG Length
);
ULONG
NTAPI
-HalpSetPCIData(
+HalpcGetCmosData(
IN PBUS_HANDLER BusHandler,
- IN PBUS_HANDLER RootBusHandler,
- IN PCI_SLOT_NUMBER SlotNumber,
- IN PUCHAR Buffer,
+ IN PBUS_HANDLER RootHandler,
+ IN ULONG SlotNumber,
+ IN PVOID Buffer,
IN ULONG Offset,
IN ULONG Length
);
-NTSTATUS
+ULONG
NTAPI
-HalpAssignPCISlotResources(
+HalpcSetCmosData(
IN PBUS_HANDLER BusHandler,
IN PBUS_HANDLER RootHandler,
- IN PUNICODE_STRING RegistryPath,
- IN PUNICODE_STRING DriverClassName OPTIONAL,
- IN PDRIVER_OBJECT DriverObject,
- IN PDEVICE_OBJECT DeviceObject OPTIONAL,
- IN ULONG Slot,
- IN OUT PCM_RESOURCE_LIST *pAllocatedResources
+ IN ULONG SlotNumber,
+ IN PVOID Buffer,
+ IN ULONG Offset,
+ IN ULONG Length
);
-VOID
+BOOLEAN
NTAPI
-HalpInitializePciBus(
- VOID
+HalpTranslateSystemBusAddress(
+ IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN PHYSICAL_ADDRESS BusAddress,
+ IN OUT PULONG AddressSpace,
+ OUT PPHYSICAL_ADDRESS TranslatedAddress
);
+BOOLEAN
+NTAPI
+HalpTranslateIsaBusAddress(
+ IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN PHYSICAL_ADDRESS BusAddress,
+ IN OUT PULONG AddressSpace,
+ OUT PPHYSICAL_ADDRESS TranslatedAddress
+);
+
+ULONG
+NTAPI
+HalpGetSystemInterruptVector(
+ IN PBUS_HANDLER BusHandler,
+ IN PBUS_HANDLER RootHandler,
+ IN ULONG BusInterruptLevel,
+ IN ULONG BusInterruptVector,
+ OUT PKIRQL Irql,
+ OUT PKAFFINITY Affinity
+);
+
extern ULONG HalpBusType;
extern BOOLEAN HalpPCIConfigInitialized;
extern BUS_HANDLER HalpFakePciBusHandler;
extern ULONG HalpMinPciBus, HalpMaxPciBus;
-
-#endif /* __INTERNAL_HAL_BUS_H */
+extern LIST_ENTRY HalpAllBusHandlers;
/* EOF */
-
-