drivers/usb/usbohci_new/hardware.h

   1 #define OHCI_NUMBER_OF_INTERRUPTS    32
   2 #define OHCI_MAX_PORT_COUNT          15
   3 #define ED_EOF                       -1
   4 #define OHCI_MAXIMUM_OVERHEAD        210 // 5.4  FrameInterval Counter, in bit-times
   5 #define OHCI_DEFAULT_FRAME_INTERVAL  11999 // 6.3.1  Frame Timing
   6 #define OHCI_MINIMAL_POTPGT          25 // == 50 ms., PowerOnToPowerGoodTime (HcRhDescriptorA Register)
   7
   8 /* Controller states */
   9 #define OHCI_HC_STATE_RESET       0
  10 #define OHCI_HC_STATE_RESUME      1
  11 #define OHCI_HC_STATE_OPERATIONAL 2
  12 #define OHCI_HC_STATE_SUSPEND     3
  13
  14 /* Endpoint Descriptor Control */
  15 #define OHCI_ED_DATA_FLOW_DIRECTION_FROM_TD 0
  16 #define OHCI_ED_DATA_FLOW_DIRECTION_OUT     1
  17 #define OHCI_ED_DATA_FLOW_DIRECTION_IN      2
  18
  19 #define OHCI_ENDPOINT_FULL_SPEED 0
  20 #define OHCI_ENDPOINT_LOW_SPEED  1
  21
  22 #define OHCI_ENDPOINT_GENERAL_FORMAT     0
  23 #define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 1
  24
  25 /* Transfer Descriptor Control */
  26 #define OHCI_TD_INTERRUPT_IMMEDIATE 0
  27 #define OHCI_TD_INTERRUPT_NONE      7
  28
  29 #define OHCI_TD_DIRECTION_PID_SETUP    0
  30 #define OHCI_TD_DIRECTION_PID_OUT      1
  31 #define OHCI_TD_DIRECTION_PID_IN       2
  32 #define OHCI_TD_DIRECTION_PID_RESERVED 3
  33
  34 #define OHCI_TD_DATA_TOGGLE_FROM_ED  0
  35 #define OHCI_TD_DATA_TOGGLE_DATA0    2
  36 #define OHCI_TD_DATA_TOGGLE_DATA1    3
  37
  38 #define OHCI_TD_CONDITION_NO_ERROR          0x00
  39 #define OHCI_TD_CONDITION_CRC_ERROR         0x01
  40 #define OHCI_TD_CONDITION_BIT_STUFFING      0x02
  41 #define OHCI_TD_CONDITION_TOGGLE_MISMATCH   0x03
  42 #define OHCI_TD_CONDITION_STALL             0x04
  43 #define OHCI_TD_CONDITION_NO_RESPONSE       0x05
  44 #define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06
  45 #define OHCI_TD_CONDITION_UNEXPECTED_PID    0x07
  46 #define OHCI_TD_CONDITION_DATA_OVERRUN      0x08
  47 #define OHCI_TD_CONDITION_DATA_UNDERRUN     0x09
  48 #define OHCI_TD_CONDITION_BUFFER_OVERRUN    0x0C
  49 #define OHCI_TD_CONDITION_BUFFER_UNDERRUN   0x0D
  50 #define OHCI_TD_CONDITION_NOT_ACCESSED      0x0E
  51
  52 typedef union _OHCI_TRANSFER_CONTROL {
  53   struct {
  54     ULONG Reserved       : 18;
  55     ULONG BufferRounding : 1;
  56     ULONG DirectionPID   : 2;
  57     ULONG DelayInterrupt : 3;
  58     ULONG DataToggle     : 2;
  59     ULONG ErrorCount     : 2;
  60     ULONG ConditionCode  : 4;
  61   };
  62   ULONG  AsULONG;
  63 } OHCI_TRANSFER_CONTROL, *POHCI_TRANSFER_CONTROL;
  64
  65 C_ASSERT(sizeof(OHCI_TRANSFER_CONTROL) == sizeof(ULONG));
  66
  67 typedef struct _OHCI_TRANSFER_DESCRIPTOR { // must be aligned to a 16-byte boundary
  68   OHCI_TRANSFER_CONTROL Control;
  69   ULONG CurrentBuffer; // physical address of the next memory location
  70   ULONG NextTD; // pointer to the next TD on the list of TDs
  71   ULONG BufferEnd; // physical address of the last byte
  72 } OHCI_TRANSFER_DESCRIPTOR, *POHCI_TRANSFER_DESCRIPTOR;
  73
  74 C_ASSERT(sizeof(OHCI_TRANSFER_DESCRIPTOR) == 16);
  75
  76 typedef union _OHCI_ISO_TRANSFER_CONTROL {
  77   struct {
  78     ULONG StartingFrame  : 16;
  79     ULONG Reserved1      : 5;
  80     ULONG DelayInterrupt : 3;
  81     ULONG FrameCount     : 3;
  82     ULONG Reserved2      : 1;
  83     ULONG ConditionCode  : 4;
  84   };
  85   ULONG  AsULONG;
  86 } OHCI_ISO_TRANSFER_CONTROL, *POHCI_ISO_TRANSFER_CONTROL;
  87
  88 C_ASSERT(sizeof(OHCI_ISO_TRANSFER_CONTROL) == sizeof(ULONG));
  89
  90 typedef struct _OHCI_ISO_TRANSFER_DESCRIPTOR { // must be aligned to a 32-byte boundary
  91   OHCI_ISO_TRANSFER_CONTROL Control;
  92   ULONG BufferPage0; // physical page number of the 1 byte of the data buffer
  93   ULONG NextTD; // pointer to the next Isochronous TD on the queue of Isochronous TDs
  94   ULONG BufferEnd; // physical address of the last byte in the buffer
  95   USHORT Offset[8]; // for determine size and start addr. iso packet | PacketStatusWord - completion code
  96 } OHCI_ISO_TRANSFER_DESCRIPTOR, *POHCI_ISO_TRANSFER_DESCRIPTOR;
  97
  98 C_ASSERT(sizeof(OHCI_ISO_TRANSFER_DESCRIPTOR) == 32);
  99
 100 typedef union _OHCI_ENDPOINT_CONTROL {
 101   struct {
 102     ULONG FunctionAddress   : 7;
 103     ULONG EndpointNumber    : 4;
 104     ULONG Direction         : 2;
 105     ULONG Speed             : 1;
 106     ULONG sKip              : 1;
 107     ULONG Format            : 1;
 108     ULONG MaximumPacketSize : 11;
 109     ULONG Reserved          : 5;
 110   };
 111   ULONG  AsULONG;
 112 } OHCI_ENDPOINT_CONTROL, *POHCI_ENDPOINT_CONTROL;
 113
 114 C_ASSERT(sizeof(OHCI_ENDPOINT_CONTROL) == sizeof(ULONG));
 115
 116 /* Bit flags for HeadPointer member of the EP descriptor */
 117 #define OHCI_ED_HEAD_POINTER_HALT        0x00000001 // hardware stopped bit
 118 #define OHCI_ED_HEAD_POINTER_CARRY       0x00000002 // hardware toggle carry bit
 119 #define OHCI_ED_HEAD_POINTER_MASK        0XFFFFFFF0 // mask physical pointer
 120 #define OHCI_ED_HEAD_POINTER_FLAGS_MASK  0X0000000F // mask bit flags
 121
 122 typedef struct _OHCI_ENDPOINT_DESCRIPTOR { // must be aligned to a 16-byte boundary
 123   OHCI_ENDPOINT_CONTROL EndpointControl;
 124   ULONG TailPointer; // if TailP and HeadP are different, then the list contains a TD to be processed
 125   ULONG HeadPointer; // physical pointer to the next TD to be processed for this endpoint
 126   ULONG NextED; // entry points to the next ED on the list
 127 } OHCI_ENDPOINT_DESCRIPTOR, *POHCI_ENDPOINT_DESCRIPTOR;
 128
 129 C_ASSERT(sizeof(OHCI_ENDPOINT_DESCRIPTOR) == 16);
 130
 131 typedef struct _OHCI_HCCA { // must be located on a 256-byte boundary
 132   ULONG InterrruptTable[OHCI_NUMBER_OF_INTERRUPTS];
 133   USHORT FrameNumber;
 134   USHORT Pad1;
 135   ULONG DoneHead;
 136   UCHAR reserved_hc[116];
 137   UCHAR Pad[4];
 138 } OHCI_HCCA, *POHCI_HCCA;
 139
 140 C_ASSERT(sizeof(OHCI_HCCA) == 256);
 141
 142 typedef union _OHCI_REG_CONTROL {
 143   struct {
 144     ULONG ControlBulkServiceRatio       : 2;
 145     ULONG PeriodicListEnable            : 1;
 146     ULONG IsochronousEnable             : 1;
 147     ULONG ControlListEnable             : 1;
 148     ULONG BulkListEnable                : 1;
 149     ULONG HostControllerFunctionalState : 2;
 150     ULONG InterruptRouting              : 1;
 151     ULONG RemoteWakeupConnected         : 1;
 152     ULONG RemoteWakeupEnable            : 1;
 153     ULONG Reserved                      : 21;
 154   };
 155   ULONG AsULONG;
 156 } OHCI_REG_CONTROL, *POHCI_REG_CONTROL;
 157
 158 C_ASSERT(sizeof(OHCI_REG_CONTROL) == sizeof(ULONG));
 159
 160 typedef union _OHCI_REG_COMMAND_STATUS {
 161   struct {
 162     ULONG HostControllerReset    : 1;
 163     ULONG ControlListFilled      : 1;
 164     ULONG BulkListFilled         : 1;
 165     ULONG OwnershipChangeRequest : 1;
 166     ULONG Reserved1              : 12;
 167     ULONG SchedulingOverrunCount : 1;
 168     ULONG Reserved2              : 15;
 169   };
 170   ULONG AsULONG;
 171 } OHCI_REG_COMMAND_STATUS, *POHCI_REG_COMMAND_STATUS;
 172
 173 C_ASSERT(sizeof(OHCI_REG_COMMAND_STATUS) == sizeof(ULONG));
 174
 175 typedef union _OHCI_REG_INTERRUPT_STATUS {
 176   struct {
 177     ULONG SchedulingOverrun   : 1;
 178     ULONG WritebackDoneHead   : 1;
 179     ULONG StartofFrame        : 1;
 180     ULONG ResumeDetected      : 1;
 181     ULONG UnrecoverableError  : 1;
 182     ULONG FrameNumberOverflow : 1;
 183     ULONG RootHubStatusChange : 1;
 184     ULONG Reserved1           : 23;
 185     ULONG OwnershipChange     : 1;
 186     ULONG Reserved2           : 1;
 187   };
 188   ULONG AsULONG;
 189 } OHCI_REG_INTERRUPT_STATUS, *POHCI_REG_INTERRUPT_STATUS;
 190
 191 C_ASSERT(sizeof(OHCI_REG_INTERRUPT_STATUS) == sizeof(ULONG));
 192
 193 typedef union _OHCI_REG_INTERRUPT_ENABLE_DISABLE {
 194   struct {
 195     ULONG SchedulingOverrun     : 1;
 196     ULONG WritebackDoneHead     : 1;
 197     ULONG StartofFrame          : 1;
 198     ULONG ResumeDetected        : 1;
 199     ULONG UnrecoverableError    : 1;
 200     ULONG FrameNumberOverflow   : 1;
 201     ULONG RootHubStatusChange   : 1;
 202     ULONG Reserved1             : 23;
 203     ULONG OwnershipChange       : 1;
 204     ULONG MasterInterruptEnable : 1;
 205   };
 206   ULONG AsULONG;
 207 } OHCI_REG_INTERRUPT_ENABLE_DISABLE, *POHCI_REG_INTERRUPT_ENABLE_DISABLE;
 208
 209 C_ASSERT(sizeof(OHCI_REG_INTERRUPT_ENABLE_DISABLE) == sizeof(ULONG));
 210
 211 typedef union _OHCI_REG_FRAME_INTERVAL {
 212   struct {
 213     ULONG FrameInterval       : 14;
 214     ULONG Reserved            : 2;
 215     ULONG FSLargestDataPacket : 15;
 216     ULONG FrameIntervalToggle : 1;
 217   };
 218   ULONG AsULONG;
 219 } OHCI_REG_FRAME_INTERVAL, *POHCI_REG_FRAME_INTERVAL;
 220
 221 C_ASSERT(sizeof(OHCI_REG_FRAME_INTERVAL) == sizeof(ULONG));
 222
 223 typedef union _OHCI_REG_RH_DESCRIPTORA {
 224   struct {
 225     ULONG NumberDownstreamPorts     : 8;
 226     ULONG PowerSwitchingMode        : 1;
 227     ULONG NoPowerSwitching          : 1;
 228     ULONG DeviceType                : 1;
 229     ULONG OverCurrentProtectionMode : 1;
 230     ULONG NoOverCurrentProtection   : 1;
 231     ULONG Reserved                  : 11;
 232     ULONG PowerOnToPowerGoodTime    : 8;
 233   };
 234   ULONG AsULONG;
 235 } OHCI_REG_RH_DESCRIPTORA, *POHCI_REG_RH_DESCRIPTORA;
 236
 237 C_ASSERT(sizeof(OHCI_REG_RH_DESCRIPTORA) == sizeof(ULONG));
 238
 239 typedef union _OHCI_REG_RH_STATUS {
 240   union {
 241     struct { // read
 242       ULONG LocalPowerStatus            : 1;
 243       ULONG OverCurrentIndicator        : 1;
 244       ULONG Reserved10                  : 13;
 245       ULONG DeviceRemoteWakeupEnable    : 1;
 246       ULONG LocalPowerStatusChange      : 1;
 247       ULONG OverCurrentIndicatorChangeR : 1;
 248       ULONG Reserved20                  : 14;
 249     };
 250     struct { // write
 251       ULONG ClearGlobalPower            : 1;
 252       ULONG Reserved11                  : 14;
 253       ULONG SetRemoteWakeupEnable       : 1;
 254       ULONG SetGlobalPower              : 1;
 255       ULONG OverCurrentIndicatorChangeW : 1;
 256       ULONG Reserved22                  : 13;
 257       ULONG ClearRemoteWakeupEnable     : 1;
 258     };
 259   };
 260   ULONG AsULONG;
 261 } OHCI_REG_RH_STATUS, *POHCI_REG_RH_STATUS;
 262
 263 C_ASSERT(sizeof(OHCI_REG_RH_STATUS) == sizeof(ULONG));
 264
 265 typedef union _OHCI_REG_RH_PORT_STATUS {
 266   struct {
 267     union  {
 268       struct { // read
 269         USHORT  CurrentConnectStatus     : 1;
 270         USHORT  PortEnableStatus         : 1;
 271         USHORT  PortSuspendStatus        : 1;
 272         USHORT  PortOverCurrentIndicator : 1;
 273         USHORT  PortResetStatus          : 1;
 274         USHORT  Reserved1r               : 3;
 275         USHORT  PortPowerStatus          : 1;
 276         USHORT  LowSpeedDeviceAttached   : 1;
 277         USHORT  Reserved2r               : 6;
 278       };
 279       struct { // write
 280         USHORT  ClearPortEnable    : 1;
 281         USHORT  SetPortEnable      : 1;
 282         USHORT  SetPortSuspend     : 1;
 283         USHORT  ClearSuspendStatus : 1;
 284         USHORT  SetPortReset       : 1;
 285         USHORT  Reserved1w         : 3;
 286         USHORT  SetPortPower       : 1;
 287         USHORT  ClearPortPower     : 1;
 288         USHORT  Reserved2w         : 6;
 289       };
 290     };
 291     USHORT ConnectStatusChange            : 1;
 292     USHORT PortEnableStatusChange         : 1;
 293     USHORT PortSuspendStatusChange        : 1;
 294     USHORT PortOverCurrentIndicatorChange : 1;
 295     USHORT PortResetStatusChange          : 1;
 296     USHORT Reserved3                      : 11;
 297   };
 298   ULONG  AsULONG;
 299 } OHCI_REG_RH_PORT_STATUS, *POHCI_REG_RH_PORT_STATUS;
 300
 301 C_ASSERT(sizeof(OHCI_REG_RH_PORT_STATUS) == sizeof(ULONG));
 302
 303 typedef struct _OHCI_OPERATIONAL_REGISTERS {
 304   ULONG HcRevision;
 305   OHCI_REG_CONTROL HcControl;
 306   OHCI_REG_COMMAND_STATUS HcCommandStatus;
 307   OHCI_REG_INTERRUPT_STATUS HcInterruptStatus;
 308   OHCI_REG_INTERRUPT_ENABLE_DISABLE HcInterruptEnable;
 309   OHCI_REG_INTERRUPT_ENABLE_DISABLE HcInterruptDisable;
 310   ULONG HcHCCA;
 311   ULONG HcPeriodCurrentED;
 312   ULONG HcControlHeadED;
 313   ULONG HcControlCurrentED;
 314   ULONG HcBulkHeadED;
 315   ULONG HcBulkCurrentED;
 316   ULONG HcDoneHead;
 317   OHCI_REG_FRAME_INTERVAL HcFmInterval;
 318   ULONG HcFmRemaining;
 319   ULONG HcFmNumber;
 320   ULONG HcPeriodicStart;
 321   ULONG HcLSThreshold;
 322   OHCI_REG_RH_DESCRIPTORA HcRhDescriptorA;
 323   ULONG HcRhDescriptorB;
 324   OHCI_REG_RH_STATUS HcRhStatus;
 325   OHCI_REG_RH_PORT_STATUS HcRhPortStatus[OHCI_MAX_PORT_COUNT];
 326 } OHCI_OPERATIONAL_REGISTERS, *POHCI_OPERATIONAL_REGISTERS;