7 #define PLACE_IN_SECTION(s) __attribute__((section (s)))
10 #define PAGE_LOCKED_FUNCTION PLACE_IN_SECTION("pagelk")
11 #define PAGE_UNLOCKED_FUNCTION PLACE_IN_SECTION("pagepo")
14 #define PAGE_LOCKED_FUNCTION
15 #define PAGE_UNLOCKED_FUNCTION
19 #define REGISTERCALL FASTCALL
21 #define REGISTERCALL __attribute__((regparm(3)))
25 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
27 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
30 typedef struct _HAL_BIOS_FRAME
37 PKTRAP_FRAME TrapFrame
;
45 } HAL_BIOS_FRAME
, *PHAL_BIOS_FRAME
;
49 (*PHAL_SW_INTERRUPT_HANDLER
)(
56 (FASTCALL
*PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY
)(
57 IN PKTRAP_FRAME TrapFrame
60 #define HAL_APC_REQUEST 0
61 #define HAL_DPC_REQUEST 1
63 /* CMOS Registers and Ports */
64 #define CMOS_CONTROL_PORT (PUCHAR)0x70
65 #define CMOS_DATA_PORT (PUCHAR)0x71
66 #define RTC_REGISTER_A 0x0A
67 #define RTC_REG_A_UIP 0x80
68 #define RTC_REGISTER_B 0x0B
69 #define RTC_REG_B_PI 0x40
70 #define RTC_REGISTER_C 0x0C
71 #define RTC_REGISTER_D 0x0D
72 #define RTC_REGISTER_CENTURY 0x32
75 #define IDT_REGISTERED 0x01
76 #define IDT_LATCHED 0x02
77 #define IDT_READ_ONLY 0x04
78 #define IDT_INTERNAL 0x11
79 #define IDT_DEVICE 0x21
81 /* Conversion functions */
82 #define BCD_INT(bcd) \
83 (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
84 #define INT_BCD(int) \
85 (UCHAR)(((int / 10) << 4) + (int % 10))
90 #define VIDEO_SERVICES 0x10
93 // Operations for INT 10h (in AH)
95 #define SET_VIDEO_MODE 0x00
98 // Video Modes for INT10h AH=00 (in AL)
100 #define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
103 // Commonly stated as being 1.19318MHz
105 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
108 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
109 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
111 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
112 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
113 // infinite series) and divides it by three, one obtains 1.19318167.
115 // It may be that the original NT HAL source code introduced a typo and turned
116 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
117 // number is quite long.
119 #define PIT_FREQUENCY 1193182
122 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
124 #define TIMER_CHANNEL0_DATA_PORT 0x40
125 #define TIMER_CHANNEL1_DATA_PORT 0x41
126 #define TIMER_CHANNEL2_DATA_PORT 0x42
127 #define TIMER_CONTROL_PORT 0x43
130 // Mode 0 - Interrupt On Terminal Count
131 // Mode 1 - Hardware Re-triggerable One-Shot
132 // Mode 2 - Rate Generator
133 // Mode 3 - Square Wave Generator
134 // Mode 4 - Software Triggered Strobe
135 // Mode 5 - Hardware Triggered Strobe
137 typedef enum _TIMER_OPERATING_MODES
145 PitOperatingMode2Reserved
,
146 PitOperatingMode5Reserved
147 } TIMER_OPERATING_MODES
;
149 typedef enum _TIMER_ACCESS_MODES
151 PitAccessModeCounterLatch
,
155 } TIMER_ACCESS_MODES
;
157 typedef enum _TIMER_CHANNELS
165 typedef union _TIMER_CONTROL_PORT_REGISTER
170 UCHAR OperatingMode
:3;
175 } TIMER_CONTROL_PORT_REGISTER
, *PTIMER_CONTROL_PORT_REGISTER
;
178 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
181 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
183 #define SYSTEM_CONTROL_PORT_A 0x92
184 #define SYSTEM_CONTROL_PORT_B 0x61
185 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
189 UCHAR Timer2GateToSpeaker
:1;
190 UCHAR SpeakerDataEnable
:1;
191 UCHAR ParityCheckEnable
:1;
192 UCHAR ChannelCheckEnable
:1;
193 UCHAR RefreshRequest
:1;
194 UCHAR Timer2Output
:1;
195 UCHAR ChannelCheck
:1;
199 } SYSTEM_CONTROL_PORT_B_REGISTER
, *PSYSTEM_CONTROL_PORT_B_REGISTER
;
202 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
205 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
207 #define PIC1_CONTROL_PORT 0x20
208 #define PIC1_DATA_PORT 0x21
209 #define PIC2_CONTROL_PORT 0xA0
210 #define PIC2_DATA_PORT 0xA1
213 // Definitions for ICW/OCW Bits
215 typedef enum _I8259_ICW1_OPERATING_MODE
219 } I8259_ICW1_OPERATING_MODE
;
221 typedef enum _I8259_ICW1_INTERRUPT_MODE
225 } I8259_ICW1_INTERRUPT_MODE
;
227 typedef enum _I8259_ICW1_INTERVAL
231 } I8259_ICW1_INTERVAL
;
233 typedef enum _I8259_ICW4_SYSTEM_MODE
237 } I8259_ICW4_SYSTEM_MODE
;
239 typedef enum _I8259_ICW4_EOI_MODE
243 } I8259_ICW4_EOI_MODE
;
245 typedef enum _I8259_ICW4_BUFFERED_MODE
251 } I8259_ICW4_BUFFERED_MODE
;
253 typedef enum _I8259_READ_REQUEST
259 } I8259_READ_REQUEST
;
261 typedef enum _I8259_EOI_MODE
274 // Definitions for ICW Registers
276 typedef union _I8259_ICW1
281 UCHAR OperatingMode
:1;
283 UCHAR InterruptMode
:1;
285 UCHAR InterruptVectorAddress
:3;
288 } I8259_ICW1
, *PI8259_ICW1
;
290 typedef union _I8259_ICW2
295 UCHAR InterruptVector
:5;
298 } I8259_ICW2
, *PI8259_ICW2
;
300 typedef union _I8259_ICW3
322 } I8259_ICW3
, *PI8259_ICW3
;
324 typedef union _I8259_ICW4
330 UCHAR BufferedMode
:2;
331 UCHAR SpecialFullyNestedMode
:1;
335 } I8259_ICW4
, *PI8259_ICW4
;
337 typedef union _I8259_OCW2
346 } I8259_OCW2
, *PI8259_OCW2
;
348 typedef union _I8259_OCW3
356 UCHAR SpecialMaskMode
:2;
360 } I8259_OCW3
, *PI8259_OCW3
;
362 typedef union _I8259_ISR
379 } I8259_ISR
, *PI8259_ISR
;
381 typedef I8259_ISR I8259_IDR
, *PI8259_IDR
;
384 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
387 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
389 #define EISA_ELCR_MASTER 0x4D0
390 #define EISA_ELCR_SLAVE 0x4D1
392 typedef union _EISA_ELCR
420 } EISA_ELCR
, *PEISA_ELCR
;
422 typedef struct _PIC_MASK
433 } PIC_MASK
, *PPIC_MASK
;
437 ( REGISTERCALL
*PHAL_DISMISS_INTERRUPT
)(
445 HalpDismissIrqGeneric(
485 HalpDismissIrq15Level(
493 HalpDismissIrq13Level(
501 HalpDismissIrq07Level(
508 HalpHardwareInterruptLevel(
515 #define HALP_REVISION_FROM_HACK_FLAGS(x) ((x) >> 24)
516 #define HALP_REVISION_HACK_FLAGS(x) ((x) >> 12)
517 #define HALP_HACK_FLAGS(x) ((x) & 0xFFF)
522 #define HALP_CARD_FEATURE_FULL_DECODE 0x0001
527 #define HALP_CHECK_CARD_REVISION_ID 0x10000
528 #define HALP_CHECK_CARD_SUBVENDOR_ID 0x20000
529 #define HALP_CHECK_CARD_SUBSYSTEM_ID 0x40000
532 // Mm PTE/PDE to Hal PTE/PDE
534 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
535 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
537 typedef struct _IDTUsageFlags
545 UCHAR BusReleativeVector
;
548 typedef struct _HalAddressUsage
550 struct _HalAddressUsage
*Next
;
551 CM_RESOURCE_TYPE Type
;
558 } ADDRESS_USAGE
, *PADDRESS_USAGE
;
561 PADAPTER_OBJECT NTAPI
HalpAllocateAdapterEx(ULONG NumberOfMapRegisters
,BOOLEAN IsMaster
, BOOLEAN Dma32BitAddresses
);
566 HalpRegisterVector(IN UCHAR Flags
,
568 IN ULONG SystemVector
,
573 HalpEnableInterruptHandler(IN UCHAR Flags
,
575 IN ULONG SystemVector
,
578 IN KINTERRUPT_MODE Mode
);
581 VOID NTAPI
HalpInitializePICs(IN BOOLEAN EnableInterrupts
);
582 VOID
HalpApcInterrupt(VOID
);
583 VOID
HalpDispatchInterrupt(VOID
);
584 VOID
HalpDispatchInterrupt2(VOID
);
585 DECLSPEC_NORETURN VOID FASTCALL
HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame
);
586 DECLSPEC_NORETURN VOID FASTCALL
HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame
);
589 VOID NTAPI
HalpInitializeClock(VOID
);
590 VOID
HalpClockInterrupt(VOID
);
591 VOID
HalpProfileInterrupt(VOID
);
595 HalpCalibrateStallExecution(VOID
);
598 VOID
HalpInitPciBus (VOID
);
601 VOID
HalpInitDma (VOID
);
603 /* Non-generic initialization */
604 VOID
HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock
);
605 VOID
HalpInitPhase1(VOID
);
616 HalpCheckPowerButton(
622 HalpRegisterKdSupportFunctions(
628 HalpSetupPciDeviceForDebugging(
629 IN PVOID LoaderBlock
,
630 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
635 HalpReleasePciDeviceForDebugging(
636 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
644 HalpAllocPhysicalMemory(
645 IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
646 IN ULONG_PTR MaxAddress
,
647 IN PFN_NUMBER PageCount
,
653 HalpMapPhysicalMemory64(
654 IN PHYSICAL_ADDRESS PhysicalAddress
,
655 IN PFN_COUNT PageCount
660 HalpUnmapVirtualAddress(
661 IN PVOID VirtualAddress
,
662 IN PFN_COUNT NumberPages
668 HaliQuerySystemInformation(
669 IN HAL_QUERY_INFORMATION_CLASS InformationClass
,
672 OUT PULONG ReturnedLength
677 HaliSetSystemInformation(
678 IN HAL_SET_INFORMATION_CLASS InformationClass
,
688 HalpBiosDisplayReset(
695 PKTRAP_FRAME TrapFrame
705 // Processor Halt Routine
736 // Spinlock for protecting CMOS access
740 HalpAcquireCmosSpinLock(
746 HalpReleaseCmosSpinLock(
753 IN PHANDLE KeyHandle
,
755 IN PUNICODE_STRING KeyName
,
756 IN ACCESS_MASK DesiredAccess
,
768 HalpGetDebugPortTable(
774 HalpReportSerialNumber(
792 HalpReportResourceUsage(
793 IN PUNICODE_STRING HalName
,
794 IN INTERFACE_TYPE InterfaceType
799 HalpIs16BitPortDecodeSupported(
805 HalpQueryAcpiResourceRequirements(
806 OUT PIO_RESOURCE_REQUIREMENTS_LIST
*Requirements
812 IN PKTRAP_FRAME TrapFrame
,
835 IN PPCI_COMMON_CONFIG PciData
841 IN ULONG ProcessorNumber
,
842 IN PLOADER_PARAMETER_BLOCK LoaderBlock
846 #define KfLowerIrql KeLowerIrql
847 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
848 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
849 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
851 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
852 #define KiAcquireSpinLock(SpinLock)
853 #define KiReleaseSpinLock(SpinLock)
854 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
855 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
856 #endif // !CONFIG_SMP
859 extern BOOLEAN HalpNMIInProgress
;
861 extern ADDRESS_USAGE HalpDefaultIoSpace
;
863 extern KSPIN_LOCK HalpSystemHardwareLock
;
865 extern PADDRESS_USAGE HalpAddressUsageList
;
867 extern LARGE_INTEGER HalpPerfCounter
;
869 extern KAFFINITY HalpActiveProcessors
;
871 extern BOOLEAN HalDisableFirmwareMapper
;
872 extern PWCHAR HalHardwareIdString
;
873 extern PWCHAR HalName
;
875 extern KAFFINITY HalpDefaultInterruptAffinity
;
877 extern IDTUsageFlags HalpIDTUsageFlags
[MAXIMUM_IDTVECTOR
+1];
879 extern const USHORT HalpBuildType
;