hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7 #if defined(__GNUC__) && !defined(_MINIHAL_)
   8 #define INIT_SECTION __attribute__((section ("INIT")))
   9 #else
  10 #define INIT_SECTION /* Done via alloc_text for MSC */
  11 #endif
  12
  13
  14 #ifdef CONFIG_SMP
  15 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
  16 #else
  17 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
  18 #endif
  19
  20 typedef struct _HAL_BIOS_FRAME
  21 {
  22     ULONG SegSs;
  23     ULONG Esp;
  24     ULONG EFlags;
  25     ULONG SegCs;
  26     ULONG Eip;
  27     PKTRAP_FRAME TrapFrame;
  28     ULONG CsLimit;
  29     ULONG CsBase;
  30     ULONG CsFlags;
  31     ULONG SsLimit;
  32     ULONG SsBase;
  33     ULONG SsFlags;
  34     ULONG Prefix;
  35 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  36
  37 typedef
  38 VOID
  39 (__cdecl *PHAL_SW_INTERRUPT_HANDLER)(
  40     VOID
  41 );
  42
  43 typedef
  44 VOID
  45 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  46     IN PKTRAP_FRAME TrapFrame
  47 );
  48
  49 #define HAL_APC_REQUEST         0
  50 #define HAL_DPC_REQUEST         1
  51
  52 /* HAL profiling offsets in KeGetPcr()->HalReserved[] */
  53 #define HAL_PROFILING_INTERVAL      0
  54 #define HAL_PROFILING_MULTIPLIER    1
  55
  56 /* CMOS Registers and Ports */
  57 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  58 #define CMOS_DATA_PORT          (PUCHAR)0x71
  59 #define RTC_REGISTER_A          0x0A
  60 #define   RTC_REG_A_UIP         0x80
  61 #define RTC_REGISTER_B          0x0B
  62 #define   RTC_REG_B_PI          0x40
  63 #define RTC_REGISTER_C          0x0C
  64 #define   RTC_REG_C_IRQ         0x80
  65 #define RTC_REGISTER_D          0x0D
  66 #define RTC_REGISTER_CENTURY    0x32
  67
  68 /* Usage flags */
  69 #define IDT_REGISTERED          0x01
  70 #define IDT_LATCHED             0x02
  71 #define IDT_READ_ONLY           0x04
  72 #define IDT_INTERNAL            0x11
  73 #define IDT_DEVICE              0x21
  74
  75 /* Conversion functions */
  76 #define BCD_INT(bcd)            \
  77     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  78 #define INT_BCD(int)            \
  79     (UCHAR)(((int / 10) << 4) + (int % 10))
  80
  81 //
  82 // BIOS Interrupts
  83 //
  84 #define VIDEO_SERVICES   0x10
  85
  86 //
  87 // Operations for INT 10h (in AH)
  88 //
  89 #define SET_VIDEO_MODE   0x00
  90
  91 //
  92 // Video Modes for INT10h AH=00 (in AL)
  93 //
  94 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
  95
  96 //
  97 // Commonly stated as being 1.19318MHz
  98 //
  99 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 100 // P. 471
 101 //
 102 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
 103 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
 104 //
 105 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
 106 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
 107 // infinite series) and divides it by three, one obtains 1.19318167.
 108 //
 109 // It may be that the original NT HAL source code introduced a typo and turned
 110 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
 111 // number is quite long.
 112 //
 113 #define PIT_FREQUENCY 1193182
 114
 115 //
 116 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 117 //
 118 #define TIMER_CHANNEL0_DATA_PORT 0x40
 119 #define TIMER_CHANNEL1_DATA_PORT 0x41
 120 #define TIMER_CHANNEL2_DATA_PORT 0x42
 121 #define TIMER_CONTROL_PORT       0x43
 122
 123 //
 124 // Mode 0 - Interrupt On Terminal Count
 125 // Mode 1 - Hardware Re-triggerable One-Shot
 126 // Mode 2 - Rate Generator
 127 // Mode 3 - Square Wave Generator
 128 // Mode 4 - Software Triggered Strobe
 129 // Mode 5 - Hardware Triggered Strobe
 130 //
 131 typedef enum _TIMER_OPERATING_MODES
 132 {
 133     PitOperatingMode0,
 134     PitOperatingMode1,
 135     PitOperatingMode2,
 136     PitOperatingMode3,
 137     PitOperatingMode4,
 138     PitOperatingMode5,
 139     PitOperatingMode2Reserved,
 140     PitOperatingMode5Reserved
 141 } TIMER_OPERATING_MODES;
 142
 143 typedef enum _TIMER_ACCESS_MODES
 144 {
 145     PitAccessModeCounterLatch,
 146     PitAccessModeLow,
 147     PitAccessModeHigh,
 148     PitAccessModeLowHigh
 149 } TIMER_ACCESS_MODES;
 150
 151 typedef enum _TIMER_CHANNELS
 152 {
 153     PitChannel0,
 154     PitChannel1,
 155     PitChannel2,
 156     PitReadBack
 157 } TIMER_CHANNELS;
 158
 159 typedef union _TIMER_CONTROL_PORT_REGISTER
 160 {
 161     struct
 162     {
 163         UCHAR BcdMode:1;
 164         UCHAR OperatingMode:3;
 165         UCHAR AccessMode:2;
 166         UCHAR Channel:2;
 167     };
 168     UCHAR Bits;
 169 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 170
 171 //
 172 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 173 // P. 400
 174 //
 175 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 176 //
 177 #define SYSTEM_CONTROL_PORT_A   0x92
 178 #define SYSTEM_CONTROL_PORT_B   0x61
 179 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 180 {
 181     struct
 182     {
 183         UCHAR Timer2GateToSpeaker:1;
 184         UCHAR SpeakerDataEnable:1;
 185         UCHAR ParityCheckEnable:1;
 186         UCHAR ChannelCheckEnable:1;
 187         UCHAR RefreshRequest:1;
 188         UCHAR Timer2Output:1;
 189         UCHAR ChannelCheck:1;
 190         UCHAR ParityCheck:1;
 191     };
 192     UCHAR Bits;
 193 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 194
 195 //
 196 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 197 // P. 396, 397
 198 //
 199 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 200 //
 201 #define PIC1_CONTROL_PORT      0x20
 202 #define PIC1_DATA_PORT         0x21
 203 #define PIC2_CONTROL_PORT      0xA0
 204 #define PIC2_DATA_PORT         0xA1
 205
 206 //
 207 // Definitions for ICW/OCW Bits
 208 //
 209 typedef enum _I8259_ICW1_OPERATING_MODE
 210 {
 211     Cascade,
 212     Single
 213 } I8259_ICW1_OPERATING_MODE;
 214
 215 typedef enum _I8259_ICW1_INTERRUPT_MODE
 216 {
 217     EdgeTriggered,
 218     LevelTriggered
 219 } I8259_ICW1_INTERRUPT_MODE;
 220
 221 typedef enum _I8259_ICW1_INTERVAL
 222 {
 223     Interval8,
 224     Interval4
 225 } I8259_ICW1_INTERVAL;
 226
 227 typedef enum _I8259_ICW4_SYSTEM_MODE
 228 {
 229     Mcs8085Mode,
 230     New8086Mode
 231 } I8259_ICW4_SYSTEM_MODE;
 232
 233 typedef enum _I8259_ICW4_EOI_MODE
 234 {
 235     NormalEoi,
 236     AutomaticEoi
 237 } I8259_ICW4_EOI_MODE;
 238
 239 typedef enum _I8259_ICW4_BUFFERED_MODE
 240 {
 241     NonBuffered,
 242     NonBuffered2,
 243     BufferedSlave,
 244     BufferedMaster
 245 } I8259_ICW4_BUFFERED_MODE;
 246
 247 typedef enum _I8259_READ_REQUEST
 248 {
 249     InvalidRequest,
 250     InvalidRequest2,
 251     ReadIdr,
 252     ReadIsr
 253 } I8259_READ_REQUEST;
 254
 255 typedef enum _I8259_EOI_MODE
 256 {
 257     RotateAutoEoiClear,
 258     NonSpecificEoi,
 259     InvalidEoiMode,
 260     SpecificEoi,
 261     RotateAutoEoiSet,
 262     RotateNonSpecific,
 263     SetPriority,
 264     RotateSpecific
 265 } I8259_EOI_MODE;
 266
 267 //
 268 // Definitions for ICW Registers
 269 //
 270 typedef union _I8259_ICW1
 271 {
 272     struct
 273     {
 274         UCHAR NeedIcw4:1;
 275         UCHAR OperatingMode:1;
 276         UCHAR Interval:1;
 277         UCHAR InterruptMode:1;
 278         UCHAR Init:1;
 279         UCHAR InterruptVectorAddress:3;
 280     };
 281     UCHAR Bits;
 282 } I8259_ICW1, *PI8259_ICW1;
 283
 284 typedef union _I8259_ICW2
 285 {
 286     struct
 287     {
 288         UCHAR Sbz:3;
 289         UCHAR InterruptVector:5;
 290     };
 291     UCHAR Bits;
 292 } I8259_ICW2, *PI8259_ICW2;
 293
 294 typedef union _I8259_ICW3
 295 {
 296     union
 297     {
 298         struct
 299         {
 300             UCHAR SlaveIrq0:1;
 301             UCHAR SlaveIrq1:1;
 302             UCHAR SlaveIrq2:1;
 303             UCHAR SlaveIrq3:1;
 304             UCHAR SlaveIrq4:1;
 305             UCHAR SlaveIrq5:1;
 306             UCHAR SlaveIrq6:1;
 307             UCHAR SlaveIrq7:1;
 308         };
 309         struct
 310         {
 311             UCHAR SlaveId:3;
 312             UCHAR Reserved:5;
 313         };
 314     };
 315     UCHAR Bits;
 316 } I8259_ICW3, *PI8259_ICW3;
 317
 318 typedef union _I8259_ICW4
 319 {
 320     struct
 321     {
 322         UCHAR SystemMode:1;
 323         UCHAR EoiMode:1;
 324         UCHAR BufferedMode:2;
 325         UCHAR SpecialFullyNestedMode:1;
 326         UCHAR Reserved:3;
 327     };
 328     UCHAR Bits;
 329 } I8259_ICW4, *PI8259_ICW4;
 330
 331 typedef union _I8259_OCW2
 332 {
 333     struct
 334     {
 335         UCHAR IrqNumber:3;
 336         UCHAR Sbz:2;
 337         UCHAR EoiMode:3;
 338     };
 339     UCHAR Bits;
 340 } I8259_OCW2, *PI8259_OCW2;
 341
 342 typedef union _I8259_OCW3
 343 {
 344     struct
 345     {
 346         UCHAR ReadRequest:2;
 347         UCHAR PollCommand:1;
 348         UCHAR Sbo:1;
 349         UCHAR Sbz:1;
 350         UCHAR SpecialMaskMode:2;
 351         UCHAR Reserved:1;
 352     };
 353     UCHAR Bits;
 354 } I8259_OCW3, *PI8259_OCW3;
 355
 356 typedef union _I8259_ISR
 357 {
 358     union
 359     {
 360         struct
 361         {
 362             UCHAR Irq0:1;
 363             UCHAR Irq1:1;
 364             UCHAR Irq2:1;
 365             UCHAR Irq3:1;
 366             UCHAR Irq4:1;
 367             UCHAR Irq5:1;
 368             UCHAR Irq6:1;
 369             UCHAR Irq7:1;
 370         };
 371     };
 372     UCHAR Bits;
 373 } I8259_ISR, *PI8259_ISR;
 374
 375 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 376
 377 //
 378 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 379 // P. 34, 35
 380 //
 381 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 382 //
 383 #define EISA_ELCR_MASTER       0x4D0
 384 #define EISA_ELCR_SLAVE        0x4D1
 385
 386 typedef union _EISA_ELCR
 387 {
 388     struct
 389     {
 390         struct
 391         {
 392             UCHAR Irq0Level:1;
 393             UCHAR Irq1Level:1;
 394             UCHAR Irq2Level:1;
 395             UCHAR Irq3Level:1;
 396             UCHAR Irq4Level:1;
 397             UCHAR Irq5Level:1;
 398             UCHAR Irq6Level:1;
 399             UCHAR Irq7Level:1;
 400         } Master;
 401         struct
 402         {
 403             UCHAR Irq8Level:1;
 404             UCHAR Irq9Level:1;
 405             UCHAR Irq10Level:1;
 406             UCHAR Irq11Level:1;
 407             UCHAR Irq12Level:1;
 408             UCHAR Irq13Level:1;
 409             UCHAR Irq14Level:1;
 410             UCHAR Irq15Level:1;
 411         } Slave;
 412     };
 413     USHORT Bits;
 414 } EISA_ELCR, *PEISA_ELCR;
 415
 416 typedef struct _PIC_MASK
 417 {
 418     union
 419     {
 420         struct
 421         {
 422             UCHAR Master;
 423             UCHAR Slave;
 424         };
 425         USHORT Both;
 426     };
 427 } PIC_MASK, *PPIC_MASK;
 428
 429 typedef
 430 BOOLEAN
 431 (NTAPI *PHAL_DISMISS_INTERRUPT)(
 432     IN KIRQL Irql,
 433     IN ULONG Irq,
 434     OUT PKIRQL OldIrql
 435 );
 436
 437 BOOLEAN
 438 NTAPI
 439 HalpDismissIrqGeneric(
 440     IN KIRQL Irql,
 441     IN ULONG Irq,
 442     OUT PKIRQL OldIrql
 443 );
 444
 445 BOOLEAN
 446 NTAPI
 447 HalpDismissIrq15(
 448     IN KIRQL Irql,
 449     IN ULONG Irq,
 450     OUT PKIRQL OldIrql
 451 );
 452
 453 BOOLEAN
 454 NTAPI
 455 HalpDismissIrq13(
 456     IN KIRQL Irql,
 457     IN ULONG Irq,
 458     OUT PKIRQL OldIrql
 459 );
 460
 461 BOOLEAN
 462 NTAPI
 463 HalpDismissIrq07(
 464     IN KIRQL Irql,
 465     IN ULONG Irq,
 466     OUT PKIRQL OldIrql
 467 );
 468
 469 BOOLEAN
 470 NTAPI
 471 HalpDismissIrqLevel(
 472     IN KIRQL Irql,
 473     IN ULONG Irq,
 474     OUT PKIRQL OldIrql
 475 );
 476
 477 BOOLEAN
 478 NTAPI
 479 HalpDismissIrq15Level(
 480     IN KIRQL Irql,
 481     IN ULONG Irq,
 482     OUT PKIRQL OldIrql
 483 );
 484
 485 BOOLEAN
 486 NTAPI
 487 HalpDismissIrq13Level(
 488     IN KIRQL Irql,
 489     IN ULONG Irq,
 490     OUT PKIRQL OldIrql
 491 );
 492
 493 BOOLEAN
 494 NTAPI
 495 HalpDismissIrq07Level(
 496     IN KIRQL Irql,
 497     IN ULONG Irq,
 498     OUT PKIRQL OldIrql
 499 );
 500
 501 VOID
 502 __cdecl
 503 HalpHardwareInterruptLevel(
 504     VOID
 505 );
 506
 507 //
 508 // Hack Flags
 509 //
 510 #define HALP_REVISION_FROM_HACK_FLAGS(x)    ((x) >> 24)
 511 #define HALP_REVISION_HACK_FLAGS(x)         ((x) >> 12)
 512 #define HALP_HACK_FLAGS(x)                  ((x) & 0xFFF)
 513
 514 //
 515 // Feature flags
 516 //
 517 #define HALP_CARD_FEATURE_FULL_DECODE   0x0001
 518
 519 //
 520 // Match Flags
 521 //
 522 #define HALP_CHECK_CARD_REVISION_ID     0x10000
 523 #define HALP_CHECK_CARD_SUBVENDOR_ID    0x20000
 524 #define HALP_CHECK_CARD_SUBSYSTEM_ID    0x40000
 525
 526 //
 527 // Mm PTE/PDE to Hal PTE/PDE
 528 //
 529 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 530 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 531
 532 typedef struct _IDTUsageFlags
 533 {
 534     UCHAR Flags;
 535 } IDTUsageFlags;
 536
 537 typedef struct
 538 {
 539     KIRQL Irql;
 540     UCHAR BusReleativeVector;
 541 } IDTUsage;
 542
 543 typedef struct _HalAddressUsage
 544 {
 545     struct _HalAddressUsage *Next;
 546     CM_RESOURCE_TYPE Type;
 547     UCHAR Flags;
 548     struct
 549     {
 550         ULONG Start;
 551         ULONG Length;
 552     } Element[];
 553 } ADDRESS_USAGE, *PADDRESS_USAGE;
 554
 555 /* adapter.c */
 556 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 557
 558 /* sysinfo.c */
 559 VOID
 560 NTAPI
 561 HalpRegisterVector(IN UCHAR Flags,
 562                    IN ULONG BusVector,
 563                    IN ULONG SystemVector,
 564                    IN KIRQL Irql);
 565
 566 VOID
 567 NTAPI
 568 HalpEnableInterruptHandler(IN UCHAR Flags,
 569                            IN ULONG BusVector,
 570                            IN ULONG SystemVector,
 571                            IN KIRQL Irql,
 572                            IN PVOID Handler,
 573                            IN KINTERRUPT_MODE Mode);
 574
 575 /* pic.c */
 576 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 577 VOID __cdecl HalpApcInterrupt(VOID);
 578 VOID __cdecl HalpDispatchInterrupt(VOID);
 579 PHAL_SW_INTERRUPT_HANDLER __cdecl HalpDispatchInterrupt2(VOID);
 580 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 581 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 582
 583 /* profil.c */
 584 extern BOOLEAN HalpProfilingStopped;
 585
 586 /* timer.c */
 587 VOID NTAPI HalpInitializeClock(VOID);
 588 VOID __cdecl HalpClockInterrupt(VOID);
 589 VOID __cdecl HalpProfileInterrupt(VOID);
 590
 591 VOID
 592 NTAPI
 593 HalpCalibrateStallExecution(VOID);
 594
 595 /* pci.c */
 596 VOID HalpInitPciBus (VOID);
 597
 598 /* dma.c */
 599 VOID HalpInitDma (VOID);
 600
 601 /* Non-generic initialization */
 602 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 603 VOID HalpInitPhase1(VOID);
 604
 605 VOID
 606 NTAPI
 607 HalpFlushTLB(VOID);
 608
 609 //
 610 // KD Support
 611 //
 612 VOID
 613 NTAPI
 614 HalpCheckPowerButton(
 615     VOID
 616 );
 617
 618 VOID
 619 NTAPI
 620 HalpRegisterKdSupportFunctions(
 621     VOID
 622 );
 623
 624 NTSTATUS
 625 NTAPI
 626 HalpSetupPciDeviceForDebugging(
 627     IN PVOID LoaderBlock,
 628     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 629 );
 630
 631 NTSTATUS
 632 NTAPI
 633 HalpReleasePciDeviceForDebugging(
 634     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 635 );
 636
 637 //
 638 // Memory routines
 639 //
 640 ULONG64
 641 NTAPI
 642 HalpAllocPhysicalMemory(
 643     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 644     IN ULONG64 MaxAddress,
 645     IN PFN_NUMBER PageCount,
 646     IN BOOLEAN Aligned
 647 );
 648
 649 PVOID
 650 NTAPI
 651 HalpMapPhysicalMemory64Vista(
 652     IN PHYSICAL_ADDRESS PhysicalAddress,
 653     IN PFN_COUNT PageCount,
 654     IN BOOLEAN FlushCurrentTLB
 655 );
 656
 657 VOID
 658 NTAPI
 659 HalpUnmapVirtualAddressVista(
 660     IN PVOID VirtualAddress,
 661     IN PFN_COUNT NumberPages,
 662     IN BOOLEAN FlushCurrentTLB
 663 );
 664
 665 PVOID
 666 NTAPI
 667 HalpMapPhysicalMemory64(
 668     IN PHYSICAL_ADDRESS PhysicalAddress,
 669     IN PFN_COUNT PageCount
 670 );
 671
 672 VOID
 673 NTAPI
 674 HalpUnmapVirtualAddress(
 675     IN PVOID VirtualAddress,
 676     IN PFN_COUNT NumberPages
 677 );
 678
 679 /* sysinfo.c */
 680 NTSTATUS
 681 NTAPI
 682 HaliQuerySystemInformation(
 683     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 684     IN ULONG BufferSize,
 685     IN OUT PVOID Buffer,
 686     OUT PULONG ReturnedLength
 687 );
 688
 689 NTSTATUS
 690 NTAPI
 691 HaliSetSystemInformation(
 692     IN HAL_SET_INFORMATION_CLASS InformationClass,
 693     IN ULONG BufferSize,
 694     IN OUT PVOID Buffer
 695 );
 696
 697 //
 698 // BIOS Routines
 699 //
 700 BOOLEAN
 701 NTAPI
 702 HalpBiosDisplayReset(
 703     VOID
 704 );
 705
 706 VOID
 707 FASTCALL
 708 HalpExitToV86(
 709     PKTRAP_FRAME TrapFrame
 710 );
 711
 712 VOID
 713 __cdecl
 714 HalpRealModeStart(
 715     VOID
 716 );
 717
 718 //
 719 // Processor Halt Routine
 720 //
 721 VOID
 722 NTAPI
 723 HaliHaltSystem(
 724     VOID
 725 );
 726
 727 //
 728 // CMOS Routines
 729 //
 730 VOID
 731 NTAPI
 732 HalpInitializeCmos(
 733     VOID
 734 );
 735
 736 UCHAR
 737 NTAPI
 738 HalpReadCmos(
 739     IN UCHAR Reg
 740 );
 741
 742 VOID
 743 NTAPI
 744 HalpWriteCmos(
 745     IN UCHAR Reg,
 746     IN UCHAR Value
 747 );
 748
 749 //
 750 // Spinlock for protecting CMOS access
 751 //
 752 VOID
 753 NTAPI
 754 HalpAcquireCmosSpinLock(
 755     VOID
 756 );
 757
 758 VOID
 759 NTAPI
 760 HalpReleaseCmosSpinLock(
 761     VOID
 762 );
 763
 764 VOID
 765 NTAPI
 766 HalpInitializeLegacyPICs(
 767     VOID
 768 );
 769
 770 NTSTATUS
 771 NTAPI
 772 HalpOpenRegistryKey(
 773     IN PHANDLE KeyHandle,
 774     IN HANDLE RootKey,
 775     IN PUNICODE_STRING KeyName,
 776     IN ACCESS_MASK DesiredAccess,
 777     IN BOOLEAN Create
 778 );
 779
 780 VOID
 781 NTAPI
 782 HalpGetNMICrashFlag(
 783     VOID
 784 );
 785
 786 BOOLEAN
 787 NTAPI
 788 HalpGetDebugPortTable(
 789     VOID
 790 );
 791
 792 VOID
 793 NTAPI
 794 HalpReportSerialNumber(
 795     VOID
 796 );
 797
 798 NTSTATUS
 799 NTAPI
 800 HalpMarkAcpiHal(
 801     VOID
 802 );
 803
 804 VOID
 805 NTAPI
 806 HalpBuildAddressMap(
 807     VOID
 808 );
 809
 810 VOID
 811 NTAPI
 812 HalpReportResourceUsage(
 813     IN PUNICODE_STRING HalName,
 814     IN INTERFACE_TYPE InterfaceType
 815 );
 816
 817 ULONG
 818 NTAPI
 819 HalpIs16BitPortDecodeSupported(
 820     VOID
 821 );
 822
 823 NTSTATUS
 824 NTAPI
 825 HalpQueryAcpiResourceRequirements(
 826     OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
 827 );
 828
 829 VOID
 830 FASTCALL
 831 KeUpdateSystemTime(
 832     IN PKTRAP_FRAME TrapFrame,
 833     IN ULONG Increment,
 834     IN KIRQL OldIrql
 835 );
 836
 837 VOID
 838 NTAPI
 839 HalpInitBusHandlers(
 840     VOID
 841 );
 842
 843 NTSTATUS
 844 NTAPI
 845 HaliInitPnpDriver(
 846     VOID
 847 );
 848
 849 VOID
 850 NTAPI
 851 HalpDebugPciDumpBus(
 852     IN ULONG i,
 853     IN ULONG j,
 854     IN ULONG k,
 855     IN PPCI_COMMON_CONFIG PciData
 856 );
 857
 858 VOID
 859 NTAPI
 860 HalpInitProcessor(
 861     IN ULONG ProcessorNumber,
 862     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 863 );
 864
 865 #ifdef _M_AMD64
 866 #define KfLowerIrql KeLowerIrql
 867 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
 868 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
 869 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
 870 #ifndef CONFIG_SMP
 871 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 872 #define KiAcquireSpinLock(SpinLock)
 873 #define KiReleaseSpinLock(SpinLock)
 874 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 875 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 876 #endif // !CONFIG_SMP
 877 #endif // _M_AMD64
 878
 879 extern BOOLEAN HalpNMIInProgress;
 880
 881 extern ADDRESS_USAGE HalpDefaultIoSpace;
 882
 883 extern KSPIN_LOCK HalpSystemHardwareLock;
 884
 885 extern PADDRESS_USAGE HalpAddressUsageList;
 886
 887 extern LARGE_INTEGER HalpPerfCounter;
 888
 889 extern KAFFINITY HalpActiveProcessors;
 890
 891 extern BOOLEAN HalDisableFirmwareMapper;
 892 extern PWCHAR HalHardwareIdString;
 893 extern PWCHAR HalName;
 894
 895 extern KAFFINITY HalpDefaultInterruptAffinity;
 896
 897 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
 898
 899 extern const USHORT HalpBuildType;